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1. 发明授权

US09418733B2 Joint short-time and long-time storage device and storage method thereof 有权
标题翻译：联合短时和长时间存储设备及其存储方法
公开(公告)号：US09418733B2
公开(公告)日：2016-08-16
申请号：US14800693
申请日：2015-07-15
申请人： Huazhong University of Science and Technology
发明人： Xiangshui Miao , Yi Li , Yingpeng Zhong , Lei Xu , Huajun Sun , Xiaohua Xu
IPC分类号： G11C11/00 , G11C13/00 , H01L45/00 , G11C14/00 , G11C11/54
CPC分类号： G11C13/0004 , G11C11/005 , G11C11/54 , G11C13/0002 , G11C13/0011 , G11C13/0033 , G11C13/0035 , G11C13/0069 , G11C13/0097 , G11C14/00 , G11C2013/0092 , H01L45/06 , H01L45/085 , H01L45/1233 , H01L45/1253 , H01L45/142 , H01L45/143 , H01L45/144
摘要： A joint short-time and long-time storage device, including a first electrode layer, a functional material layer connected to the first electrode layer, and a second electrode layer connected to the functional material layer. The first electrode layer is made of inert conductive metal, the second electrode layer is made of active conductive metal, and the functional material layer is made of chalcogenide.
摘要翻译：一种联合的短时和长时间存储装置，包括第一电极层，连接到第一电极层的功能材料层和连接到功能材料层的第二电极层。第一电极层由惰性导电金属制成，第二电极层由有源导电金属制成，功能材料层由硫族化物制成。

2. 发明授权

US11531880B2 Memory-based convolutional neural network system 有权
公开(公告)号：US11531880B2
公开(公告)日：2022-12-20
申请号：US16464977
申请日：2018-06-07
申请人： Huazhong University of Science and Technology
发明人： Yi Li , Wenqian Pan , Xiangshui Miao
IPC分类号： G06N3/08 , G06N3/04 , G06N3/063
摘要： A memory-based CNN, includes an input module, a convolution layer circuit module, a pooling layer circuit module, an activation function module, a fully connected layer circuit module, a softmax function module and an output module, convolution kernel values or synapse weights are stored in the NOR FLASH units; the input module converts an input signal into a voltage signal required by the convolutional neural network; the convolutional layer circuit module convolves the voltage signal corresponding to the input signal with the convolution kernel values, and transmits the result to the activation function module; the activation function module activates the signal; the pooling layer circuit module performs a pooling operation on the activated signal; the fully connected layer circuit module multiplies the pooled signal with the synapse weights to achieve classification; the softmax function module normalizes the classification result into probability values as an output of the entire network.

3. 发明授权

US11475949B2 Computing array based on 1T1R device, operation circuits and operating methods thereof 有权
公开(公告)号：US11475949B2
公开(公告)日：2022-10-18
申请号：US16336900
申请日：2018-06-07
申请人： HUAZHONG UNIVERSITY OF SCIENCE AND TECHNOLOGY
发明人： Yi Li , Zhuorui Wang , Xiangshui Miao , Yaxiong Zhou , Long Cheng
IPC分类号： G11C11/00 , G11C13/00 , G06F7/48 , H03K19/21
摘要： The present invention discloses a computing array based on 1T1R device, operation circuits and operating methods thereof. The computing array has 1T1R arrays and a peripheral circuit; the 1T1R array is configured to achieve operation and storage of an operation result, and the peripheral circuit is configured to transmit data and control signals to control operation and storage processes of the 1T1R arrays; the operation circuits are respectively configured to implement a 1-bit full adder, a multi-bit step-by-step carry adder and optimization design thereof, a 2-bit data selector, a multi-bit carry select adder and a multi-bit pre-calculation adder; and in the operating method corresponding to the operation circuit, initialized resistance states of the 1T1R devices, word line input signals, bit line input signals and source line input signals are controlled to complete corresponding operation and storage processes.

4. 发明授权

US11416744B2 Max pooling processor based on 1T1R memory 有权
公开(公告)号：US11416744B2
公开(公告)日：2022-08-16
申请号：US16631840
申请日：2019-07-12
申请人： HUAZHONG UNIVERSITY OF SCIENCE AND TECHNOLOGY
发明人： Yi Li , Rui Kuang , Xiang-Shui Miao
IPC分类号： G11C11/54 , G06N3/08 , G06N3/04 , G11C13/00
摘要： The present disclosure belongs to the technical field of artificial neural networks, and provides to a max pooling processor based on 1T1R memory, comprising an input module, a max pooling operation module, and an output module; the input module is configured to transmit an operating voltage according to the convolution result in the convolutional neural network; the 1T1R memory in the max pooling operation module is configured to adjust a conductance value of the RRAM according to the gate voltage of the transistor therein to achieve the max pooling operation by using the non-volatile multi-value conductance regulation characteristic of the RRAM, and store a max pooling result; and the output module is configured to read the max pooling result and output it.

5. 发明授权

US09564218B2 Associative memory circuit 有权
标题翻译：关联存储器电路
公开(公告)号：US09564218B2
公开(公告)日：2017-02-07
申请号：US14601216
申请日：2015-01-20
申请人： Huazhong University of Science and Technology
发明人： Xiangshui Miao , Yi Li , Lei Xu , Yingpeng Zhong
IPC分类号： G11C15/04 , G11C11/54 , G11C13/00
CPC分类号： G11C15/046 , G11C11/54 , G11C13/0007
摘要： An associative memory circuit including a first memristor, a second memristor, a fixed value resistor R, and an operational comparator. One terminal of the first memristor is a first input terminal of the associative memory circuit, and the other terminal of the first memristor is connected to a first input terminal of the operational comparator. One terminal of the second memristor is a second input terminal of the associative memory circuit, and the other terminal of the second memristor is connected to the first input terminal of the operational comparator. One terminal of the fixed value resistor is connected to the first input terminal of the operational comparator, and the other terminal of the fixed value resistor is connected to the ground. A second input terminal of the operational comparator is connected to a reference voltage.
摘要翻译：一种包括第一忆阻器，第二忆阻器，固定值电阻器R和操作比较器的关联存储器电路。第一忆阻器的一个端子是相关存储器电路的第一输入端，并且第一忆阻器的另一端连接到操作比较器的第一输入端。第二忆阻器的一个端子是关联存储器电路的第二输入端，并且第二忆阻器的另一端连接到运算比较器的第一输入端。固定值电阻的一端连接到运算比较器的第一输入端，固定值电阻的另一端连接到地。操作比较器的第二输入端连接到参考电压。

6. 发明授权

US09369130B2 Nonvolatile logic gate circuit based on phase change memory 有权
标题翻译：基于相变存储器的非易失逻辑门电路
公开(公告)号：US09369130B2
公开(公告)日：2016-06-14
申请号：US14706004
申请日：2015-05-07
申请人： Huazhong University of Science and Technology
发明人： Xiangshui Miao , Yi Li , Yingpeng Zhong , Lei Xu , Huajun Sun , Xiaomin Cheng
IPC分类号： H03K19/003 , G11C13/00 , H03K19/173 , H03K19/20 , H03K19/177
CPC分类号： H03K19/00346 , G11C13/0004 , G11C13/004 , H03K19/1733 , H03K19/17724 , H03K19/20
摘要： A nonvolatile logic gate circuit based on phase change memories, including a first phase change memory, a second phase change memory, a first controllable switch element and a first resistor, wherein a first end of the first phase change memory serves as a first input end of an AND gate circuit, a first end of the second phase change memory serves as a second input end of the AND gate circuit, a first end of the first controllable switch element is connected to a second end of the first phase change memory, a second end of the first controllable switch element is grounded; one end of the first resistor is connected to the first end of the second phase change memory, the other end of the first resistor is grounded; and the first end of the second phase change memory serves as an output end of the AND gate circuit.
摘要翻译：一种基于相变存储器的非易失性逻辑门电路，包括第一相变存储器，第二相变存储器，第一可控开关元件和第一电阻器，其中第一相变存储器的第一端用作第一输入端和门电路的第一端，第二相变存储器的第一端用作与门电路的第二输入端，第一可控开关元件的第一端连接到第一相变存储器的第二端，第一可控开关元件的第二端接地; 第一电阻器的一端连接到第二相变存储器的第一端，第一电阻器的另一端接地; 并且第二相变存储器的第一端用作与门电路的输出端。

7. 发明授权

US09473137B2 Non-volatile boolean logic operation circuit and operation method thereof 有权
标题翻译：非易失性布尔逻辑运算电路及其运算方法
公开(公告)号：US09473137B2
公开(公告)日：2016-10-18
申请号：US14867030
申请日：2015-09-28
申请人： Huazhong University of Science and Technology
发明人： Xiangshui Miao , Yaxiong Zhou , Yi Li , Huajun Sun
IPC分类号： H03K19/00 , H03K19/20 , H03K19/08
CPC分类号： H03K19/0002 , H03K19/0021 , H03K19/0813 , H03K19/20
摘要： A non-volatile Boolean logic operation circuit, including: two input ends; an output end; a first resistive switching element M1, the first resistive switching element M including a positive electrode and a negative electrode; and a second resistive switching element M2, the second resistive switching element M2 including a positive electrode and a negative electrode. The negative electrode of the first resistive switching element M1 operates as a first input end of the logic operation circuit. The negative electrode of the second resistive switching element M2 operates as a second input end of the logic operation circuit. The positive electrode of the second resistive switching element M2 is connected to the positive electrode of the first resistive switching element M1, and a connected end thereof operates as the output end of the logic operation circuit.
摘要翻译：一种非易失性布尔逻辑运算电路，包括：两个输入端; 输出端第一电阻式开关元件M1，第一电阻式开关元件M包括正极和负极; 和第二电阻开关元件M2，第二电阻开关元件M2包括正极和负极。第一电阻式开关元件M1的负电极作为逻辑运算电路的第一输入端工作。第二电阻开关元件M2的负极作为逻辑运算电路的第二输入端工作。第二电阻开关元件M2的正极与第一电阻式开关元件M1的正极连接，其连接端作为逻辑运算电路的输出端。

8. 发明授权

US11200949B2 Multiplier and operation method based on 1T1R memory 有权
公开(公告)号：US11200949B2
公开(公告)日：2021-12-14
申请号：US16971678
申请日：2019-07-12
申请人： HUAZHONG UNIVERSITY OF SCIENCE AND TECHNOLOGY
发明人： Xiangshui Miao , Yi Li , Xiaodi Huang
IPC分类号： G11C11/00 , G11C13/00 , G06F7/523 , G11C7/10
摘要： The invention discloses a multiplier and an operation method based on 1T1R memory. The multiplier includes: a 1T1R crossbar A1, a 1T1R crossbar A2, a 1T1R crossbar A3, and a peripheral circuit. The 1T1R matrices are configured to realize operation and store result of it, and the peripheral circuit is configured to transfer data and control signals, thereby controlling the operation and storage process of the 1T1R matrices. An operation circuit is configured to respectively achieve NOR Boolean logic operations, two-bit binary multipliers, and optimization. The operation method corresponding to the operation circuit respectively completes the corresponding calculation and storage process by controlling an initialization resistance state of 1T1R devices, the size of a word line input signal, the size of a bit line input signal, and the size of a source line input signal.

9. 发明授权

US11171650B2 Reversible logic circuit and operation method thereof 有权
公开(公告)号：US11171650B2
公开(公告)日：2021-11-09
申请号：US16965602
申请日：2019-07-16
申请人： HUAZHONG UNIVERSITY OF SCIENCE AND TECHNOLOGY
发明人： Yi Li , Long Cheng , Xiangshui Miao
IPC分类号： H03K19/177 , H03K19/173
摘要： A reversible logic circuit and an operation method thereof are provided. The logic circuit includes resistive switching cells, word lines, and bit lines. The word lines and the bit lines are perpendicular to each other. The anode of a resistive switching cell is connected to the word line as a first input terminal to apply logic operating voltage or be grounded. The cathode of a resistive switching cell is connected to the bit line as a second input terminal to apply logic operating voltage or be grounded. When performing reversible logic operation, four levels of resistance states of the resistive switching cell are used as logic outputs to implement single-input NOT and dual-input C-NOT reversible logic functions.

10. 发明授权

US10020054B2 Memristor-based processor integrating computing and memory and method for using the processor 有权
公开(公告)号：US10020054B2
公开(公告)日：2018-07-10
申请号：US15629714
申请日：2017-06-21
申请人： HUAZHONG UNIVERSITY OF SCIENCE AND TECHNOLOGY
发明人： Qun Liu , Tao Zhang , Xiangshui Miao , Yi Li , Yaxiong Zhou , Tianpeng Miao
IPC分类号： G06F12/0813 , G11C13/00
CPC分类号： G11C13/0069 , G11C13/0007 , G11C13/0097 , G11C2213/77
摘要： A processor including a computing and memory structure including X in number integration units and X in number communication units, and a control unit. The integration units are computing and memory units (CMUs), each computing and memory unit (CMU) is connected to a corresponding communication unit. The control unit is configured to produce control signals according to the commands, connect communication networks between the CMUs, choose operand addresses and result storage addresses, and search for one or a plurality of idle CMUs when extra CMUs are required for an operation. Each computing and memory unit includes M in number bit units and M−1 in number vertical line switches. Each bit unit includes a resistor, a horizontal line switch and N in number memristors. X is a positive integer greater than or equal to 2; M is a positive integer greater than or equal to 1.

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