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1. 发明授权

US5453718A Differential amplifier for reducing input capacitance without deterorating noise characteristics 失效
标题翻译：用于降低输入电容的差分放大器，不会阻碍噪声特性
公开(公告)号：US5453718A
公开(公告)日：1995-09-26
申请号：US284122
申请日：1994-08-02
申请人： Katuyuki Kurokawa , Takehiko Umeyama , Masayasu Tanaka
发明人： Katuyuki Kurokawa , Takehiko Umeyama , Masayasu Tanaka
IPC分类号： H03F3/45
CPC分类号： H03F3/4521 , H03F3/45089 , H03F2203/45024 , H03F2203/45031 , H03F2203/45302 , H03F2203/45366 , H03F2203/45584 , H03F2203/45594 , H03F2203/45702
摘要： A differential amplifier (101) includes an input circuit (20), a bias circuit (31) and an output circuit (50). In the input circuit (20), when base potentials of transistors (Q1) and (Q2) change respectively by .DELTA.V and -.DELTA.V thereby changing current flowing through the transistors (Q1) and (Q2) by .DELTA.I and -.DELTA.I, respectively, base-emitter voltages of transistors (Q5) and (Q9) equally increase by .DELTA.V in the bias circuit (31). However, since a base potential of the transistor (Q5) is fixed, an emitter potential of the transistor (Q9) drops by 2.DELTA.V, decreasing a base potential of a transistor (Q4) by 2.DELTA.V. On the other hand, since a current flowing through the transistor (Q4) changes by -.DELTA.I, a base-emitter voltage of the transistor (Q4) accordingly falls by .DELTA.V. This reduces an emitter potential of the transistor (Q4), i.e., a collector potential of the transistor (Q2) by .DELTA.V, and hence, a base-emitter voltage of the transistor (Q2) stays unchanged. Thus, Miller effect is prevented and an input capacitance is reduced.
摘要翻译：差分放大器（101）包括输入电路（20），偏置电路（31）和输出电路（50）。在输入电路（20）中，当晶体管（Q1）和（Q2）的基极电位分别改变DELTA V和-TATA V，从而改变流过晶体管（Q1）和（Q2）的电流DELTA I和DELTA I 晶体管（Q5）和（Q9）的基极 - 发射极电压分别在偏置电路（31）中增加DELTA V. 然而，由于晶体管（Q5）的基极电位是固定的，所以晶体管（Q9）的发射极电位下降2VTAV，将晶体管（Q4）的基极电位降低2VTA。另一方面，由于流过晶体管（Q4）的电流改变了-ΔTA，所以晶体管（Q4）的基极 - 发射极电压相应地下降了DELTA V.这降低了晶体管（Q4）的发射极电位，即集电极电位（Q2）的晶体管（Q2）的晶体管（Q2）的基极 - 发射极电压保持不变。因此，可以防止米勒效应，降低输入电容。

2. 发明授权

US5886577A Apparatus for efficient current amplification 失效
标题翻译：用于高效电流放大的装置
公开(公告)号：US5886577A
公开(公告)日：1999-03-23
申请号：US900146
申请日：1997-07-28
申请人： Pierce V. Keating
发明人： Pierce V. Keating
IPC分类号： H03F3/45 , H03F3/50 , H03F3/68
CPC分类号： H03F3/4508 , H03F3/45085 , H03F3/50 , H03F2203/45584 , H03F2203/45631 , H03F2203/45641
摘要： Two emitter follower transistors (260, 250), in which each transistor has an emitter coupled to one of the collectors of a differential pair structure (230, 240)to form two stacked transistor pairs (260, 230) and (250, 240). A first differential signal (IN, INX) is positive supply referenced (Vcc) and is coupled to the bases of the emitter follower transistors (250, 260). A second differential input signal (275, 295) is coupled to the bases of the differential pair transistors (230, 240). The second differential input signal (275, 295) is identical to the first input signal but also includes a voltage level shift from the positive supply (Vcc). The first and second input signal portions are coupled to the transistors which make up the stacked transistor pair (260, 230) and (250, 240) and are chosen so that they are 180 degrees out of phase.
摘要翻译：两个射极跟随器晶体管（260,250），其中每个晶体管具有耦合到差分对结构（230,240）的集电极之一的发射极，以形成两个堆叠的晶体管对（260,230）和（250,240）。第一差分信号（IN，INX）为正电源（Vcc），并耦合到发射极跟随器晶体管（250,260）的基极。第二差分输入信号（275,295）耦合到差分对晶体管（230,240）的基极。第二差分输入信号（275,295）与第一输入信号相同，但也包括从正电源（Vcc）的电压电平移位。第一和第二输入信号部分耦合到构成堆叠晶体管对（260,230）和（250,240）的晶体管，并被选择为使它们相位相差180度。

3. 发明授权

US5812026A Differential amplifier with improved voltage gain 失效
标题翻译：差分放大器具有改善的电压增益
公开(公告)号：US5812026A
公开(公告)日：1998-09-22
申请号：US705596
申请日：1996-08-30
申请人： Alexander Fairgrieve
发明人： Alexander Fairgrieve
IPC分类号： H03F3/45
CPC分类号： H03F3/45085 , H03F2203/45352 , H03F2203/45584 , H03F2203/45641 , H03F2203/45648 , H03F2203/45696
摘要： A circuit used with a differential amplifier to eliminate the effect of Early Voltage from voltage gain provided by the differential amplifier. With a differential amplifier utilizing PNP transistors which experience the lowest, and most undesirable Early Voltage, the circuitry includes a pair of transistors 400 and 402, each with a base connected to an input of the differential amplifier corresponding to a similar base connection of a respective one of transistors 100 and 102 of the differential amplifier, an emitter connected to a current source, and a collector connected to the collector of a respective one of NPN current sink transistors 306 and 308 connected at outputs of the differential amplifier. The circuitry for elimination of Early Voltage further includes components to assure the collector voltages of transistors 400 and 402 are equal and the collector voltages of transistors 102 and 400 are equal. In addition to circuitry for elimination of Early Voltage when PNP transistors 100 and 102 are used to provide the differential amplifier inputs, the circuitry may also be configured for use when NPN transistors provide inputs for a differential amplifier.
摘要翻译：与差分放大器一起使用的电路，以消除由差分放大器提供的电压增益对早期电压的影响。利用利用PNP晶体管的差分放大器，其经历最低和最不期望的早期电压，该电路包括一对晶体管400和402，每个晶体管400和402各自具有连接到差分放大器的输入，该输入对应于相应的基本连接差分放大器的晶体管100和102中的一个，连接到电流源的发射极和连接到差分放大器的输出处的NPN电流吸收晶体管306和308中的相应一个的集电极的集电极。用于消除早期电压的电路还包括确保晶体管400和402的集电极电压相等并且晶体管102和400的集电极电压相等的组件。除了使用PNP晶体管100和102用于提供差分放大器输入以消除早期电压的电路之外，还可以将电路配置为在NPN晶体管为差分放大器提供输入时使用。

4. 发明授权

US06344762B1 Bias circuit for a low voltage differential circuit 失效
标题翻译：用于低压差分电路的偏置电路
公开(公告)号：US06344762B1
公开(公告)日：2002-02-05
申请号：US09747321
申请日：2000-12-21
申请人： John S. Prentice
发明人： John S. Prentice
IPC分类号： H03K522
CPC分类号： H03F3/45556 , H03F2203/45464 , H03F2203/45584 , H03F2203/45596 , H03K5/2418
摘要： A bias circuit that provides biasing for a differential circuit. The bias circuitincludes first and second transistors, first and second impedance devices, a reference current source and an amplifier. The first and second transistors each have a control input and a current path coupled between a first node and ground, where the control inputs of the first and second transistors receive the differential signal. The impedance devices are each coupled between a control input of one of the first and second transistors and a second node. The reference current source provides a reference current for the first node and the amplifier has an input coupled to the first node and an output coupled to the second node. The transistors of the bias circuit and the differential circuit may be matched, NPN bipolar junction transistors with emitters connected to ground. A filter capacitor may be coupled between the first node and ground and operates as a low pass filter.
摘要翻译：偏置电路，为差分电路提供偏置。偏置电路包括第一和第二晶体管，第一和第二阻抗器件，参考电流源和放大器。第一和第二晶体管各自具有耦合在第一节点和地之间的控制输入和电流路径，其中第一和第二晶体管的控制输入接收差分信号。阻抗器件各自耦合在第一和第二晶体管之一的控制输入端和第二节点之间。参考电流源为第一节点提供参考电流，并且放大器具有耦合到第一节点的输入和耦合到第二节点的输出。偏置电路和差分电路的晶体管可以匹配，具有连接到地的发射极的NPN双极结型晶体管。滤波电容器可以耦合在第一节点和地之间并作为低通滤波器工作。

5. 发明授权

US5910736A Differential-type data transmitter 失效
标题翻译：差分式数据发射机
公开(公告)号：US5910736A
公开(公告)日：1999-06-08
申请号：US733636
申请日：1996-10-17
申请人： Junichi Nagata , Junji Hayakawa
发明人： Junichi Nagata , Junji Hayakawa
IPC分类号： H03K5/08 , H03F3/45 , H04L25/02 , H03K19/086
CPC分类号： H03F3/45085 , H03F3/45551 , H03F2203/45031 , H03F2203/45188 , H03F2203/45272 , H03F2203/45352 , H03F2203/45561 , H03F2203/45584 , H03F2203/45612 , H03F2203/45674
摘要： A differential-type data transmitter includes a differential amplifier pair (T1, T2, T4, T6, T8) having a plurality of transistors and receiving a pair of a first input signal and a second input signal. A load (T3, T5, T7) is connected to the differential amplifier pair. A detection circuit (T9, T10, I4, I5, I6, I7) connected to a junction between the differential amplifier pair and the load is operative for detecting whether or not the first and second input signals are outside a common-mode input voltage range with respect to the differential amplifier pair. A first output circuit (T12) connected to the detection circuit is operative for outputting a signal depending on an output signal from the differential amplifier pair. The signal outputted from the first output circuit is set to a given level when the detection circuit detects that the first and second input signals are outside the conmmon-mode input voltage range. A second output circuit (T11) connected to the detection circuit is operative for outputting a detection signal representing whether or not the detection circuit detects that the first and second input signals are outside the common-mode input voltage range.
摘要翻译：差分型数据发送器包括具有多个晶体管并且接收一对第一输入信号和第二输入信号的差分放大器对（T1，T2，T4，T6，T8）。负载（T3，T5，T7）连接到差分放大器对。连接到差分放大器对和负载之间的结点的检测电路（T9，T10，I4，I5，I6，I7）可操作用于检测第一和第二输入信号是否在共模输入电压范围之外相对于差分放大器对。连接到检测电路的第一输出电路（T12）用于根据来自差分放大器对的输出信号输出信号。当检测电路检测到第一和第二输入信号在辅助模式输入电压范围之外时，从第一输出电路输出的信号被设置为给定电平。连接到检测电路的第二输出电路（T11）用于输出表示检测电路是否检测到第一和第二输入信号在共模输入电压范围之外的检测信号。

6. 发明授权

US5699010A Differential amplifier circuit 失效
标题翻译：差分放大电路
公开(公告)号：US5699010A
公开(公告)日：1997-12-16
申请号：US667708
申请日：1996-06-21
申请人： Kazuomi Hatanaka
发明人： Kazuomi Hatanaka
IPC分类号： H03F1/32 , H03F3/45
CPC分类号： H03F3/45098 , H03F1/3211 , H03F2203/45561 , H03F2203/45584 , H03F2203/45612 , H03F2203/45702
摘要： At the input sides of matched first and second differential amplifiers 11 and 12, first and second input buffers 21 and 22, and third and fourth input buffers 23 and 24 are respectively connected. In input transistors Q5 and Q8 in the first and second input buffers 21 and 22, emitter currents corresponding to the collector currents of differential transistors Q3 and Q4 of the second differential amplifier 12 flow by using current mirror circuits. Changes of base-emitter voltage of the PNP transistors Q5 and Q8, and changes of base-emitter voltage of NPN transistors Q1 and Q2 cancel each other, and an output voltage improved in linearity is obtained between a negative phase output terminal 33 and a positive phase output terminal 34.
摘要翻译：在匹配的第一和第二差分放大器11和12的输入侧，分别连接有第一和第二输入缓冲器21和22以及第三和第四输入缓冲器23和24。在第一和第二输入缓冲器21和22中的输入晶体管Q5和Q8中，与第二差分放大器12的差分晶体管Q3和Q4的集电极电流相对应的发射极电流通过使用电流镜电路流动。 PNP晶体管Q5和Q8的基极 - 发射极电压的变化以及NPN晶体管Q1和Q2的基极 - 发射极电压的变化彼此抵消，并且在负相输出端子33和正极之间获得线性改善的输出电压相输出端子34。

7. 发明授权

US5572165A Amplifier arrangements 失效
标题翻译：放大器布置
公开(公告)号：US5572165A
公开(公告)日：1996-11-05
申请号：US295620
申请日：1994-08-25
申请人： Arshad Madni
发明人： Arshad Madni
IPC分类号： H03F1/48 , H03F3/45
CPC分类号： H03F3/4521 , H03F1/48 , H03F3/45089 , H03F2203/45366 , H03F2203/45371 , H03F2203/45392 , H03F2203/45584 , H03F2203/45641 , H03F2203/45702
摘要： An amplifier arrangement comprising a plurality of similar amplifier stages to which input signal voltages are applied in common, the output signal voltages being summed to retain bandwidth at the expense of gain compared with cascaded stages. The individual stages of the arrangement may be cascoded amplifier stages.
摘要翻译：一种放大器装置，包括多个类似的放大器级，输入信号电压被共同施加到输入信号电压，输出信号电压被相加以相对于级联级以牺牲增益为代价来保持带宽。该装置的各个阶段可以是级联的放大器级。

8. 发明授权

US07170347B1 Offset trim circuit and method for a constant-transconductance rail-to-rail CMOS input circuit 有权
标题翻译：用于恒定跨导轨至轨CMOS输入电路的偏置微调电路和方法
公开(公告)号：US07170347B1
公开(公告)日：2007-01-30
申请号：US10716019
申请日：2003-11-17
申请人： Willem Johannes Kindt
发明人： Willem Johannes Kindt
IPC分类号： H03F3/45
CPC分类号： H03F3/45183 , H03F3/45695 , H03F2200/456 , H03F2203/45366 , H03F2203/45564 , H03F2203/45584 , H03F2203/45588
摘要： A constant-transconductance rail-to-rail CMOS input circuit with offset trim is provided. PMOS and NMOS differential trim stages are scaled versions of PMOS and NMOS input stages respectively. The differential trim stages are configured to adjust the offset of the differential output current with accuracy over temperature. A first current mirror circuit is configured to receive a fraction of a bias current (βI), where β is related to the input common mode voltage. A second current mirror circuit is configured to receive another fraction of the bias current ((1−β)I). The first current mirror circuit is configured to provide current βI to the PMOS input stage, and a scaled-down version of current βI to the PMOS differential trim stage. The second current mirror circuit is configured to provide current ((1−β)I) to the NMOS input stage, and a scaled-down version of current ((1−β)I) to the differential PMOS trim stage.
摘要翻译：提供了具有偏移微调的恒定跨导轨至轨CMOS输入电路。 PMOS和NMOS差分微调级分别是PMOS和NMOS输入级的缩放版本。差分微调级配置为在温度范围内精确调整差分输出电流的偏移。第一电流镜电路被配置为接收一部分偏置电流（βI），其中β与输入共模电压相关。第二电流镜电路被配置为接收另一部分偏置电流（（1-β）I））。第一电流镜电路被配置为向PMOS输入级提供电流βI，并将电流βI的缩小版本提供给PMOS差分微调级。第二电流镜电路被配置为向NMOS输入级提供电流（（1-β）I），并将电流（（1-β）I）的缩小版本提供给差分PMOS修调级。

9. 发明授权

US06710659B2 Variable-gain amplifier with stepwise controller 有权
标题翻译：具有逐步控制器的可变增益放大器
公开(公告)号：US06710659B2
公开(公告)日：2004-03-23
申请号：US10216873
申请日：2002-08-13
申请人： Makoto Teramoto , Mamoru Shimoda
发明人： Makoto Teramoto , Mamoru Shimoda
IPC分类号： H03G1108
CPC分类号： H03G1/0023 , H03F3/45103 , H03F2203/45302 , H03F2203/45311 , H03F2203/45366 , H03F2203/45466 , H03F2203/45508 , H03F2203/45584
摘要： In a conventional variable-gain amplifier, when high-frequency signals are fed in, leak current flows through the collector-emitter parasitic capacitance of transistors, making it impossible to attenuate the gain sufficiently. A variable-gain amplifier of the invention has a controller for controlling the operation of input transistors so as to reduce the leak current that flows through transistors because of their collector-emitter parasitic capacitance when high-frequency signals are fed in and thereby prevent saturation of gain attenuation. Another variable-gain amplifier of the invention has a plurality of variable-gain amplifier circuits connected in parallel, and has a current control circuit for controlling the bias current sources provided within each of the variable-gain amplifier circuits so as to reduce the leak current that flows through transistors because of their collector-emitter parasitic capacitance when high-frequency signals are fed in and thereby prevent saturation of gain attenuation.
摘要翻译：在常规的可变增益放大器中，当馈入高频信号时，漏电流流过晶体管的集电极 - 发射极寄生电容，使得不可能充分衰减增益。本发明的可变增益放大器具有用于控制输入晶体管的操作的控制器，以便在馈入高频信号时由于其集电极 - 发射极寄生电容而减小流过晶体管的漏电流，从而防止饱和增益衰减。本发明的另一个可变增益放大器具有并联连接的多个可变增益放大器电路，并且具有用于控制在每个可变增益放大器电路内提供的偏置电流源的电流控制电路，以便减少漏电流当高频信号被馈入时由于它们的集电极 - 发射极寄生电容而流过晶体管，从而防止增益衰减的饱和。

10. 发明授权

US06707339B1 Controlled bias current buffer and method thereof 有权
标题翻译：控制偏置电流缓冲器及其方法
公开(公告)号：US06707339B1
公开(公告)日：2004-03-16
申请号：US10301992
申请日：2002-11-22
申请人： Kiyoshi Kase , Joseph Y. Chan , Chunhe Zhao
发明人： Kiyoshi Kase , Joseph Y. Chan , Chunhe Zhao
IPC分类号： H03F345
CPC分类号： H03F3/3023 , H03F3/45183 , H03F2203/45454 , H03F2203/45584 , H03F2203/45658
摘要： An operational amplifier circuit (10) uses a first operational amplifier (16) to selectively provide a boosted drive current in response to an input signal voltage transitioning. The boosted driver current is used by a second operational amplifier (22) having a single high gain stage (76). The output drive current of the operational amplifier circuit (10) is increased to a predetermined maximum value for a predetermined time after an input signal transition in order to source increased current to a capacitive or inductive load only during output signal transitions. Separate current boost circuits (30, 70) in each of the first and second operational amplifiers enable early signal transition detection and ensure continuation of increased current until completion of the signal transition.
摘要翻译：运算放大器电路（10）使用第一运算放大器（16）来响应于输入信号电压转换来选择性地提供升压的驱动电流。升压的驱动器电流由具有单个高增益级（76）的第二运算放大器（22）使用。运算放大器电路（10）的输出驱动电流在输入信号转换之后的预定时间内增加到预定的最大值，以便仅在输出信号转换期间将电流增加到电容或电感性负载。第一和第二运算放大器中的每一个中的独立电流升压电路（30,70）可以实现早期的信号转换检测，并确保持续增加的电流，直到完成信号转换。

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