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1. 发明授权

US5867068A Frequency synthesizer using double resolution fractional frequency division 失效
$Frequency synthesizer using double resolution fractional frequency division$
标题翻译：频率合成器采用双分辨率小数分频
公开(公告)号：US5867068A
公开(公告)日：1999-02-02
申请号：US958505
申请日：1997-10-27
申请人： Pierce V. Keating
发明人： Pierce V. Keating
IPC分类号： H03K23/68 , H03L7/197 , H03K23/00 , H03K23/66 , H03L7/18
CPC分类号： H03L7/1978 , H03K23/68
摘要： A fractional frequency synthesizer (100) includes a symmetrical divider (165) having an output frequency signal (135) fractionalized based on half cycles of its input frequency signal (130). The divider (165) is provided with a divisor (145) that varies based on half cycles of the output signal. Preferably, the divider (165) operates to selectively add or subtract an increment, corresponding to one half cycle of the input frequency signal (130), to a half cycle of the output frequency signal (135).
摘要翻译：分数频率合成器（100）包括对称分频器（165），其具有基于其输入频率信号（130）的半个周期分数化的输出频率信号（135）。除法器（165）具有根据输出信号的半周期而变化的除数（145）。优选地，分频器（165）操作以选择性地将对应于输入频率信号（130）的一个半周期的增量减去到输出频率信号（135）的半个周期。

2. 发明授权

US5828237A Emitter coupled logic (ECL) gate and method of forming same 失效
标题翻译：发射极耦合逻辑（ECL）门及其形成方法
公开(公告)号：US5828237A
公开(公告)日：1998-10-27
申请号：US656543
申请日：1996-05-31
申请人： Pierce V. Keating
发明人： Pierce V. Keating
IPC分类号： H03K19/086
CPC分类号： H03K19/086
摘要： A fully differential, low voltage ECL gate (300) receives complementary logic signals (A, Ax, B, Bx) and provides them to first and second differential pairs (306, 318). Collectors from different differential pairs (306) and (318) are coupled together and provided with independent current paths through load resistors, R1, (336) and R2 (338). Differential outputs (OUT, OUTx) are generated at the common collector nodes (344, 346). The load resistors (336, 338) are selected to control the gain and ensure that a minimum switching threshold (V.sub.th) is maintained under all differential input signal conditions of (A, Ax, B, and Bx) for a logical AND or OR function.
摘要翻译：全差分低电压ECL门（300）接收互补逻辑信号（A，Ax，B，Bx）并将它们提供给第一和第二差分对（306,318）。来自不同差分对（306）和（318）的集电极耦合在一起，并且通过负载电阻R1，（336）和R2（338）提供独立的电流路径。差分输出（OUT，OUTx）在公共收集器节点（344,346）处产生。选择负载电阻（336,338）以控制增益，并确保在逻辑“或”或“（或）”功能的所有差分输入信号条件（A，Ax，B和Bx）下维持最小切换阈值（Vth）。

3. 发明授权

US5751169A Emitter coupled logic (ECL) gate which generates intermediate signals of four different voltages 失效
标题翻译：发射极耦合逻辑（ECL）门，产生四个不同电压的中间信号
公开(公告)号：US5751169A
公开(公告)日：1998-05-12
申请号：US641865
申请日：1996-05-02
申请人： Pierce V. Keating
发明人： Pierce V. Keating
IPC分类号： H03K19/082 , H03K19/086 , H03M5/02
CPC分类号： H03M5/02 , H03K19/0823 , H03K19/086
摘要： A fully differential, low voltage ECL gate (300) receives differential input signals (A, Ax, B, Bx) and provides them to first and second differential amplifiers (306, 328). The first differential amplifier (306) amplifies and level shifts the differential input (A, Ax) to provide a differential output (OUTx). The second differential amplifier amplifies the second differential input (B, Bx) to provide an amplified output, OUT. The amplified output signal, OUT, provides a different voltage level than that provided by amplified level shifted output signal, OUTx. The amplified level shifted output (OUTx) of the first differential amplifier (306) is then compared to the amplified output (OUT) of the second differential amplifier (328) to provide either an AND gate or an OR gate function.
摘要翻译：全差分低电压ECL门（300）接收差分输入信号（A，Ax，B，Bx）并将其提供给第一和第二差分放大器（306,328）。第一差分放大器（306）对差分输入（A，Ax）进行放大和电平移位以提供差分输出（OUTx）。第二差分放大器放大第二差分输入（B，Bx）以提供放大的输出OUT。放大的输出信号OUT提供与放大的电平移位输出信号OUTx提供的不同的电压电平。然后将第一差分放大器（306）的放大电平移位输出（OUTx）与第二差分放大器（328）的放大输出（OUT）进行比较，以提供与门或或门功能。

4. 发明授权

US07099354B2 Method and apparatus for frequency and timing distribution through a packet-based network 有权
公开(公告)号：US07099354B2
公开(公告)日：2006-08-29
申请号：US10132086
申请日：2002-04-24
申请人： Pierce V. Keating
发明人： Pierce V. Keating
IPC分类号： H04J3/06 , G06F15/15 , H04L7/00
CPC分类号： H04J3/0667
摘要： A reference frequency is distributed through a packet-based network to remote elements in a system. Timing packets are periodically sent from a master timing element, to be received by at least one peripheral timing element. Echo messages are sent to the master timing element by each peripheral timing element after a unique delay, in response to the reception of a timing packet. Loopback delay measurements are included in each timing packet for each peripheral timing element. Each peripheral timing element locks a loop using only timing packets which incur a minimum loopback delay.

5. 发明授权

US5886577A Apparatus for efficient current amplification 失效
标题翻译：用于高效电流放大的装置
公开(公告)号：US5886577A
公开(公告)日：1999-03-23
申请号：US900146
申请日：1997-07-28
申请人： Pierce V. Keating
发明人： Pierce V. Keating
IPC分类号： H03F3/45 , H03F3/50 , H03F3/68
CPC分类号： H03F3/4508 , H03F3/45085 , H03F3/50 , H03F2203/45584 , H03F2203/45631 , H03F2203/45641
摘要： Two emitter follower transistors (260, 250), in which each transistor has an emitter coupled to one of the collectors of a differential pair structure (230, 240)to form two stacked transistor pairs (260, 230) and (250, 240). A first differential signal (IN, INX) is positive supply referenced (Vcc) and is coupled to the bases of the emitter follower transistors (250, 260). A second differential input signal (275, 295) is coupled to the bases of the differential pair transistors (230, 240). The second differential input signal (275, 295) is identical to the first input signal but also includes a voltage level shift from the positive supply (Vcc). The first and second input signal portions are coupled to the transistors which make up the stacked transistor pair (260, 230) and (250, 240) and are chosen so that they are 180 degrees out of phase.
摘要翻译：两个射极跟随器晶体管（260,250），其中每个晶体管具有耦合到差分对结构（230,240）的集电极之一的发射极，以形成两个堆叠的晶体管对（260,230）和（250,240）。第一差分信号（IN，INX）为正电源（Vcc），并耦合到发射极跟随器晶体管（250,260）的基极。第二差分输入信号（275,295）耦合到差分对晶体管（230,240）的基极。第二差分输入信号（275,295）与第一输入信号相同，但也包括从正电源（Vcc）的电压电平移位。第一和第二输入信号部分耦合到构成堆叠晶体管对（260,230）和（250,240）的晶体管，并被选择为使它们相位相差180度。

6. 发明授权

US5831454A Emitter coupled logic (ECL) gate 失效
标题翻译：发射极耦合逻辑（ECL）门
公开(公告)号：US5831454A
公开(公告)日：1998-11-03
申请号：US673858
申请日：1996-07-01
申请人： Pierce V. Keating
发明人： Pierce V. Keating
IPC分类号： H03K19/013 , H03K19/086
CPC分类号： H03K19/013 , H03K19/086
摘要： An emitter coupled logic gate (300) avoids the use of stacked transistors by utilizing a single-ended bias input and positive feedback (320) between first and second transistors (304, 306) to achieve an inverter function. The inverter (300) can also be configured as an OR gate (500) by adding a third transistor biased by second single-ended logic input. The OR gate (500) can be configured into an exclusive OR gate (901) by converting another set of single-ended bias inputs into what can be either differential or non-differential outputs (921, 923) to be used as inputs to OR gate (919).
摘要翻译：发射极耦合逻辑门（300）通过利用第一和第二晶体管（304,306）之间的单端偏置输入和正反馈（320）来避免使用堆叠的晶体管，以实现逆变器功能。逆变器（300）也可以通过加上由第二单端逻辑输入端偏置的第三晶体管来配置为或门（500）。通过将另一组单端偏置输入转换为差分或非差分输出（921,923）作为OR的输入，可以将或门（500）配置为异或门（901）门（919）。

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