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1. 发明授权

US06707339B1 Controlled bias current buffer and method thereof 有权
标题翻译：控制偏置电流缓冲器及其方法
公开(公告)号：US06707339B1
公开(公告)日：2004-03-16
申请号：US10301992
申请日：2002-11-22
申请人： Kiyoshi Kase , Joseph Y. Chan , Chunhe Zhao
发明人： Kiyoshi Kase , Joseph Y. Chan , Chunhe Zhao
IPC分类号： H03F345
CPC分类号： H03F3/3023 , H03F3/45183 , H03F2203/45454 , H03F2203/45584 , H03F2203/45658
摘要： An operational amplifier circuit (10) uses a first operational amplifier (16) to selectively provide a boosted drive current in response to an input signal voltage transitioning. The boosted driver current is used by a second operational amplifier (22) having a single high gain stage (76). The output drive current of the operational amplifier circuit (10) is increased to a predetermined maximum value for a predetermined time after an input signal transition in order to source increased current to a capacitive or inductive load only during output signal transitions. Separate current boost circuits (30, 70) in each of the first and second operational amplifiers enable early signal transition detection and ensure continuation of increased current until completion of the signal transition.
摘要翻译：运算放大器电路（10）使用第一运算放大器（16）来响应于输入信号电压转换来选择性地提供升压的驱动电流。升压的驱动器电流由具有单个高增益级（76）的第二运算放大器（22）使用。运算放大器电路（10）的输出驱动电流在输入信号转换之后的预定时间内增加到预定的最大值，以便仅在输出信号转换期间将电流增加到电容或电感性负载。第一和第二运算放大器中的每一个中的独立电流升压电路（30,70）可以实现早期的信号转换检测，并确保持续增加的电流，直到完成信号转换。

2. 发明授权

US6137429A Circuit and method for attenuating noise in a data converter 有权
标题翻译：用于衰减数据转换器噪声的电路和方法
公开(公告)号：US6137429A
公开(公告)日：2000-10-24
申请号：US265238
申请日：1999-03-08
申请人： Joseph Y. Chan , David Yatim , Kiyoshi Kase , Paul Astrachan
发明人： Joseph Y. Chan , David Yatim , Kiyoshi Kase , Paul Astrachan
IPC分类号： H03M1/08 , H03M3/02 , H03M3/00
CPC分类号： H03M3/324 , H03M3/37 , H03M3/50
摘要： A data converter (10) and a method for attenuating noise in an output signal generated by the data converter (10). The data converter (10) includes a sigma-delta modulator (16), a digital-to-analog converter (17), a clock generator (19) connected to the digital-to-analog converter (17), and a clock control circuit (18) connected to the clock generator (19). The clock control circuit (18) enables or disables the clock generator (19) in accordance with the single-bit digital signal to cause a notch characteristic in the output signal for attenuating noise in the output signal.
摘要翻译：数据转换器（10）和用于衰减由数据转换器（10）产生的输出信号中的噪声的方法。数据转换器（10）包括Σ-Δ调制器（16），数模转换器（17），连接到数模转换器（17）的时钟发生器（19）和时钟控制电路（18）连接到时钟发生器（19）。时钟控制电路（18）根据单比特数字信号启用或禁用时钟发生器（19），以使得输出信号中的陷波特性衰减输出信号中的噪声。

3. 发明授权

US07667492B2 Input buffer 有权
标题翻译：输入缓冲区
公开(公告)号：US07667492B2
公开(公告)日：2010-02-23
申请号：US12004617
申请日：2007-12-21
申请人： Kiyoshi Kase , May Len , Dzung T. Tran
发明人： Kiyoshi Kase , May Len , Dzung T. Tran
IPC分类号： H03K19/094
CPC分类号： H03K19/018521
摘要： Methods and corresponding systems for buffering an input signal include outputting a first logic value in response to the input signal being below a lower threshold. A second logic value is output in response to the input signal rising above the lower threshold. Thereafter, the second logic value is maintained until the input exceeds a higher threshold and thereafter falls below the higher threshold. In response to the input signal falling below the higher threshold, the first logic value is output, and maintained at the first logic value, until the input falls below the lower threshold and thereafter rises above the lower threshold.
摘要翻译：用于缓冲输入信号的方法和相应系统包括响应于输入信号低于较低阈值输出第一逻辑值。响应于输入信号上升到较低阈值以上而输出第二逻辑值。此后，维持第二逻辑值，直到输入超过较高阈值，然后低于较高阈值。响应于输入信号低于较高阈值，第一逻辑值被输出并保持在第一逻辑值，直到输入低于低阈值，然后上升到低于下阈值。

4. 发明授权

US07573332B1 Amplifier with active inductor 有权
标题翻译：有源电感放大器
公开(公告)号：US07573332B1
公开(公告)日：2009-08-11
申请号：US12039377
申请日：2008-02-28
申请人： Kiyoshi Kase
发明人： Kiyoshi Kase
IPC分类号： H03F3/45 , H03H11/00
CPC分类号： H03F3/45183 , H03F2203/45652
摘要： An amplifier comprises an amplifier stage and an active inductor. The amplifier stage has an input terminal and an output terminal. The active inductor comprises first and second resistors and first and second transistors. The first resistor has a first terminal coupled to the output terminal of the amplifier stage, and a second terminal. The second resistor has a first terminal coupled to the output terminal of the amplifier stage, and a second terminal. The first transistor has a first current electrode coupled to the second terminal of the first resistor, a control electrode coupled to receive a bias voltage, and a second current electrode. The second transistor has a first current electrode coupled to the second current electrode of the first transistor, a control electrode coupled to the second terminal of the second resistor, and a second current electrode coupled to a first power supply voltage terminal.
摘要翻译：放大器包括放大器级和有源电感器。放大器级具有输入端和输出端。有源电感器包括第一和第二电阻器以及第一和第二晶体管。第一电阻器具有耦合到放大器级的输出端的第一端子和第二端子。第二电阻器具有耦合到放大器级的输出端的第一端子和第二端子。第一晶体管具有耦合到第一电阻器的第二端子的第一电流电极，耦合以接收偏置电压的控制电极和第二电流电极。第二晶体管具有耦合到第一晶体管的第二电流电极的第一电流电极，耦合到第二电阻器的第二端子的控制电极和耦合到第一电源电压端子的第二电流电极。

5. 发明申请

US20070183549A1 Adaptive variable length pulse synchronizer 有权
标题翻译：自适应可变长度脉冲同步器
公开(公告)号：US20070183549A1
公开(公告)日：2007-08-09
申请号：US11349874
申请日：2006-02-08
申请人： John Angello , Satyavathi Akella , Kiyoshi Kase , May Len
发明人： John Angello , Satyavathi Akella , Kiyoshi Kase , May Len
IPC分类号： H04L25/38
CPC分类号： H04L25/38 , H04L7/0008
摘要： An adaptive variable length pulse synchronizer including a state keeper circuit, an asynchronous pulse edge detection circuit, a data synchronization circuit, and a pulse edge synchronization circuit. The state keeper circuit detects a leading edge of the asynchronous pulse. The asynchronous pulse edge detection circuit detects a trailing edge of the asynchronous pulse after the state keeper circuit has detected the leading edge. The asynchronous pulse edge detection circuit further provides a pulse synchronized with a clock signal after the asynchronous pulse has been detected. The data synchronization circuit latches the asynchronous data and provides the synchronous data in response to the synchronous pulse. The pulse edge synchronization provides the synchronous ready signal after synchronous data has been provided. In one embodiment, the synchronous pulse occurs between successive rising edges of the clock whereas the synchronous ready signal is provided in response to the intermediate falling edge of the clock.
摘要翻译：一种自适应可变长度脉冲同步器，包括状态保持器电路，异步脉冲沿检测电路，数据同步电路和脉冲沿同步电路。状态保持电路检测异步脉冲的前沿。在状态保持电路检测到前沿之后，异步脉冲沿检测电路检测异步脉冲的后沿。在检测到异步脉冲之后，异步脉冲沿检测电路还提供与时钟信号同步的脉冲。数据同步电路锁存异步数据，并响应于同步脉冲提供同步数据。在提供同步数据之后，脉冲沿同步提供同步就绪信号。在一个实施例中，同步脉冲发生在时钟的连续上升沿之间，而响应于时钟的中间下降沿提供同步就绪信号。

6. 发明申请

US20060082403A1 Circuit and method for interpolative delay 有权
公开(公告)号：US20060082403A1
公开(公告)日：2006-04-20
申请号：US10967898
申请日：2004-10-18
申请人： Kiyoshi Kase
发明人： Kiyoshi Kase
IPC分类号： H03L7/06
CPC分类号： H03L7/0814 , H03K5/133 , H03K5/1504 , H03K2005/00039
摘要： A circuit and a method for interpolative delay is provided. The circuit includes a delay locked loop with interpolation delay. The delay locked loop includes a differential inverter, an interpolation circuit, and a differential compare circuit. The differential inverter is coupled to receive a differential clock signal and coupled to provide an inverted differential clock signal. The interpolation circuit is coupled to receive both the clock signal and the inverted clock signal, and to provide an interpolated clock signal having a first delay relative to the clock signal. The differential compare circuit is coupled to receive the inverted clock signal and coupled to provide a non-interpolated clock signal having a second delay relative to the clock signal. The second delay corresponds to a full delay of the differential inverter and the first delay corresponds to a predetermined fraction of the full delay.

7. 发明申请

US20060071702A1 Well bias voltage generator 有权
标题翻译：良好的偏置电压发生器
公开(公告)号：US20060071702A1
公开(公告)日：2006-04-06
申请号：US10958831
申请日：2004-10-05
申请人： Kiyoshi Kase
发明人： Kiyoshi Kase
IPC分类号： G11C5/14
CPC分类号： H02M3/07 , G11C5/145
摘要： A well bias module outputs a voltage used to bias the wells of transistors or other semiconductor components. The well bias module includes a feedback loop having a voltage generation module and a subthreshold leakage sense module that is operable to model the transistors or other semiconductor components so as to sense the subthreshold leakage resulting from a particular well bias voltage output by the voltage generation module. The subthreshold leakage sense module provides a representation of the sensed subthreshold leakage to the voltage generation module, which adjusts the magnitude of the well bias voltage based on this representation so as to reduce or minimize the subthreshold leakage in the transistors or other semiconductor components.
摘要翻译：阱偏置模块输出用于偏置晶体管或其他半导体元件的阱的电压。阱偏置模块包括具有电压产生模块和亚阈值泄漏检测模块的反馈环路，该模块可操作以对晶体管或其它半导体元件建模，以便感测由电压产生模块输出的特定阱偏置电压产生的亚阈值泄漏。亚阈值泄漏检测模块提供对电压产生模块的感测到的亚阈值泄漏的表示，该电压产生模块基于该表示来调整阱偏置电压的幅度，以便减小或最小化晶体管或其它半导体部件中的亚阈值泄漏。

8. 发明申请

US20060012356A1 Voltage regulator with adaptive frequency compensation 有权
标题翻译：具有自适应频率补偿的稳压器
公开(公告)号：US20060012356A1
公开(公告)日：2006-01-19
申请号：US10891811
申请日：2004-07-15
申请人： Kiyoshi Kase , May Len
发明人： Kiyoshi Kase , May Len
IPC分类号： G05F1/40
CPC分类号： G05F1/575
摘要： A voltage regulator includes a first and second amplifier stage, an output stage, and a variable zero circuit. The first amplifier stage is coupled to receive a reference voltage and introduces a first pole of the voltage regulator. The second amplifier stage is coupled to the first amplifier stage and introduces a second pole of the voltage regulator. The output stage is coupled to the second amplifier stage, has an output driver, and is coupled to provide an output voltage based on the reference voltage. The variable zero circuit is coupled to the first amplifier stage, the second amplifier stage, and the output stage. The variable zero circuit provides a zero to compensate for at least one of the first pole or the second pole of the voltage regulator based on a gate to source voltage of the output driver and a drain to source voltage of the output driver.
摘要翻译：电压调节器包括第一和第二放大器级，输出级和可变零电路。第一放大器级耦合以接收参考电压并引入电压调节器的第一极。第二放大器级耦合到第一放大器级并引入电压调节器的第二极。输出级耦合到第二放大器级，具有输出驱动器，并且被耦合以提供基于参考电压的输出电压。可变零电路耦合到第一放大器级，第二放大级和输出级。基于输出驱动器的栅极 - 源极电压和输出驱动器的漏极 - 源极电压，可变零电路提供零以补偿电压调节器的第一极点或第二极点中的至少一个极点。

9. 发明授权

US08923465B2 Method for sampling data and apparatus therefor 有权
标题翻译：数据采集方法及其设备
公开(公告)号：US08923465B2
公开(公告)日：2014-12-30
申请号：US12988831
申请日：2008-05-19
申请人： Conor O'Keeffe , Kiyoshi Kase , Paul Kelleher
发明人： Conor O'Keeffe , Kiyoshi Kase , Paul Kelleher
IPC分类号： H04L7/00 , H04L7/033
CPC分类号： H04L7/0337
摘要： A semiconductor device comprises sampling logic, comprising: input sample path selection logic arranged to enable at least one input sample path; sampler logic arranged to receive and sample an input data signal in a serial data stream in accordance with a phase of the at least one enabled input sample path; and transition detection logic arranged to detect transitions within the received input data signal. The input sample path selection logic is further arranged, upon detection of a transition within the received input data signal, to determine if the phase of the at least one input sample path is a phase having a largest window between logic values; and if it is determined that the phase of the at least one input sample path is not the phase having a largest window between logic values, to enable at least one input sample path comprising a more appropriate phase.
摘要翻译：半导体器件包括采样逻辑，包括：输入采样路径选择逻辑，布置成使能至少一个输入采样路径; 采样器逻辑，被布置为根据所述至少一个使能的输入采样路径的相位接收和采样串行数据流中的输入数据信号; 以及转移检测逻辑，被布置成检测所接收的输入数据信号内的转变。在检测到所接收的输入数据信号中的转换之后，进一步布置输入采样路径选择逻辑，以确定至少一个输入采样路径的相位是否是在逻辑值之间具有最大窗口的相位; 并且如果确定所述至少一个输入采样路径的相位不是在逻辑值之间具有最大窗口的相位，以使得能够进行包括更适当相位的至少一个输入采样路径。

10. 发明申请

US20110043253A1 METHOD FOR SAMPLING DATA AND APPARATUS THEREFOR 有权
标题翻译：采样数据及其设备的方法
公开(公告)号：US20110043253A1
公开(公告)日：2011-02-24
申请号：US12988831
申请日：2008-05-19
申请人： Conor O'Keeffe , Kiyoshi Kase , Paul Kelleher
发明人： Conor O'Keeffe , Kiyoshi Kase , Paul Kelleher
IPC分类号： H03D13/00
CPC分类号： H04L7/0337
摘要： A semiconductor device comprises sampling logic, comprising: input sample path selection logic arranged to enable at least one input sample path; sampler logic arranged to receive and sample an input data signal in a serial data stream in accordance with a phase of the at least one enabled input sample path; and transition detection logic arranged to detect transitions within the received input data signal. The input sample path selection logic is further arranged, upon detection of a transition within the received input data signal, to determine if the phase of the at least one input sample path is a phase having a largest window between logic values; and if it is determined that the phase of the at least one input sample path is not the phase having a largest window between logic values, to enable at least one input sample path comprising a more appropriate phase.
摘要翻译：半导体器件包括采样逻辑，包括：输入采样路径选择逻辑，布置成使能至少一个输入采样路径; 采样器逻辑，被布置为根据所述至少一个使能的输入采样路径的相位接收和采样串行数据流中的输入数据信号; 以及转移检测逻辑，被布置成检测所接收的输入数据信号内的转变。在检测到所接收的输入数据信号中的转换之后，进一步布置输入采样路径选择逻辑，以确定至少一个输入采样路径的相位是否是在逻辑值之间具有最大窗口的相位; 并且如果确定所述至少一个输入采样路径的相位不是在逻辑值之间具有最大窗口的相位，以使得能够进行包括更适当相位的至少一个输入采样路径。

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