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1. 发明申请

US20180076776A1 SEMICONDUCTOR CIRCUIT 审中-公开
公开(公告)号：US20180076776A1
公开(公告)日：2018-03-15
申请号：US15442687
申请日：2017-02-26
申请人： Toshiba Memory Corporation
发明人： Hiroo YABE
IPC分类号： H03F1/30 , H03F3/45
CPC分类号： H03F1/30 , G05F1/00 , H03F1/301 , H03F3/45475 , H03F2200/447 , H03F2203/45021 , H03F2203/45026 , H03F2203/45286
摘要： A semiconductor circuit includes a differential amplifier having a first positive terminal, a second positive terminal, a first negative terminal, a second negative terminal, and an output terminal. The output voltage is at a level that corresponds to a voltage level obtained by subtracting a voltage of the first negative terminal and the second negative terminal from a voltage sum of the first positive terminal and the second positive terminal. A first diode has a first anode connected to one of the first positive or the first negative terminal. A second diode has a second anode connected to the other of the first negative and first positive terminal. A predetermined reference voltage is applied to the second positive terminal. And a voltage corresponding to the output voltage of the differential amplifier is fed back to the second negative terminal.

2. 发明授权

US09455673B2 Auto-zero circuit of operational amplifier 有权
标题翻译：运算放大器的自动归零电路
公开(公告)号：US09455673B2
公开(公告)日：2016-09-27
申请号：US14416047
申请日：2014-11-18
申请人： Shenzhen China Star Optoelectronics Technology Co., Ltd.
发明人： Jian He , Shen-Sian Syu , Yugang Bao
IPC分类号： H03F3/45 , H03F1/30
CPC分类号： H03F1/30 , H03F3/45076 , H03F3/45475 , H03F3/45977 , H03F2200/261 , H03F2203/45286 , H03F2203/45522
摘要： An auto-zero circuit of an operational amplifier is disclosed, and the auto-zero circuit has: a micro-control unit and a digital potentiometer; the micro-control unit is used to obtain a voltage value of an offset voltage of the output end when there is no input in the operational amplifier, and generates a control signal which causes the voltage value of the offset voltage to be smaller than a first threshold value according to the voltage value of the offset voltage; the digital potentiometer is used to adjust a resistance thereof according to the control signal.
摘要翻译：公开了一种运算放大器的自动调零电路，并且自动归零电路具有：微控制单元和数字电位器; 当在运算放大器中没有输入时，微控制单元用于获得输出端的偏移电压的电压值，并且产生使偏移电压的电压值小于第一值的控制信号根据偏移电压的电压值设定阈值; 数字电位器用于根据控制信号调整其电阻。

3. 发明授权

US09247331B2 Temperature compensated microphone 有权
标题翻译：温度补偿麦克风
公开(公告)号：US09247331B2
公开(公告)日：2016-01-26
申请号：US13381621
申请日：2009-06-29
申请人： Mikko Veli Aimo Suvanto
发明人： Mikko Veli Aimo Suvanto
IPC分类号： H03G3/00 , H04R1/04 , H04R19/00 , H03F1/30 , H04R19/01
CPC分类号： H04R1/04 , H03F1/30 , H03F2200/468 , H03F2203/45284 , H03F2203/45286 , H03G3/00 , H04R19/005 , H04R19/016 , H04R2201/003
摘要： A method and a device for eliminating or minimizing the sensitivity changes in a microphone due to temperature changes. The temperature-induced changes in the sensitivity can be caused by the changes in the sound-to-electrical signal transducer, in the microphone membrane, in the ASIC or other reasons. One or more temperature dependent components in the microphone or in a microphone module are used to offset the temperature-induced changes in the sensitivity. Sensitivity of a microphone is defined as the output voltage for a specific acoustic stimulus and load condition.
摘要翻译：一种用于消除或最小化由于温度变化导致的麦克风的灵敏度变化的方法和装置。灵敏度的温度引起的变化可以由声电信号传感器，麦克风膜，ASIC中的变化或其他原因引起。使用麦克风或麦克风模块中的一个或多个与温度相关的组件来抵消温度引起的灵敏度变化。麦克风的灵敏度定义为特定声学刺激和负载条件的输出电压。

4. 发明授权

US07236212B2 System and method for providing a low power receiver design 有权
标题翻译：提供低功率接收机设计的系统和方法
公开(公告)号：US07236212B2
公开(公告)日：2007-06-26
申请号：US09766048
申请日：2001-01-19
申请人： Frank Carr , Pieter Vorenkamp
发明人： Frank Carr , Pieter Vorenkamp
IPC分类号： H04N5/455 , H04N7/10 , H04N7/16
CPC分类号： H03D3/18 , H01F17/0006 , H01F17/0013 , H01F27/34 , H01F27/40 , H01F27/42 , H01F2017/0053 , H01F2021/125 , H01L23/5227 , H01L27/0248 , H01L27/0251 , H01L27/08 , H01L2924/0002 , H01L2924/3011 , H03B5/04 , H03B5/364 , H03D7/161 , H03D7/18 , H03F1/26 , H03F1/3211 , H03F3/195 , H03F3/45183 , H03F3/45188 , H03F3/68 , H03F3/72 , H03F2200/111 , H03F2200/294 , H03F2200/372 , H03F2200/447 , H03F2200/63 , H03F2203/45264 , H03F2203/45286 , H03G1/0023 , H03G1/0029 , H03G3/3052 , H03H7/25 , H03H11/04 , H03H11/1291 , H03H11/53 , H03H11/54 , H03H19/004 , H03J1/0075 , H03J3/04 , H03J3/08 , H03J3/185 , H03J2200/10 , H03L7/10 , H03L7/183 , H03L7/23 , H03L2207/06 , H01L2924/00
摘要： An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programable attenuation and a programable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator. The VCOs in the PLLs are centered using a control circuit to center the tuning capacitance range. A differential crystal oscillator is advantageously used as a frequency reference. Differential signal transmission is advantageously used throughout the receiver.
摘要翻译：描述了基本上在单个CMOS集成电路上实现的具有信道选择和图像抑制的集成接收机。接收机前端提供可编程衰减和可编程增益低噪声放大器。频率转换电路有利地使用集成到衬底上的LC滤波器与图像抑制混合器结合，以提供足够的图像频率抑制。过滤器调谐和电感Q补偿温度在芯片上执行。滤波器采用多轨螺旋电感。使用本地振荡器调整滤波器以调整替代滤波器，以及滤波器组件值期间的频率缩放与被调谐的滤波器的频率缩放。结合滤波，频率规划提供了额外的镜像抑制。片上本地振荡器信号产生方法的有利选择是通过PLL带外本地振荡和通过频带本地振荡器的直接合成。 PLL中的VCO使用控制电路居中，使调谐电容范围居中。差分晶体振荡器有利地用作频率参考。差分信号传输有利地用于整个接收机。

5. 发明申请

US20070120605A1 Integrated switchless programmable attenuator and low noise amplifier 有权
公开(公告)号：US20070120605A1
公开(公告)日：2007-05-31
申请号：US11698162
申请日：2007-01-26
申请人： Klaas Bult , Ramon Gomez
发明人： Klaas Bult , Ramon Gomez
IPC分类号： H03G3/00
CPC分类号： H03D3/18 , H01F17/0006 , H01F17/0013 , H01F27/34 , H01F27/40 , H01F27/42 , H01F2017/0053 , H01F2021/125 , H01L23/5227 , H01L27/0248 , H01L27/0251 , H01L27/08 , H01L2924/0002 , H01L2924/3011 , H03B5/04 , H03B5/364 , H03D7/161 , H03D7/18 , H03F1/26 , H03F1/3211 , H03F3/195 , H03F3/45183 , H03F3/45188 , H03F3/68 , H03F3/72 , H03F2200/111 , H03F2200/294 , H03F2200/372 , H03F2200/447 , H03F2200/63 , H03F2203/45264 , H03F2203/45286 , H03G1/0023 , H03G1/0029 , H03G3/3052 , H03H7/25 , H03H11/04 , H03H11/1291 , H03H11/53 , H03H11/54 , H03H19/004 , H03J1/0075 , H03J3/04 , H03J3/08 , H03J3/185 , H03J2200/10 , H03L7/10 , H03L7/183 , H03L7/23 , H03L2207/06 , H01L2924/00
摘要： An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programable attenuation and a programable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator. The VCOs in the PLLs are centered using a control circuit to center the tuning capacitance range. A differential crystal oscillator is advantageously used as a frequency reference. Differential signal transmission is advantageously used throughout the receiver.

6. 发明授权

US07092043B2 Fully integrated tuner architecture 有权
标题翻译：完全集成的调谐器架构
公开(公告)号：US07092043B2
公开(公告)日：2006-08-15
申请号：US09439101
申请日：1999-11-12
申请人： Pieter Vorenkamp , Klaas Bult , Frank Carr , Christopher M. Ward , Ralph Duncan , Tom W. Kwan , James Y. C. Chang , Haideh Khorramabadi
发明人： Pieter Vorenkamp , Klaas Bult , Frank Carr , Christopher M. Ward , Ralph Duncan , Tom W. Kwan , James Y. C. Chang , Haideh Khorramabadi
IPC分类号： H04N5/455
CPC分类号： H03D3/18 , H01F17/0006 , H01F17/0013 , H01F27/34 , H01F27/40 , H01F27/42 , H01F2017/0053 , H01F2021/125 , H01L23/5227 , H01L27/0248 , H01L27/0251 , H01L27/08 , H01L2924/0002 , H01L2924/3011 , H03B5/04 , H03B5/364 , H03D7/161 , H03D7/18 , H03F1/26 , H03F1/3211 , H03F3/195 , H03F3/45183 , H03F3/45188 , H03F3/68 , H03F3/72 , H03F2200/111 , H03F2200/294 , H03F2200/372 , H03F2200/447 , H03F2200/63 , H03F2203/45264 , H03F2203/45286 , H03G1/0023 , H03G1/0029 , H03G3/3052 , H03H7/25 , H03H11/04 , H03H11/1291 , H03H11/53 , H03H11/54 , H03H19/004 , H03J1/0075 , H03J3/04 , H03J3/08 , H03J3/185 , H03J2200/10 , H03L7/10 , H03L7/183 , H03L7/23 , H03L2207/06 , H01L2924/00
摘要： An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programable attenuation and a programable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator. The VCOs in the PLLs are centered using a control circuit to center the tuning capacitance range. A differential crystal oscillator is advantageously used as a frequency reference. Differential signal transmission is advantageously used throughout the receiver.
摘要翻译：描述了基本上在单个CMOS集成电路上实现的具有信道选择和图像抑制的集成接收机。接收机前端提供可编程衰减和可编程增益低噪声放大器。频率转换电路有利地使用集成到衬底上的LC滤波器与图像抑制混合器结合，以提供足够的图像频率抑制。过滤器调谐和电感Q补偿温度在芯片上执行。滤波器采用多轨螺旋电感。使用本地振荡器调整滤波器以调整替代滤波器，以及滤波器组件值期间的频率缩放与被调谐的滤波器的频率缩放。结合滤波，频率规划提供了额外的镜像抑制。片上本地振荡器信号产生方法的有利选择是通过PLL带外本地振荡和通过频带本地振荡器的直接合成。 PLL中的VCO使用控制电路居中，使调谐电容范围居中。差分晶体振荡器有利地用作频率参考。差分信号传输有利地用于整个接收机。

7. 发明申请

US20030162521A1 System and method for on-chip filter tuning 有权
公开(公告)号：US20030162521A1
公开(公告)日：2003-08-28
申请号：US10388398
申请日：2003-03-17
申请人： Broadcom Corporation
发明人： Pieter Vorenkamp , Klaas Bult , Frank Carr
IPC分类号： H04B001/10
CPC分类号： H03D3/18 , H01F17/0006 , H01F17/0013 , H01F27/34 , H01F27/40 , H01F27/42 , H01F2017/0053 , H01F2021/125 , H01L23/5227 , H01L27/0248 , H01L27/0251 , H01L27/08 , H01L2924/0002 , H01L2924/3011 , H03B5/04 , H03B5/364 , H03D7/161 , H03D7/18 , H03F1/26 , H03F1/3211 , H03F3/195 , H03F3/45183 , H03F3/45188 , H03F3/68 , H03F3/72 , H03F2200/111 , H03F2200/294 , H03F2200/372 , H03F2200/447 , H03F2200/63 , H03F2203/45264 , H03F2203/45286 , H03G1/0023 , H03G1/0029 , H03G3/3052 , H03H7/25 , H03H11/04 , H03H11/1291 , H03H11/53 , H03H11/54 , H03H19/004 , H03J1/0075 , H03J3/04 , H03J3/08 , H03J3/185 , H03J2200/10 , H03L7/10 , H03L7/183 , H03L7/23 , H03L2207/06 , H01L2924/00
摘要： An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programable attenuation and a programable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator. The VCOs in the PLLs are centered using a control circuit to center the tuning capacitance range. A differential crystal oscillator is advantageously used as a frequency reference. Differential signal transmission is advantageously used throughout the receiver.

8. 发明申请

US20190207564A1 NEGATIVE CAPACITANCE CIRCUITS INCLUDING TEMPERATURE-COMPENSATION BIASINGS 审中-公开
公开(公告)号：US20190207564A1
公开(公告)日：2019-07-04
申请号：US15859431
申请日：2017-12-30
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Ani Xavier , Neeraj SHRIVASTAVA , Arun MOHAN , Shagun DUSAD
IPC分类号： H03F1/30 , H03F1/02 , H03F3/45
CPC分类号： H03F1/301 , H03F1/0205 , H03F3/45179 , H03F2203/45286
摘要： In some examples, an amplifier stage includes a voltage-gain amplifier stage and a negative capacitance circuit coupled to the voltage-gain amplifier stage, the negative capacitance circuit comprising a first transistor that provides a first temperature-biased current.

9. 发明授权

US08212616B2 Biasing circuit for differential amplifier 有权
标题翻译：差分放大器的偏置电路
公开(公告)号：US08212616B2
公开(公告)日：2012-07-03
申请号：US12979135
申请日：2010-12-27
申请人： Eoin Ohannaidh
发明人： Eoin Ohannaidh
IPC分类号： H03F3/45
CPC分类号： H03F3/45183 , G05F3/245 , H03F1/26 , H03F1/3211 , H03F3/45197 , H03F3/45632 , H03F2200/447 , H03F2200/453 , H03F2200/456 , H03F2203/45244 , H03F2203/45286 , H03F2203/45468 , H03F2203/45484 , H03F2203/45508 , H03F2203/45702
摘要： The invention concerns a biasing circuit for controlling the current flowing through a differential pair (102, 104) comprising: a first branch comprising a first resistor (306), a first transistor device (308) and a second transistor device (310) coupled in series; a second branch comprising a second resistor (312), a third transistor device (314) and a fourth transistor device (316) coupled in series, a control node of the third transistor device being coupled to a first node (324) between the first resistor and the first transistor device, and a control node of the first transistor device being coupled to a second node (322) between the second resistor and the third transistor device; and an operational amplifier (318) having an output node coupled to control nodes of the second and fourth transistor devices, said output node providing a output signal (Vc) for controlling the current flowing through said differential pair.
摘要翻译：本发明涉及一种用于控制流过差分对（102,104）的电流的偏置电路，包括：第一分支，包括第一电阻器（306），第一晶体管器件（308）和第二晶体管器件（310）系列; 第二分支，包括串联耦合的第二电阻器（312），第三晶体管器件（314）和第四晶体管器件（316），所述第三晶体管器件的控制节点耦合到所述第一晶体管电阻器和第一晶体管器件，并且第一晶体管器件的控制节点耦合到第二电阻器和第三晶体管器件之间的第二节点（322）; 以及具有耦合到第二和第四晶体管器件的控制节点的输出节点的运算放大器（318），所述输出节点提供用于控制流过所述差分对的电流的输出信号（Vc）。

10. 发明申请

US20110067083A1 Fully Integrated Tuner Architecture 有权
标题翻译：完全集成的调谐器架构
公开(公告)号：US20110067083A1
公开(公告)日：2011-03-17
申请号：US12883575
申请日：2010-09-16
申请人： Pieter Vorenkamp , Klaas Bult , Frank Carr , Christopher M. Ward , Ralph Duncan , Tom W. Kwan , James Y.C. Chang , Haideh Khorramabadi
发明人： Pieter Vorenkamp , Klaas Bult , Frank Carr , Christopher M. Ward , Ralph Duncan , Tom W. Kwan , James Y.C. Chang , Haideh Khorramabadi
IPC分类号： H04N5/50 , H04N7/173
CPC分类号： H03D3/18 , H01F17/0006 , H01F17/0013 , H01F27/34 , H01F27/40 , H01F27/42 , H01F2017/0053 , H01F2021/125 , H01L23/5227 , H01L27/0248 , H01L27/0251 , H01L27/08 , H01L2924/0002 , H01L2924/3011 , H03B5/04 , H03B5/364 , H03D7/161 , H03D7/18 , H03F1/26 , H03F1/3211 , H03F3/195 , H03F3/45183 , H03F3/45188 , H03F3/68 , H03F3/72 , H03F2200/111 , H03F2200/294 , H03F2200/372 , H03F2200/447 , H03F2200/63 , H03F2203/45264 , H03F2203/45286 , H03G1/0023 , H03G1/0029 , H03G3/3052 , H03H7/25 , H03H11/04 , H03H11/1291 , H03H11/53 , H03H11/54 , H03H19/004 , H03J1/0075 , H03J3/04 , H03J3/08 , H03J3/185 , H03J2200/10 , H03L7/10 , H03L7/183 , H03L7/23 , H03L2207/06 , H01L2924/00
摘要： An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programmable attenuation and a programmable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator. The VCOs in the PLLs are centered using a control circuit to center the tuning capacitance range. A differential crystal oscillator is advantageously used as a frequency reference. Differential signal transmission is advantageously used throughout the receiver.
摘要翻译：描述了基本上在单个CMOS集成电路上实现的具有信道选择和图像抑制的集成接收机。接收机前端提供可编程衰减和可编程增益低噪声放大器。频率转换电路有利地使用集成到衬底上的LC滤波器与图像抑制混合器结合，以提供足够的图像频率抑制。过滤器调谐和电感Q补偿温度在芯片上执行。滤波器采用多轨螺旋电感。使用本地振荡器调整滤波器以调整替代滤波器，以及滤波器组件值期间的频率缩放与被调谐的滤波器的频率缩放。结合滤波，频率规划提供了额外的镜像抑制。片上本地振荡器信号产生方法的有利选择是通过PLL带外本地振荡和通过频带本地振荡器的直接合成。 PLL中的VCO使用控制电路居中，使调谐电容范围居中。差分晶体振荡器有利地用作频率参考。差分信号传输有利地用于整个接收机。

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