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1. 发明申请

US20180205350A1 Amplifier System for Use as High Sensitivity Selective Receiver Without Frequency Conversion 审中-公开
公开(公告)号：US20180205350A1
公开(公告)日：2018-07-19
申请号：US15916864
申请日：2018-03-09
申请人： DOCKON AG
发明人： Patrick Antoine Rada , Forrest James Brown , Alexandre Dupuy
IPC分类号： H03F3/193 , H03F3/195 , H04B1/22 , H03F3/72 , H03F1/56 , H03F1/38 , H03L7/06
CPC分类号： H03F3/193 , H03F1/38 , H03F1/56 , H03F3/195 , H03F3/72 , H03F2200/129 , H03F2200/147 , H03F2200/222 , H03F2200/237 , H03F2200/241 , H03F2200/243 , H03F2200/246 , H03F2200/261 , H03F2200/294 , H03F2200/297 , H03F2200/301 , H03F2200/306 , H03F2200/309 , H03F2200/387 , H03F2200/391 , H03F2200/399 , H03F2200/402 , H03F2200/438 , H03F2200/451 , H03F2200/462 , H03L7/06 , H04B1/22
摘要： An amplifying system is provided for use as a high sensitivity receive booster or replacement for a low noise amplifier in a receive chain of a communication device. The amplifying system includes an amplifying circuit configured to receive an input signal having a first frequency and generate an oscillation based on the input signal, a sampling circuit coupled to the amplifying circuit and configured to terminate the oscillation based on a predetermined threshold to periodically clamp and restart the oscillation to generate a series of pulses modulated by the oscillation and by the input signal, and one or more resonant circuits coupled with the amplifying circuit and configured to establish a frequency of operation and to generate an output signal having a second frequency, the second frequency being substantially the same as the first frequency.

2. 发明申请

US20180026591A1 Logarithmic Detector Amplifier System for Use as High Sensitivity Selective Receiver Without Frequency Conversion 审中-公开
公开(公告)号：US20180026591A1
公开(公告)日：2018-01-25
申请号：US15723060
申请日：2017-10-02
申请人： DOCKON AG
发明人： Patrick Antoine Rada , Forrest James Brown , Alexandre Dupuy
IPC分类号： H03F3/193 , H03F1/38 , H03F3/195 , H03F3/72 , H04B1/22 , H03L7/06 , H03F1/56
CPC分类号： H03F3/193 , H03F1/38 , H03F1/56 , H03F3/195 , H03F3/72 , H03F2200/129 , H03F2200/147 , H03F2200/222 , H03F2200/237 , H03F2200/241 , H03F2200/243 , H03F2200/246 , H03F2200/261 , H03F2200/294 , H03F2200/297 , H03F2200/301 , H03F2200/306 , H03F2200/309 , H03F2200/387 , H03F2200/391 , H03F2200/399 , H03F2200/402 , H03F2200/438 , H03F2200/451 , H03F2200/462 , H03L7/06 , H04B1/22
摘要： A logarithmic detector amplifying (LDA) system is provided for use as a high sensitivity receive booster or replacement for a low noise amplifier in a receive chain of a communication device. The LDA system includes an amplifying circuit configured to receive an input signal having a first frequency and generate an oscillation based on the input signal, a sampling circuit coupled to the amplifying circuit and configured to terminate the oscillation based on a predetermined threshold to periodically clamp and restart the oscillation to generate a series of pulses modulated by the oscillation and by the input signal, and one or more resonant circuits coupled with the amplifying circuit and configured to establish a frequency of operation and to generate an output signal having a second frequency, the second frequency being substantially the same as the first frequency.

3. 发明申请

US20150070058A1 Logarithmic Detector Amplifier System for Use as High Sensitivity Selective Receiver Without Frequency Conversion 有权
公开(公告)号：US20150070058A1
公开(公告)日：2015-03-12
申请号：US14216945
申请日：2014-03-17
申请人： DockOn AG
发明人： Patrick Antoine Rada , Forrest James Brown , Alexandre Dupuy
IPC分类号： H03L7/093 , H04B1/10
CPC分类号： H03F3/193 , H03F1/38 , H03F1/56 , H03F3/195 , H03F3/72 , H03F2200/129 , H03F2200/147 , H03F2200/222 , H03F2200/237 , H03F2200/241 , H03F2200/243 , H03F2200/246 , H03F2200/261 , H03F2200/294 , H03F2200/297 , H03F2200/301 , H03F2200/306 , H03F2200/309 , H03F2200/387 , H03F2200/391 , H03F2200/399 , H03F2200/402 , H03F2200/438 , H03F2200/451 , H03F2200/462 , H03L7/06 , H04B1/22
摘要： A logarithmic detector amplifying (LDA) system is provided for use as a high sensitivity receive booster or replacement for a low noise amplifier in a receive chain of a communication device. The LDA system includes an amplifying circuit configured to receive an input signal having a first frequency and generate an oscillation based on the input signal, a sampling circuit coupled to the amplifying circuit and configured to terminate the oscillation based on a predetermined threshold to periodically clamp and restart the oscillation to generate a series of pulses modulated by the oscillation and by the input signal, and one or more resonant circuits coupled with the amplifying circuit and configured to establish a frequency of operation and to generate an output signal having a second frequency, the second frequency being substantially the same as the first frequency.

4. 发明申请

US20140240046A1 SYSTEMS AND METHODS FOR OPERATING A POWER AMPLIFIER 审中-公开
标题翻译：用于操作功率放大器的系统和方法
公开(公告)号：US20140240046A1
公开(公告)日：2014-08-28
申请号：US14269438
申请日：2014-05-05
申请人： Marvell World Trade Ltd.
发明人： Poh Boon Leong , Ping Song , Sehat Sutardja
IPC分类号： H03F3/26
CPC分类号： H03F3/265 , H03F1/223 , H03F3/193 , H03F3/245 , H03F2200/306 , H03F2200/408 , H03F2200/534 , H03F2200/537 , H03F2200/541
摘要： A power amplifier configured to receive an AC input signal and output, based on the AC input signal, an output voltage via a first output voltage terminal and a second output voltage terminal. The power amplifier includes a first transistor and a second transistor connected in a push-pull configuration, a first inductor, a second inductor, and a first capacitor. The first output voltage terminal is located between the first inductor and the first transistor. The second output voltage terminal is located between the second transistor and ground. The first capacitor is configured to provide a first circuit path between the first output voltage terminal and the second output voltage terminal. The first circuit path functions as a short circuit for even harmonics of a fundamental frequency of the AC input signal but does not function as a short circuit for the fundamental frequency of the AC input signal.
摘要翻译：功率放大器，被配置为接收AC输入信号，并且经由第一输出电压端子和第二输出电压端子输出基于AC输入信号的输出电压。功率放大器包括以推挽配置连接的第一晶体管和第二晶体管，第一电感器，第二电感器和第一电容器。第一输出电压端子位于第一电感器和第一晶体管之间。第二输出电压端子位于第二晶体管和地之间。第一电容器被配置为提供第一输出电压端子和第二输出电压端子之间的第一电路路径。第一电路路径用作AC输入信号的基频的偶次谐波的短路，但不用作AC输入信号的基频的短路。

5. 发明授权

US08717103B2 Techniques to improve the stress issue in cascode power amplifier design 失效
标题翻译：改进共源共模功率放大器设计中的应力问题的技术
公开(公告)号：US08717103B2
公开(公告)日：2014-05-06
申请号：US13336857
申请日：2011-12-23
申请人： Poh Boon Leong , Ping Song , Sehat Sutardja
发明人： Poh Boon Leong , Ping Song , Sehat Sutardja
IPC分类号： H03F3/04
CPC分类号： H03F3/265 , H03F1/223 , H03F3/193 , H03F3/245 , H03F2200/306 , H03F2200/408 , H03F2200/534 , H03F2200/537 , H03F2200/541
摘要： An amplifier includes a first transistor, and a first inductor disposed between the first transistor and a voltage source. A first output node is between the first transistor and the first inductor. The amplifier further includes a second inductor disposed between the first transistor and ground. The amplifier further includes a second transistor, and a third inductor disposed between the second transistor and a ground. A second output node is between the second transistor and the third inductor. The amplifier further includes a fourth inductor disposed between the second transistor and the voltage source. The amplifier further includes a first capacitor disposed between the first output node and the second output node, and a second capacitor disposed between a first mid-node, which is between the first transistor and the first inductor, and a second mid-node, which is between the second transistor and fourth inductor.
摘要翻译：放大器包括第一晶体管和设置在第一晶体管和电压源之间的第一电感器。第一输出节点位于第一晶体管和第一电感器之间。放大器还包括设置在第一晶体管和地之间的第二电感器。放大器还包括第二晶体管，以及设置在第二晶体管和地之间的第三电感器。第二输出节点在第二晶体管和第三电感之间。放大器还包括设置在第二晶体管和电压源之间的第四电感器。所述放大器还包括设置在所述第一输出节点和所述第二输出节点之间的第一电容器，以及设置在所述第一晶体管和所述第一电感器之间的第一中间节点和第二中间节点之间的第二电容器，在第二晶体管和第四电感之间。

6. 发明授权

US06535069B2 High-frequency power amplifier module 失效
标题翻译：高频功率放大器模块
公开(公告)号：US06535069B2
公开(公告)日：2003-03-18
申请号：US10084364
申请日：2002-02-28
申请人： Toru Fujioka , Isao Yoshida , Mineo Katsueda , Masatoshi Morikawa , Yoshikuni Matsunaga , Kenji Sekine , Osamu Kagaya
发明人： Toru Fujioka , Isao Yoshida , Mineo Katsueda , Masatoshi Morikawa , Yoshikuni Matsunaga , Kenji Sekine , Osamu Kagaya
IPC分类号： H03F304
CPC分类号： H03F3/72 , H03F3/193 , H03F3/211 , H03F2200/306 , H03F2200/309 , H03F2200/39 , H03F2200/429 , H04B1/0053 , H04B1/0458
摘要： A radio frequency power amplifier module for a dual-band type mobile communication apparatus that can transmit and receive a first frequency f1 and second frequency f2 (f2=2×f1). It includes a drive stage amplifier having the gain peaks at f1 and f2 with a matching circuit and a radio frequency power output circuit including a radio frequency power output transistor. The output circuit has a transmission line connected to the drain end of the output transistor, a parallel resonance circuit connected in series to the transmission line to resonate at harmonics of a frequency twice the frequency f2, a series resonance circuit provided between one end of the resonance circuit and the ground to resonate at harmonics of a frequency twice the frequency f2 and an output matching circuit provided in series to the other end of the parallel resonance circuit for matching with f1 and f2.
摘要翻译：一种能够发送和接收第一频率f1和第二频率f2（f2 = 2xf1）的双频带型移动通信装置的射频功率放大器模块。它包括具有匹配电路的f1和f2处的增益峰值的驱动级放大器和包括射频功率输出晶体管的射频功率输出电路。输出电路具有连接到输出晶体管的漏极端的传输线，串联连接到传输线的并联谐振电路，以使谐振频率为频率f2的两倍的频率，串联谐振电路设置在谐振电路和接地谐振频率为频率f2的频率的谐波，以及与并联谐振电路的另一端串联设置的与f1和f2匹配的输出匹配电路。

7. 发明授权

US06366788B1 Mobile telephone system 失效
标题翻译：移动电话系统
公开(公告)号：US06366788B1
公开(公告)日：2002-04-02
申请号：US09674072
申请日：2000-10-26
申请人： Toru Fujioka , Isao Yoshida , Mineo Katsueda , Masatoshi Morikawa , Yoshikuni Matsunaga , Kenji Sekine , Osamu Kagaya
发明人： Toru Fujioka , Isao Yoshida , Mineo Katsueda , Masatoshi Morikawa , Yoshikuni Matsunaga , Kenji Sekine , Osamu Kagaya
IPC分类号： H04B138
CPC分类号： H04B1/006 , H03F3/193 , H03F3/604 , H03F3/72 , H03F2200/306 , H03F2200/309 , H03F2200/39 , H03F2200/429 , H04B1/005 , H04B1/406
摘要： In a mobile telephone apparatus corresponding to dual-band provided with an RF power module to operate in two kinds of different frequencies, a common harmonics control circuit is provided to the output circuit of such RF power module to realize higher efficiency in view of controlling respective harmonics power for both band frequencies. Moreover, a means for selectively setting the bias is also provided so that the maximum efficiency can be attained depending on the output power required with respective communication systems with the bias control signal output from the CPU of the control unit interlocking with selection of frequency of the mobile telephone apparatus body.
摘要翻译：在对应于具有以两种不同频率工作的RF功率模块的双频带的移动电话装置中，向这种RF功率模块的输出电路提供公共谐波控制电路，以实现更高的效率两个频段的谐波功率。此外，还提供了用于选择性地设置偏置的装置，使得可以根据各个通信系统所需的输出功率来获得最大效率，其中从控制单元的CPU输出的偏置控制信号与选择频率的移动电话机身。

8. 发明申请

US20180205351A1 Amplifier System for Use as High Sensitivity Selective Receiver Without Frequency Conversion 审中-公开
公开(公告)号：US20180205351A1
公开(公告)日：2018-07-19
申请号：US15916873
申请日：2018-03-09
申请人： DOCKON AG
发明人： Patrick Antoine Rada , Forrest James Brown , Alexandre Dupuy
IPC分类号： H03F3/193 , H03F3/195 , H04B1/22 , H03F3/72 , H03F1/56 , H03F1/38 , H03L7/06
CPC分类号： H03F3/193 , H03F1/38 , H03F1/56 , H03F3/195 , H03F3/72 , H03F2200/129 , H03F2200/147 , H03F2200/222 , H03F2200/237 , H03F2200/241 , H03F2200/243 , H03F2200/246 , H03F2200/261 , H03F2200/294 , H03F2200/297 , H03F2200/301 , H03F2200/306 , H03F2200/309 , H03F2200/387 , H03F2200/391 , H03F2200/399 , H03F2200/402 , H03F2200/438 , H03F2200/451 , H03F2200/462 , H03L7/06 , H04B1/22
摘要： An amplifying system is provided for use as a high sensitivity receive booster or replacement for a low noise amplifier in a receive chain of a communication device. The amplifying system includes an amplifying circuit configured to receive an input signal having a first frequency and generate an oscillation based on the input signal, a sampling circuit coupled to the amplifying circuit and configured to terminate the oscillation based on a predetermined threshold to periodically clamp and restart the oscillation to generate a series of pulses modulated by the oscillation and by the input signal, and one or more resonant circuits coupled with the amplifying circuit and configured to establish a frequency of operation and to generate an output signal having a second frequency, the second frequency being substantially the same as the first frequency.

9. 发明授权

US09973149B2 Source switched split LNA 有权
公开(公告)号：US09973149B2
公开(公告)日：2018-05-15
申请号：US15342016
申请日：2016-11-02
申请人： pSemi Corporation
发明人： Emre Ayranci , Miles Sanner
IPC分类号： H03F1/14 , H03F1/02 , H03F3/193 , H03F1/56
CPC分类号： H03F1/0277 , H03F1/086 , H03F1/565 , H03F3/193 , H03F3/195 , H03F3/72 , H03F2200/111 , H03F2200/18 , H03F2200/213 , H03F2200/222 , H03F2200/225 , H03F2200/243 , H03F2200/252 , H03F2200/294 , H03F2200/297 , H03F2200/301 , H03F2200/306 , H03F2200/321 , H03F2200/387 , H03F2200/391 , H03F2200/399 , H03F2200/411 , H03F2200/42 , H03F2200/429 , H03F2200/451 , H03F2200/48 , H03F2200/489 , H03F2200/492 , H03F2200/525 , H03F2200/61 , H03F2200/75 , H03F2203/7206 , H03F2203/7209 , H03F2203/7233
摘要： A receiver front end capable of receiving and processing intraband non-contiguous carrier aggregate (CA) signals using multiple low noise amplifiers (LNAs) is disclosed herein. A cascode having a “common source” configured input FET and a “common gate” configured output FET can be turned on or off using the gate of the output FET. A first switch is provided that allows a connection to be either established or broken between the source terminal of the input FET of each LNA. Further switches used for switching degeneration inductors, gate capacitors and gate to ground caps for each legs can be used to further improve the matching performance of the invention.

10. 发明申请

US20180083578A1 Cascode Amplifier Bias Circuits 审中-公开
公开(公告)号：US20180083578A1
公开(公告)日：2018-03-22
申请号：US15268229
申请日：2016-09-16
申请人： Peregrine Semiconductor Corporation
发明人： Jonathan Klaren , Poojan Wagh , David Kovac , Eric S. Shapiro , Neil Calanca , Dan William Nobbe , Christopher Murphy , Robert Mark Englekirk , Emre Ayranci , Keith Bargroff , Tero Tapio Ranta
IPC分类号： H03F1/22 , H03F1/30 , H03F1/56 , H03F3/193
CPC分类号： H03F1/223 , H03F1/301 , H03F1/56 , H03F3/193 , H03F3/195 , H03F3/213 , H03F3/245 , H03F2200/102 , H03F2200/105 , H03F2200/165 , H03F2200/18 , H03F2200/21 , H03F2200/222 , H03F2200/225 , H03F2200/243 , H03F2200/294 , H03F2200/297 , H03F2200/301 , H03F2200/306 , H03F2200/387 , H03F2200/391 , H03F2200/399 , H03F2200/42 , H03F2200/451 , H03F2200/48 , H03F2200/489 , H03F2200/492 , H03F2200/498 , H03F2200/555 , H03F2200/61 , H03F2200/78
摘要： Bias circuits and methods for silicon-based amplifier architectures that are tolerant of supply and bias voltage variations, bias current variations, and transistor stack height, and compensate for poor output resistance characteristics. Embodiments include power amplifiers and low-noise amplifiers that utilize a cascode reference circuit to bias the final stages of a cascode amplifier under the control of a closed loop bias control circuit. The closed loop bias control circuit ensures that the current in the cascode reference circuit is approximately equal to a selected multiple of a known current value by adjusting the gate bias voltage to the final stage of the cascode amplifier. The final current through the cascode amplifier is a multiple of the current in the cascode reference circuit, based on a device scaling factor representing the relative sizes of the transistor devices in the cascode amplifier and in the cascode reference circuit.

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