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1. 发明公开

US20230283237A1 Body Tie Optimization for Stacked Transistor Amplifier 审中-公开
公开(公告)号：US20230283237A1
公开(公告)日：2023-09-07
申请号：US18182047
申请日：2023-03-10
申请人： pSemi Corporation
发明人： Simon Edward Willard , Chris Olson , Tero Tapio Ranta
IPC分类号： H03F1/02 , H01L21/84 , H01L27/12 , H01L29/08 , H01L29/10 , H01L27/06 , H03F3/193 , H03F1/22 , H03F1/52 , H03F3/195 , H03F3/21
CPC分类号： H03F1/0205 , H01L28/40 , H01L21/84 , H01L27/1203 , H01L29/0847 , H01L29/1095 , H01L27/0688 , H03F3/193 , H03F1/223 , H03F1/523 , H03F3/195 , H03F3/21 , H03F2200/48 , H03F2200/297 , H03F2200/61 , H03F2200/451 , H03F2200/108 , H03F2200/42 , H03F2200/75
摘要： A transistor stack can include a combination of floating and body tied devices. Improved performance of the RF amplifier can be obtained by using a single body tied device as the input transistor of the stack, or as the output transistor of the stack, while other transistors of the stack are floating transistors. Transient response of the RF amplifier can be improved by using all body tied devices in the stack.

2. 发明授权

US11664769B2 Cascode amplifier bias circuits 有权
公开(公告)号：US11664769B2
公开(公告)日：2023-05-30
申请号：US17843372
申请日：2022-06-17
申请人： pSemi Corporation
发明人： Jonathan James Klaren , David Kovac , Eric S. Shapiro , Christopher C. Murphy , Robert Mark Englekirk , Keith Bargroff , Tero Tapio Ranta
IPC分类号： H03F1/22 , H03F3/195 , H03F3/213 , H03F3/24 , H03F1/30 , H03F1/56 , H03F3/193
CPC分类号： H03F1/223 , H03F1/301 , H03F1/56 , H03F3/193 , H03F3/195 , H03F3/213 , H03F3/245 , H03F2200/102 , H03F2200/105 , H03F2200/165 , H03F2200/18 , H03F2200/21 , H03F2200/222 , H03F2200/225 , H03F2200/243 , H03F2200/294 , H03F2200/297 , H03F2200/301 , H03F2200/306 , H03F2200/387 , H03F2200/391 , H03F2200/399 , H03F2200/42 , H03F2200/451 , H03F2200/48 , H03F2200/489 , H03F2200/492 , H03F2200/498 , H03F2200/555 , H03F2200/61 , H03F2200/78
摘要： Bias circuits and methods for silicon-based amplifier architectures that are tolerant of supply and bias voltage variations, bias current variations, and transistor stack height, and compensate for poor output resistance characteristics. Embodiments include power amplifiers and low-noise amplifiers that utilize a cascode reference circuit to bias the final stages of a cascode amplifier under the control of a closed loop bias control circuit. The closed loop bias control circuit ensures that the current in the cascode reference circuit is approximately equal to a selected multiple of a known current value by adjusting the gate bias voltage to the final stage of the cascode amplifier. The final current through the cascode amplifier is a multiple of the current in the cascode reference circuit, based on a device scaling factor representing the relative sizes of the transistor devices in the cascode amplifier and in the cascode reference circuit.

3. 发明授权

US10616518B2 Amplifier, and analog-to-digital conversion circuit and image sensor including the same 有权
公开(公告)号：US10616518B2
公开(公告)日：2020-04-07
申请号：US16008186
申请日：2018-06-14
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Yun-Hwan Jung , Sun-Yool Kang
IPC分类号： H04N5/374 , H04N5/3745 , H03F1/02 , H03F3/45 , H03M1/56 , H04N5/357
CPC分类号： H04N5/3745 , H03F1/0211 , H03F3/4521 , H03F3/45475 , H03M1/56 , H04N5/3575 , H04N5/37455 , H03F2200/129 , H03F2200/156 , H03F2200/297 , H03F2203/45116 , H03F2203/45156 , H03F2203/45536 , H03F2203/45544
摘要： An analog-to-digital conversion circuit includes a first amplifier that generates a first output signal by comparing a pixel signal output from a pixel array with a ramp signal, and a second amplifier that generates a comparison signal based on the first output signal. The first amplifier includes a first current source that generates a first bias current in a first operation period and a second operation period, and a second current source that generates a second bias current in the first operation period. The analog-to-digital conversion circuit converts an analog signal output from the pixel array into a digital signal.

4. 发明申请

US20190229686A1 RF Power Amplifier with Frequency Selective Impedance Matching Network 审中-公开
公开(公告)号：US20190229686A1
公开(公告)日：2019-07-25
申请号：US15879621
申请日：2018-01-25
申请人： Cree, Inc.
发明人： Haedong Jang , Timothy Canning , Bjoern Herrmann , Zulhazmi Mokhti , Frank Trang , Richard Wilson
IPC分类号： H03F3/189 , H03F3/24
CPC分类号： H03F3/189 , H03F1/0288 , H03F1/565 , H03F3/193 , H03F3/24 , H03F2200/222 , H03F2200/297 , H03F2200/301 , H03F2200/306 , H03F2200/309 , H03F2200/387 , H03F2200/391 , H03F2200/399 , H03F2200/451 , H03H7/01 , H03H7/0115 , H03H7/17 , H03H7/38
摘要： An amplifier circuit includes an input port, an output port, and a reference potential port, an RF amplifier device having an input terminal electrically coupled to the input port, an output terminal electrically coupled to the output port, and a reference potential terminal electrically coupled to the reference potential port. An impedance matching network is electrically connected to the output terminal, the reference potential port, and the output port. The impedance matching network includes a reactive efficiency optimization circuit that forms a parallel resonant circuit with a characteristic output impedance of the peaking amplifier at a center frequency of the fundamental frequency range. The impedance matching network includes a reactive frequency selective circuit that negates a phase shift of the RF signal in phase at the center frequency and exhibits a linear transfer characteristic in a baseband frequency range.

5. 发明申请

US20180083579A1 LNA with Programmable Linearity 有权
公开(公告)号：US20180083579A1
公开(公告)日：2018-03-22
申请号：US15272103
申请日：2016-09-21
申请人： Peregrine Semiconductor Corporation
发明人： Hossein Noori , Chih-Chieh Cheng
IPC分类号： H03F1/32 , H03F1/56 , H03F3/195 , H03G3/00 , H03G3/10
CPC分类号： H03F1/3205 , H03F1/56 , H03F3/195 , H03F3/72 , H03F2200/18 , H03F2200/21 , H03F2200/211 , H03F2200/213 , H03F2200/222 , H03F2200/225 , H03F2200/24 , H03F2200/243 , H03F2200/249 , H03F2200/27 , H03F2200/294 , H03F2200/297 , H03F2200/301 , H03F2200/306 , H03F2200/312 , H03F2200/387 , H03F2200/391 , H03F2200/399 , H03F2200/417 , H03F2200/451 , H03F2200/48 , H03F2200/489 , H03F2200/492 , H03F2200/495 , H03F2200/546 , H03F2200/72 , H03F2200/75 , H03G1/0029 , H03G1/0088 , H03G1/0094 , H03G3/001 , H03G3/008 , H03G3/10 , H03G2201/106 , H03G2201/307 , H03G2201/504
摘要： A receiver front end capable of receiving and processing intraband non-contiguous carrier aggregate (CA) signals using multiple low noise amplifiers (LNAs) is disclosed herein. A cascode having a “common source” input stage and a “common gate” output stage can be turned on or off using the gate of the output stage. A first switch is provided that allows a connection to be either established or broken between the source terminal of the input stage of each cascode. Further switches used for switching degeneration inductors, gate/sources caps and gate to ground caps for each legs can be used to further improve the matching performance of the invention.

6. 发明授权

US09755588B2 Signal output circuit 有权
公开(公告)号：US09755588B2
公开(公告)日：2017-09-05
申请号：US14779642
申请日：2014-03-27
申请人： Asahi Kasei Microdevices Corporation
发明人： Daisuke Matsuoka
IPC分类号： H03F1/02 , H03F3/45 , H03F3/00 , H02M3/07
CPC分类号： H03F3/005 , H02M3/07 , H03F1/0205 , H03F3/45076 , H03F3/45183 , H03F2200/297 , H03F2200/513 , H03F2203/45012 , H03F2203/45674
摘要： An object is to output output signal amplitude exceeding power supply voltage or output signal amplitude falling below ground voltage without requiring a charge pump circuit or the like to generate positive or negative power supply voltage for an operational amplifier. The present invention provides a signal output circuit comprising an operational amplifier including: an amplification stage configured to amplify differential input voltage; and an output stage configured to amplify an input signal amplified by the amplification stage and output the input signal as an output signal, wherein the output stage is a switched capacitor circuit which includes switches and a capacitor configured to sample differential voltage between input voltage outputted from the amplification stage and voltage other than the input voltage and which transfers the differential voltage sampled by the capacitor by switching of the switches based on the input voltage.

7. 发明申请

US20170230014A1 FULLY INTEGRATED LOW-NOISE AMPLIFIER 审中-公开
公开(公告)号：US20170230014A1
公开(公告)日：2017-08-10
申请号：US15229464
申请日：2016-08-05
申请人： STMicroelectronics SA
发明人： Raphael Paulin
IPC分类号： H03F1/56 , H04B5/00 , H03F3/195
CPC分类号： H03F1/565 , H03F1/086 , H03F1/223 , H03F3/195 , H03F2200/108 , H03F2200/181 , H03F2200/216 , H03F2200/294 , H03F2200/297 , H03F2200/301 , H03F2200/321 , H03F2200/336 , H03F2200/387 , H03F2200/391 , H03F2200/451 , H03F2200/48 , H03F2200/489 , H03F2200/492 , H03F2200/75 , H04B5/0081
摘要： A low-noise amplifier device includes an inductive input element, an amplifier circuit, an inductive output element and an inductive degeneration element. The amplifier device is formed in and on a semiconductor substrate. The semiconductor substrate supports metallization levels of a back end of line structure. The metal lines of the inductive input element, inductive output element and inductive degeneration element are formed within one or more of the metallization levels. The inductive input element has a spiral shape and the an amplifier circuit, an inductive output element and an inductive degeneration element are located within the spiral shape.

8. 发明申请

US20170093350A1 Multi-Stage Amplifier with Improved Operating Efficiency 有权
公开(公告)号：US20170093350A1
公开(公告)日：2017-03-30
申请号：US15232422
申请日：2016-08-09
申请人： Dialog Semiconductor (UK) Limited
发明人： Carlos Zamarreno Ramos , Ambreesh Bhattad , Frank Kronmueller
IPC分类号： H03F1/34 , H03F3/45 , H03F3/193
CPC分类号： H03F1/342 , H03F1/14 , H03F3/193 , H03F3/45179 , H03F3/45475 , H03F2200/135 , H03F2200/153 , H03F2200/297 , H03F2200/36 , H03F2200/411 , H03F2200/462 , H03F2200/474
摘要： A multi-stage amplifier, comprising a first amplifier stage is presented. The output of the first amplifier stage is coupled to a first terminal of a capacitor having a controllable capacitance. The input of a second amplifier stage is coupled to the output of the first amplifier stage and the first terminal of the capacitor. The output of the second amplifier stage is coupled to a second terminal of the capacitor and an output of the multi-stage amplifier. The input of a current sensing circuit is coupled with the output of the multi-stage amplifier. A control signal generator is coupled between the output of the current sensing circuit and a control terminal of the capacitor. The control signal generator provides a control signal to the capacitor in order to control or vary the capacitance of the capacitor.

9. 发明授权

US09571044B1 RF power transistors with impedance matching circuits, and methods of manufacture thereof 有权
标题翻译：具有阻抗匹配电路的RF功率晶体管及其制造方法
公开(公告)号：US09571044B1
公开(公告)日：2017-02-14
申请号：US14919513
申请日：2015-10-21
申请人： FREESCALE SEMICONDUCTOR, INC.
发明人： Ning Zhu , Damon G. Holmes , Jeffrey K. Jones
IPC分类号： H03F3/04 , H03F1/42 , H03F3/193 , H03F1/56
CPC分类号： H03F1/565 , H01L23/66 , H01L2223/6655 , H01L2224/48091 , H01L2224/4813 , H01L2224/48137 , H01L2224/49175 , H03F3/195 , H03F2200/108 , H03F2200/181 , H03F2200/216 , H03F2200/222 , H03F2200/225 , H03F2200/297 , H03F2200/301 , H03F2200/309 , H03F2200/387 , H03F2200/391 , H03F2200/402 , H03F2200/451 , H03F2200/552 , H03F2200/75 , H01L2924/00014
摘要： Embodiments of an RF amplifier include a transistor with a control terminal and first and second current carrying terminals, and a shunt circuit coupled between the first current carrying terminal and a ground reference node. The shunt circuit includes a first shunt inductance, a second shunt inductance, and a shunt capacitor coupled in series. The second shunt inductance and the shunt capacitor form a series resonant circuit in proximity to a center operating frequency of the amplifier, and an RF cold point node is present between the first and second shunt inductances. The RF amplifier also includes a video bandwidth circuit coupled between the RF cold point node and the ground reference node.
摘要翻译： RF放大器的实施例包括具有控制端子和第一和第二载流端子的晶体管，以及耦合在第一载流端子和接地参考节点之间的分流电路。分路电路包括第一并联电感，第二并联电感和串联耦合的并联电容器。第二并联电感和并联电容器在放大器的中心工作频率附近形成串联谐振电路，并且RF冷点节点存在于第一和第二分流电感之间。 RF放大器还包括耦合在RF冷点节点和接地参考节点之间的视频带宽电路。

10. 发明申请

US20160218685A1 MULTI-STAGE TRACK-AND-HOLD AMPLIFIER 有权
标题翻译：多级跟踪和保持放大器
公开(公告)号：US20160218685A1
公开(公告)日：2016-07-28
申请号：US15092215
申请日：2016-04-06
申请人： SEMTECH CORPORATION
发明人： Sandeep Louis D'SOUZA , Kenneth Colin DYER , Raghava Manas BACHU
IPC分类号： H03F3/16
CPC分类号： H03F3/16 , G11C27/02 , H03F2200/297 , H03F2200/411
摘要： Examples are provided for a multi-stage track-and-hold circuit (THA). The multi-stage THA may include a first stage, a second stage, and a third stage. The first stage may be coupled to an input signal and configured to sample the input signal. The second stage may be coupled to the first stage and may include a buffer circuit. The third stage may be coupled to the second stage and can include a bootstrapped THA. The first stage may further include a shunted source-follower circuit and a switched source-follower circuit. The shunted source-follower circuit may include a first switch that can be operable to couple an output node of the shunted source-follower circuit to ground potential.
摘要翻译：为多级跟踪保持电路（THA）提供了实例。多级THA可以包括第一级，第二级和第三级。第一级可以耦合到输入信号并被配置为对输入信号进行采样。第二级可以耦合到第一级，并且可以包括缓冲器电路。第三级可以耦合到第二级并且可以包括引导的THA。第一级还可以包括分流源跟随器电路和开关源跟随器电路。分流源跟随器电路可以包括第一开关，其可操作以将分流源跟随器电路的输出节点耦合到地电位。

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