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1. 发明申请

US20180233442A1 FABRICATION METHOD OF LAYER STRUCTURE FOR MOUNTING SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：US20180233442A1
公开(公告)日：2018-08-16
申请号：US15950734
申请日：2018-04-11
申请人： Siliconware Precision Industries Co., Ltd.
发明人： Fang-Lin Tsai , Yi-Feng Chang , Cheng-Jen Liu , Yi-Min Fu , Hung-Chi Chen
IPC分类号： H01L23/498 , H01L21/265 , H01L29/78 , H01L29/762 , H01L21/48
CPC分类号： H01L23/49827 , H01L21/26533 , H01L21/486 , H01L29/762 , H01L29/7834 , H01L2224/16225 , H01L2924/0002 , H01L2924/00
摘要： A fabrication method of a layer structure for mounting a semiconductor device is provided, which includes the steps of: providing a base material, wherein the base material has a conductive layer having a first surface having a plurality of first conductive elements and an opposite second surface having a plurality of second conductive elements, and a first encapsulant formed on the first surface of the conductive layer for encapsulating the first conductive elements; partially removing the conductive layer to form a circuit layer that electrically connects the first conductive elements and the second conductive elements; and forming a second encapsulant on a bottom surface of the first encapsulant for encapsulating the circuit layer and the second conductive elements, thus reducing the fabrication difficulty and increasing the product yield.

2. 发明授权

US5258625A Interband single-electron tunnel transistor and integrated circuit 失效
标题翻译：带间单电子隧道晶体管和集成电路
公开(公告)号：US5258625A
公开(公告)日：1993-11-02
申请号：US961547
申请日：1992-10-15
申请人： Shiroo Kamohara , Toru Toyabe , Kozo Katayama , Shuichi Yamamoto , Sigeo Ihara
发明人： Shiroo Kamohara , Toru Toyabe , Kozo Katayama , Shuichi Yamamoto , Sigeo Ihara
IPC分类号： H01L21/82 , H01L21/8232 , H01L21/8244 , H01L27/06 , H01L27/095 , H01L27/10 , H01L27/11 , H01L27/118 , H01L29/66 , H01L29/68 , H01L29/72 , H01L29/762 , H01L29/80 , H01L29/88 , H03K19/02
CPC分类号： B82Y10/00 , B82Y30/00 , H01L27/118 , H01L29/72 , H01L29/762 , H01L29/88 , H03K19/02 , Y10S977/937
摘要： An interband single-electron tunnel transistor utilizes an interband single-electron tunneling phenomenon between a valence band and a conduction band through a p-n junction. The transistor includes the combination of microcapacities as fundamental constituent elements each formed by joining a p-type semiconductor material doped with an impurity in the degree of concentration with which a Fermi level overlaps a valence band and an n-type semiconductor material doped with an impurity in the degree of concentration with which the Fermi level overlaps a conduction band. The microcapacity includes a p-n junction having a junction area with which interband electron tunneling is inhibited due to Coulomb blockade.
摘要翻译：带间单电子隧道晶体管利用通过p-n结的价带和导带之间的带间单电子隧道现象。晶体管包括作为基本构成元件的微电容的组合，其通过将掺杂有杂质的p型半导体材料以费米能级与价带重叠的浓度与掺杂有杂质的n型半导体材料接合而形成在费米能级与导带重叠的浓度下。微容量包括具有结区的p-n结，由于库仑阻挡，带间电子隧道被阻止。

3. 发明申请

US20150206814A1 LAYER STRUCTURE FOR MOUNTING SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF 有权
标题翻译：用于安装半导体器件的层结构及其制造方法
公开(公告)号：US20150206814A1
公开(公告)日：2015-07-23
申请号：US14290217
申请日：2014-05-29
申请人： SILICONWARE PRECISION INDUSTRIES CO., LTD.
发明人： Fang-Lin Tsai , Yi-Feng Chang , Cheng-Jen Liu , Yi-Min Fu , Hung-Chi Chen
IPC分类号： H01L23/14 , H01L21/48
CPC分类号： H01L23/49827 , H01L21/26533 , H01L21/486 , H01L29/762 , H01L29/7834 , H01L2224/16225 , H01L2924/0002 , H01L2924/00
摘要： A fabrication method of a layer structure for mounting a semiconductor device is provided, which includes the steps of: providing a base material, wherein the base material has a conductive layer having a first surface having a plurality of first conductive elements and an opposite second surface having a plurality of second conductive elements, and a first encapsulant formed on the first surface of the conductive layer for encapsulating the first conductive elements; partially removing the conductive layer to form a circuit layer that electrically connects the first conductive elements and the second conductive elements; and forming a second encapsulant on a bottom surface of the first encapsulant for encapsulating the circuit layer and the second conductive elements, thus reducing the fabrication difficulty and increasing the product yield.
摘要翻译：提供一种用于安装半导体器件的层结构的制造方法，其包括以下步骤：提供基材，其中所述基材具有导电层，所述导电层具有第一表面，所述第一表面具有多个第一导电元件和相对的第二表面具有多个第二导电元件，以及第一密封剂，其形成在所述导电层的第一表面上，用于封装所述第一导电元件; 部分去除所述导电层以形成电连接所述第一导电元件和所述第二导电元件的电路层; 以及在所述第一密封剂的底表面上形成用于封装所述电路层和所述第二导电元件的第二密封剂，从而降低制造难度并提高产品产率。

4. 发明授权

US4176369A Image sensor having improved moving target discernment capabilities 失效
公开(公告)号：US4176369A
公开(公告)日：1979-11-27
申请号：US857633
申请日：1977-12-05
申请人： Richard D. Nelson , A. James Hughes
发明人： Richard D. Nelson , A. James Hughes
IPC分类号： H01L21/339 , H01L27/148 , H01L29/76 , H01L29/762 , H01L29/772 , H01L29/78 , H01L31/00
CPC分类号： H01L29/762 , H01L27/14831 , H01L27/14875
摘要： A semiconductor image sensor comprises an array of charge collection elements buried within the semiconductor for collecting charge photogenerated in response to the image. This sensor is easily configured to discern changes in an image. One or more charge transfer devices (CTD's) of an array are associated with each column of charge collection elements. For readout, the charge collected by each charge collection element is transferred to an associated storage cell of an array CTD associated with the column in which that charge collection element is disposed.For discernment of moving targets or image changes, a difference between the charge collected by a given charge collection element during a first frame and a second frame is determined. To discern a moving target, each column of charge collection elements has a first and a second array CTD associated therewith and a first image frame of charge is collected, transferred to and stored in the channels of the first array CTD's, after which a second image frame of charge is collected, transferred to and stored in the channels of the second array CTD's. The charges in the first and second array CTD's are then read out in parallel, thereby transferring the image frames in parallel. Output CTD channels positioned to accept charge from the channels of the array CTD's have special charge transfer control structures for transferring the charge from the channels of the array's first CTD's to the channel of a first output CTD and from the channels of the array's second CTD's to the channel of a second output CTD to ensure that parallel transfer of the image frames continues in the output CTD's. This parallel in the array, parallel in the output (parallel-parallel) CTD transfer architecture minimizes interframe cross-talk and maximizes resolution. Interleaved first and second array CTD's to which charge may be selectively transferred are achieved by splitting the propagation electrodes for one phase into two electrodes each in order to control charge transfer from the charge collectors to the first and second associated CTD's independently.The CTD's (array and output together) may be combined with a prior art single-frame-at-a-time imager to form a system which appears (at the external system output) to be the same as the monolithic structure.

5. 发明授权

US07923353B2 Gettering method and a wafer using the same 有权
标题翻译：吸气方法和使用其的晶片
公开(公告)号：US07923353B2
公开(公告)日：2011-04-12
申请号：US11389087
申请日：2006-03-27
申请人： Jari Mäkinen
发明人： Jari Mäkinen
IPC分类号： H01L21/321
CPC分类号： H01L21/3226 , H01L21/67253 , H01L21/76256 , H01L29/762
摘要： It is shown in the invention a method for manufacturing a semiconductor wafer structure with an active layer for impurity removal, which method comprises phases of depositing a first layer on a first wafer surface for providing an active layer, an optional phase of preparation for said first layer for next phase, growing thermal oxide layer on a second wafer, bonding said first and second wafers into a stack, annealing the stack for a crystalline formation in said thermal oxide layer as a second layer, and thinning said first wafer to a pre-determined thickness. The invention concerns also a wafer manufactured according to the method, chip that utilizes such a wafer structure and an electronic device utilizing such a chip.
摘要翻译：在本发明中示出了一种用于制造具有用于杂质去除的有源层的半导体晶片结构的方法，该方法包括在第一晶片表面上沉积第一层以提供有源层的阶段，用于所述第一层，用于在第二晶片上生长热氧化物层，将所述第一和第二晶片结合成堆叠，将所述堆叠退火以在所述热氧化物层中的结晶形成作为第二层，以及将所述第一晶片细化为预制的，确定厚度。本发明还涉及根据该方法制造的晶片，利用这种晶片结构的芯片和利用这种芯片的电子器件。

6. 发明授权

US5422496A Interband single-electron tunnel transistor and integrated circuit 失效
标题翻译：带间单电子隧道晶体管和集成电路
公开(公告)号：US5422496A
公开(公告)日：1995-06-06
申请号：US117801
申请日：1993-09-08
申请人： Shiroo Kamohara , Toru Toyabe , Kozo Katayama , Shuichi Yamamoto , Sigeo Ihara
发明人： Shiroo Kamohara , Toru Toyabe , Kozo Katayama , Shuichi Yamamoto , Sigeo Ihara
IPC分类号： H01L21/82 , H01L21/8232 , H01L21/8244 , H01L27/06 , H01L27/095 , H01L27/10 , H01L27/11 , H01L27/118 , H01L29/66 , H01L29/68 , H01L29/72 , H01L29/762 , H01L29/80 , H01L29/88 , H03K19/02
CPC分类号： B82Y10/00 , B82Y30/00 , H01L27/118 , H01L29/72 , H01L29/762 , H01L29/88 , H03K19/02 , Y10S977/937
摘要： An interband single-electron tunnel/transistor utilizes an interband single-electron tunneling phenomenon between a valence band and a conduction band through a p-n junction. The transistor includes the combination of microcapacities as fundamental constituent elements each formed by joining a p-type semiconductor material doped with an impurity in the degree of concentration with which a Fermi level overlaps a valence band and an n-type semiconductor material doped with an impurity in the degree of concentration with which the Fermi level overlaps a conduction band. The microcapacity includes a p-n junction having a junction area with which interband electron tunneling is inhibited due to Coulomb blockade.
摘要翻译：带间单电子隧道/晶体管利用通过p-n结的价带和导带之间的带间单电子隧道现象。晶体管包括作为基本构成元件的微电容的组合，其通过将掺杂有杂质的p型半导体材料以费米能级与价带重叠的浓度与掺杂有杂质的n型半导体材料接合而形成在费米能级与导带重叠的浓度下。微容量包括具有结区的p-n结，由于库仑阻挡，带间电子隧穿被阻止。

7. 发明授权

US08659109B2 Image sensor photodiode 有权
标题翻译：图像传感器光电二极管
公开(公告)号：US08659109B2
公开(公告)日：2014-02-25
申请号：US12984067
申请日：2011-01-04
申请人： François Roy
发明人： François Roy
IPC分类号： H01L31/00
CPC分类号： H01L27/14603 , H01L27/14612 , H01L27/1463 , H01L27/14632 , H01L27/1464 , H01L27/14641 , H01L27/14645 , H01L27/14687 , H01L27/14689 , H01L29/762
摘要： An image sensor including a plurality of pixels each including a charge collection region including an N-type region bounded by P-type regions and having an overlying P-type layer; and an insulated gate electrode positioned over the P-type layer and arranged to receive a gate voltage for conveying charges stored in the charge collection region through the P-type layer.
摘要翻译：一种图像传感器，包括多个像素，每个像素包括包含由P型区域限定并具有上覆P型层的N型区域的电荷收集区域; 以及绝缘栅电极，其位于所述P型层上并被布置成接收用于通过所述P型层传送存储在所述电荷收集区域中的电荷的栅极电压。

8. 发明申请

US20110183709A1 IMAGE SENSOR PHOTODIODE 有权
标题翻译：图像传感器光电二极管
公开(公告)号：US20110183709A1
公开(公告)日：2011-07-28
申请号：US12984067
申请日：2011-01-04
申请人： François Roy
发明人： François Roy
IPC分类号： H04M1/00 , H01L31/113 , H01L31/18
CPC分类号： H01L27/14603 , H01L27/14612 , H01L27/1463 , H01L27/14632 , H01L27/1464 , H01L27/14641 , H01L27/14645 , H01L27/14687 , H01L27/14689 , H01L29/762
摘要： An image sensor including a plurality of pixels each including a charge collection region including an N-type region bounded by P-type regions and having an overlying P-type layer; and an insulated gate electrode positioned over the P-type layer and arranged to receive a gate voltage for conveying charges stored in the charge collection region through the P-type layer.
摘要翻译：一种图像传感器，包括多个像素，每个像素包括包含由P型区域限定并具有上覆P型层的N型区域的电荷收集区域; 以及绝缘栅电极，其位于所述P型层上并被布置成接收用于通过所述P型层传送存储在所述电荷收集区域中的电荷的栅极电压。

9. 发明授权

US5742071A Wiringless logical operation circuits 失效
标题翻译：无线逻辑运算电路
公开(公告)号：US5742071A
公开(公告)日：1998-04-21
申请号：US695533
申请日：1996-08-12
申请人： Shiroo Kamohara , Peter M. Lee , Hitoshi Matsuo , Sigeo Ihara
发明人： Shiroo Kamohara , Peter M. Lee , Hitoshi Matsuo , Sigeo Ihara
IPC分类号： H01L27/118 , H01L29/762 , H03K19/02 , H01L29/06 , H01L31/0328 , H01L31/0336
CPC分类号： B82Y10/00 , H01L27/118 , H01L29/762 , H03K19/02 , Y10S977/937
摘要： A logical operation circuit in which wiring as generally performed between transistors is made unnecessary to improve reliability, stability and integration degree of a logical circuit using a tunnel phenomenon, for example, a single-electron tunnel phenomenon, or a flight phenomenon of a particle group. Conducting materials are arranged in a two-dimensional plane or three-dimensional space in the logical circuit. When two conducting materials are arranged to be nearest each other, the two conducting materials are connected, for example, by a single-electron tunnel phenomenon. When two conducting materials are arranged to be not nearest, there is no connection between the conducting materials by the tunnel phenomenon. Propagation of electrons is controlled by changing the arrangement. Further, because particles which have entered input regions move toward different flight directions respectively from a branch region on the basis of the property that two particles cannot enter simultaneously within an effective scatter distance by repulsive interaction between particles, flight of particles is controlled so as to enter or not branched particles into an observation region to thereby construct a wiringless logical operation circuit.
摘要翻译：不需要通常在晶体管之间进行的布线的逻辑运算电路，以提高使用隧道现象（例如单电子隧道现象）或粒子群的飞行现象的逻辑电路的可靠性，稳定性和集成度。导电材料被布置在逻辑电路中的二维平面或三维空间中。当两个导电材料被布置成彼此最接近时，例如通过单电子隧道现象连接两个导电材料。当两个导电材料被布置为不是最近时，导电材料之间没有通过隧道现象的连接。通过改变电极来控制电子的传播。此外，由于进入输入区域的颗粒基于两个颗粒不能通过颗粒之间的排斥相互作用而在有效散射距离内不能同时进入的特性从分支区域移动到不同的飞行方向，所以粒子的飞行被控制为进入或不分支的颗粒进入观察区域，从而构成无线逻辑运算电路。

10. 发明授权

US12133475B2 Component having a band assembly for individual electron movement over a long distance 有权
公开(公告)号：US12133475B2
公开(公告)日：2024-10-29
申请号：US17636522
申请日：2020-09-01
申请人： Rheinisch-Westfälische Technische Hochschule (RWTH) Aachen , Forschungszentrum Jülich GmbH
发明人： Inga Seidler , Hendrik Bluhm , Lars Schreiber , Matthias Künne
IPC分类号： H10N60/10 , B82Y10/00 , G06N10/00 , G06N10/40 , H01L29/40 , H01L29/762
CPC分类号： H10N60/128 , G06N10/00 , G06N10/40 , H01L29/401 , H01L29/762 , H10N60/11 , B82Y10/00
摘要： An electronic component (10, 110) is designed as a semiconductor or with a semiconductor-like structure for moving a quantum dot (68, 168) over a distance. The electronic component (10, 110) comprises a substrate (32, 132) having a two-dimensional electron gas or electron hole gas. A gate electrode assembly (16, 18, 20, 116, 118, 120) having gate electrodes (38, 40, 42, 44, 138, 140, 142, 144) is arranged on a surface (31, 131) of the electronic component (10, 110). The gate electrode assembly (16, 18, 20, 116, 118, 120) produces a potential well (66, 166) in the substrate (32, 132). Electrical terminals for connecting the gate electrode assembly (16, 18, 20, 116, 118, 120) to voltage sources are provided for this purpose. The disclosure further relates to a method for such an electronic component (10, 110).

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