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1. 发明授权

US5258625A Interband single-electron tunnel transistor and integrated circuit 失效
标题翻译：带间单电子隧道晶体管和集成电路
公开(公告)号：US5258625A
公开(公告)日：1993-11-02
申请号：US961547
申请日：1992-10-15
申请人： Shiroo Kamohara , Toru Toyabe , Kozo Katayama , Shuichi Yamamoto , Sigeo Ihara
发明人： Shiroo Kamohara , Toru Toyabe , Kozo Katayama , Shuichi Yamamoto , Sigeo Ihara
IPC分类号： H01L21/82 , H01L21/8232 , H01L21/8244 , H01L27/06 , H01L27/095 , H01L27/10 , H01L27/11 , H01L27/118 , H01L29/66 , H01L29/68 , H01L29/72 , H01L29/762 , H01L29/80 , H01L29/88 , H03K19/02
CPC分类号： B82Y10/00 , B82Y30/00 , H01L27/118 , H01L29/72 , H01L29/762 , H01L29/88 , H03K19/02 , Y10S977/937
摘要： An interband single-electron tunnel transistor utilizes an interband single-electron tunneling phenomenon between a valence band and a conduction band through a p-n junction. The transistor includes the combination of microcapacities as fundamental constituent elements each formed by joining a p-type semiconductor material doped with an impurity in the degree of concentration with which a Fermi level overlaps a valence band and an n-type semiconductor material doped with an impurity in the degree of concentration with which the Fermi level overlaps a conduction band. The microcapacity includes a p-n junction having a junction area with which interband electron tunneling is inhibited due to Coulomb blockade.
摘要翻译：带间单电子隧道晶体管利用通过p-n结的价带和导带之间的带间单电子隧道现象。晶体管包括作为基本构成元件的微电容的组合，其通过将掺杂有杂质的p型半导体材料以费米能级与价带重叠的浓度与掺杂有杂质的n型半导体材料接合而形成在费米能级与导带重叠的浓度下。微容量包括具有结区的p-n结，由于库仑阻挡，带间电子隧道被阻止。

2. 发明授权

US5422496A Interband single-electron tunnel transistor and integrated circuit 失效
标题翻译：带间单电子隧道晶体管和集成电路
公开(公告)号：US5422496A
公开(公告)日：1995-06-06
申请号：US117801
申请日：1993-09-08
申请人： Shiroo Kamohara , Toru Toyabe , Kozo Katayama , Shuichi Yamamoto , Sigeo Ihara
发明人： Shiroo Kamohara , Toru Toyabe , Kozo Katayama , Shuichi Yamamoto , Sigeo Ihara
IPC分类号： H01L21/82 , H01L21/8232 , H01L21/8244 , H01L27/06 , H01L27/095 , H01L27/10 , H01L27/11 , H01L27/118 , H01L29/66 , H01L29/68 , H01L29/72 , H01L29/762 , H01L29/80 , H01L29/88 , H03K19/02
CPC分类号： B82Y10/00 , B82Y30/00 , H01L27/118 , H01L29/72 , H01L29/762 , H01L29/88 , H03K19/02 , Y10S977/937
摘要： An interband single-electron tunnel/transistor utilizes an interband single-electron tunneling phenomenon between a valence band and a conduction band through a p-n junction. The transistor includes the combination of microcapacities as fundamental constituent elements each formed by joining a p-type semiconductor material doped with an impurity in the degree of concentration with which a Fermi level overlaps a valence band and an n-type semiconductor material doped with an impurity in the degree of concentration with which the Fermi level overlaps a conduction band. The microcapacity includes a p-n junction having a junction area with which interband electron tunneling is inhibited due to Coulomb blockade.
摘要翻译：带间单电子隧道/晶体管利用通过p-n结的价带和导带之间的带间单电子隧道现象。晶体管包括作为基本构成元件的微电容的组合，其通过将掺杂有杂质的p型半导体材料以费米能级与价带重叠的浓度与掺杂有杂质的n型半导体材料接合而形成在费米能级与导带重叠的浓度下。微容量包括具有结区的p-n结，由于库仑阻挡，带间电子隧穿被阻止。

3. 发明授权

US5323344A Quantum memory device 失效
标题翻译：量子存储器件
公开(公告)号：US5323344A
公开(公告)日：1994-06-21
申请号：US000880
申请日：1993-01-05
申请人： Kozo Katayama , Shiroo Kamohara
发明人： Kozo Katayama , Shiroo Kamohara
IPC分类号： G06N99/00 , G11C11/44 , H01L27/18 , H01L29/66 , H01L39/22 , H01L39/10
CPC分类号： G06N99/002 , B82Y10/00 , G11C11/44 , H01L27/18 , Y10S505/832 , Y10S505/841
摘要： A quantum memory device in which a memory operation is enabled even if the structure of a Josephson device is reduced in size. Each memory cell of the quantum memory device includes a superconducting quantum interference device having two Josephson junctions, a write word line for supplying a current to the superconducting quantum interference device, a write data line and a magnetic field detection line magnetically coupled with the superconducting quantum interference device, a three-terminal switching device for turning a signal of the magnetic field detection line on and off to transfer the signal to a read data line, and a read word line connected to a gate of the three-terminal switching device. The junction area of the Josephson junction is made small to oscillate a magnetic flux so that information is stored in accordance with the phase of oscillation of the magnetic flux. An induced current produced by an oscillating flux of a dummy cell and an induced current produced by an oscillating flux of each memory cell are compared to detect the phases of flux oscillation of the dummy and memory cells, thereby reading information.
摘要翻译：即使约瑟夫逊装置的结构尺寸减小，也能够进行存储器操作的量子存储装置。量子存储器件的每个存储单元包括具有两个约瑟夫逊结的超导量子干涉器件，用于向超导量子干涉器件提供电流的写字线，与超导量子磁耦合的写数据线和磁场检测线干扰装置，用于使磁场检测线的信号接通和断开以将信号传送到读取数据线的三端子开关装置，以及连接到三端子开关装置的栅极的读取字线。约瑟夫逊结的接合区域被做得很小以振荡磁通量，从而根据磁通量的振荡相位来存储信息。比较由虚拟单元的振荡磁通产生的感应电流和由每个存储单元的振荡磁通产生的感应电流，以检测虚拟和存储单元的磁通振荡的相位，从而读取信息。

4. 发明授权

US08017986B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08017986B2
公开(公告)日：2011-09-13
申请号：US12718111
申请日：2010-03-05
申请人： Toshihiro Tanaka , Yukiko Umemoto , Mitsuru Hiraki , Yutaka Shinagawa , Masamichi Fujito , Kazufumi Suzukawa , Hiroyuki Tanikawa , Takashi Yamaki , Yoshiaki Kamigaki , Shinichi Minami , Kozo Katayama , Nozomu Matsuzaki
发明人： Toshihiro Tanaka , Yukiko Umemoto , Mitsuru Hiraki , Yutaka Shinagawa , Masamichi Fujito , Kazufumi Suzukawa , Hiroyuki Tanikawa , Takashi Yamaki , Yoshiaki Kamigaki , Shinichi Minami , Kozo Katayama , Nozomu Matsuzaki
IPC分类号： H01L29/788
CPC分类号： G11C16/26 , G11C5/025 , G11C8/08 , G11C16/04 , G11C16/0425 , G11C16/0433 , G11C16/08 , G11C16/24 , G11C16/30 , H01L21/28 , H01L21/28273 , H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11526 , H01L27/11546 , H01L29/42328 , H01L29/42332 , H01L29/4234 , H01L29/66825 , H01L29/7885 , H01L29/792
摘要： A semiconductor device includes a plurality of nonvolatile memory cells (1). Each of the nonvolatile memory cells comprises a MOS type first transistor section (3) used for information storage, and a MOS type second transistor section (4) which selects the first transistor section. The second transistor section has a bit line electrode (16) connected to a bit line, and a control gate electrode (18) connected to a control gate control line. The first transistor section has a source line electrode (10) connected to a source line, a memory gate electrode (14) connected to a memory gate control line, and a charge storage region (11) disposed directly below the memory gate electrode. A gate withstand voltage of the second transistor section is lower than that of the first transistor section. Assuming that the thickness of a gate insulating film of the second transistor section is defined as tc and the thickness of a gate insulating film of the first transistor section is defined as tm, they have a relationship of tc
摘要翻译：半导体器件包括多个非易失性存储单元（1）。每个非易失性存储单元包括用于信息存储的MOS型第一晶体管部分（3）和选择第一晶体管部分的MOS型第二晶体管部分（4）。第二晶体管部分具有连接到位线的位线电极（16）和连接到控制栅极控制线的控制栅电极（18）。第一晶体管部分具有连接到源极线的源极线电极（10），连接到存储器栅极控制线的存储栅电极（14）和直接位于存储栅电极下方的电荷存储区域（11）。第二晶体管部分的栅极耐受电压低于第一晶体管部分的栅极耐受电压。假设第二晶体管部分的栅极绝缘膜的厚度被定义为tc，并且第一晶体管部分的栅极绝缘膜的厚度被定义为tm，它们具有tc

5. 发明授权

US07414283B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07414283B2
公开(公告)日：2008-08-19
申请号：US11415129
申请日：2006-05-02
申请人： Toshihiro Tanaka , Yukiko Umemoto , Mitsuru Hiraki , Yutaka Shinagawa , Masamichi Fujito , Kazufumi Suzukawa , Hiroyuki Tanikawa , Takashi Yamaki , Yoshiaki Kamigaki , Shinichi Minami , Kozo Katayama , Nozomu Matsuzaki
发明人： Toshihiro Tanaka , Yukiko Umemoto , Mitsuru Hiraki , Yutaka Shinagawa , Masamichi Fujito , Kazufumi Suzukawa , Hiroyuki Tanikawa , Takashi Yamaki , Yoshiaki Kamigaki , Shinichi Minami , Kozo Katayama , Nozomu Matsuzaki
IPC分类号： H01L29/788
CPC分类号： G11C16/26 , G11C5/025 , G11C8/08 , G11C16/04 , G11C16/0425 , G11C16/0433 , G11C16/08 , G11C16/24 , G11C16/30 , H01L21/28 , H01L21/28273 , H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11526 , H01L27/11546 , H01L29/42328 , H01L29/42332 , H01L29/4234 , H01L29/66825 , H01L29/7885 , H01L29/792
摘要： A semiconductor device includes a plurality of nonvolatile memory cells (1). Each of the nonvolatile memory cells comprises a MOS type first transistor section (3) used for information storage, and a MOS type second transistor section (4) which selects the first transistor section. The second transistor section has a bit line electrode (16) connected to a bit line, and a control gate electrode (18) connected to a control gate control line. The first transistor section has a source line electrode (10) connected to a source line, a memory gate electrode (14) connected to a memory gate control line, and a charge storage region (11) disposed directly below the memory gate electrode. A gate withstand voltage of the second transistor section is lower than that of the first transistor section. Assuming that the thickness of a gate insulating film of the second transistor section is defined as tc and the thickness of a gate insulating film of the first transistor section is defined as tm, they have a relationship of tc
摘要翻译：半导体器件包括多个非易失性存储单元（1）。每个非易失性存储单元包括用于信息存储的MOS型第一晶体管部分（3）和选择第一晶体管部分的MOS型第二晶体管部分（4）。第二晶体管部分具有连接到位线的位线电极（16）和连接到控制栅极控制线的控制栅电极（18）。第一晶体管部分具有连接到源极线的源极线电极（10），连接到存储器栅极控制线的存储栅电极（14）和直接位于存储栅电极下方的电荷存储区域（11）。第二晶体管部分的栅极耐受电压低于第一晶体管部分的栅极耐受电压。假设第二晶体管部分的栅极绝缘膜的厚度被定义为tc，并且第一晶体管部分的栅极绝缘膜的厚度被定义为tm，它们具有tc

6. 发明授权

US07190023B2 Semiconductor integrated circuit having discrete trap type memory cells 失效
标题翻译：具有离散陷阱型存储单元的半导体集成电路
公开(公告)号：US07190023B2
公开(公告)日：2007-03-13
申请号：US11320850
申请日：2005-12-30
申请人： Yoshiaki Kamigaki , Shinichi Minami , Kozo Katayama , Masataka Kato
发明人： Yoshiaki Kamigaki , Shinichi Minami , Kozo Katayama , Masataka Kato
IPC分类号： H01L29/788
CPC分类号： G11C16/0475 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L29/42332 , H01L29/7887
摘要： A multi-storage nonvolatile memory of high density, high speed and high reliability has a memory transistor and switch transistors disposed on both the sides of the memory transistor. The memory transistor includes a gate insulating film having discrete traps and a memory gate electrode, whereas the switch transistors include switch gate electrodes. The gate insulating film has the discrete traps for storing information charge, can locally inject carriers, and one memory cell constitutes a multi-storage cell for storing at least information of 2 bits. The switch transistors having the switch gate electrodes realize source side injection. The memory transistor is fommed together with the switch transistors in self-aligned diffusion. The memory gate electrode of the memory transistor is connected to a word line so as to perform word-line erase.
摘要翻译：高密度，高速度和高可靠性的多存储非易失性存储器具有置于存储晶体管的两侧的存储晶体管和开关晶体管。存储晶体管包括具有离散陷阱和存储栅电极的栅极绝缘膜，而开关晶体管包括开关栅电极。栅极绝缘膜具有用于存储信息电荷的离散陷阱，可以局部注入载流子，并且一个存储器单元构成用于至少存储2位信息的多存储单元。具有开关栅电极的开关晶体管实现源极侧注入。存储晶体管与自对准扩散中的开关晶体管一起发生。存储晶体管的存储栅电极连接到字线，以便执行字线擦除。

7. 发明授权

US08050085B2 Semiconductor processing device and IC card 有权
标题翻译：半导体处理装置和IC卡
公开(公告)号：US08050085B2
公开(公告)日：2011-11-01
申请号：US10521553
申请日：2002-08-29
申请人： Masatoshi Takahashi , Takanori Yamazoe , Kozo Katayama , Toshihiro Tanaka , Yutaka Shinagawa , Hiroshi Watase , Takeo Kanai , Nobutaka Nagasaki
发明人： Masatoshi Takahashi , Takanori Yamazoe , Kozo Katayama , Toshihiro Tanaka , Yutaka Shinagawa , Hiroshi Watase , Takeo Kanai , Nobutaka Nagasaki
IPC分类号： G11C7/10 , G11C11/40
CPC分类号： G07F7/1008 , G06Q20/341 , G06Q20/40975 , G07F7/084 , G11C11/005 , G11C16/0425 , G11C16/0433 , G11C16/16
摘要： A semiconductor processing device according to the invention includes a first non-volatile memory (21) for erasing stored information on a first data length unit, a second non-volatile memory (22) for erasing stored information on a second data length unit, and a central processing unit (2), and capable of inputting/outputting encrypted data from/to an outside. The first non-volatile memory is used for storing an encryption key to be utilized for encrypting the data. The second non-volatile memory is used for storing a program to be processed by the central processing unit. The non-volatile memories to be utilized for storing the program and for storing the encryption key are separated from each other, and the data lengths of the erase units of information to be stored in the non-volatile memories are defined separately. Therefore, the stored information can efficiently be erased before the execution of a processing of writing the program, and the stored information can be erased corresponding to the data length of a necessary processing unit in the write of the encryption key to be utilized in the calculation processing of the CPU.
摘要翻译：根据本发明的半导体处理装置包括用于擦除第一数据长度单元上存储的信息的第一非易失性存储器（21），用于擦除第二数据长度单元上存储的信息的第二非易失性存储器（22），以及中央处理单元（2），能够从/向外部输入/输出加密数据。第一非易失性存储器用于存储要用于加密数据的加密密钥。第二非易失性存储器用于存储要由中央处理单元处理的程序。用于存储程序和用于存储加密密钥的非易失性存储器彼此分离，并且存储在非易失性存储器中的信息的擦除单元的数据长度被分开地定义。因此，在执行写入程序的处理之前可以有效地擦除存储的信息，并且可以根据在计算中要使用的加密密钥的写入中的必要处理单元的数据长度来擦除存储的信息处理CPU。

8. 发明申请

US20090213649A1 Semiconductor processing device and IC card 有权
标题翻译：半导体处理装置和IC卡
公开(公告)号：US20090213649A1
公开(公告)日：2009-08-27
申请号：US10521553
申请日：2002-08-29
申请人： Masatoshi Takahashi , Takanori Yamazoe , Kozo Katayama , Toshihiro Tanaka , Yutaka Shinagawa , Hiroshi Watase , Takeo Kanai , Nobutaka Nagasaki
发明人： Masatoshi Takahashi , Takanori Yamazoe , Kozo Katayama , Toshihiro Tanaka , Yutaka Shinagawa , Hiroshi Watase , Takeo Kanai , Nobutaka Nagasaki
IPC分类号： G11C11/34 , G11C16/04 , G11C5/14 , G06F12/14
CPC分类号： G07F7/1008 , G06Q20/341 , G06Q20/40975 , G07F7/084 , G11C11/005 , G11C16/0425 , G11C16/0433 , G11C16/16
摘要： A semiconductor processing device according to the invention includes a first non-volatile memory (21) for erasing stored information on a first data length unit, a second non-volatile memory (22) for erasing stored information on a second data length unit, and a central processing unit (2), and capable of inputting/outputting encrypted data from/to an outside. The first non-volatile memory is used for storing an encryption key to be utilized for encrypting the data. The second non-volatile memory is used for storing a program to be processed by the central processing unit. The non-volatile memories to be utilized for storing the program and for storing the encryption key are separated from each other, and the data lengths of the erase units of information to be stored in the non-volatile memories are defined separately. Therefore, the stored information can efficiently be erased before the execution of a processing of writing the program, and the stored information can be erased corresponding to the data length of a necessary processing unit in the write of the encryption key to be utilized in the calculation processing of the CPU.
摘要翻译：根据本发明的半导体处理装置包括用于擦除第一数据长度单元上存储的信息的第一非易失性存储器（21），用于擦除第二数据长度单元上存储的信息的第二非易失性存储器（22），以及中央处理单元（2），能够从/向外部输入/输出加密数据。第一非易失性存储器用于存储要用于加密数据的加密密钥。第二非易失性存储器用于存储要由中央处理单元处理的程序。用于存储程序和用于存储加密密钥的非易失性存储器彼此分离，并且存储在非易失性存储器中的信息的擦除单元的数据长度被分开地定义。因此，在执行写入程序的处理之前可以有效地擦除存储的信息，并且可以根据在计算中要使用的加密密钥的写入中的必要处理单元的数据长度来擦除存储的信息处理CPU。

9. 发明申请

US20060102967A1 Semiconductor integrated circuit 失效
公开(公告)号：US20060102967A1
公开(公告)日：2006-05-18
申请号：US11320850
申请日：2005-12-30
申请人： Yoshiaki Kamigaki , Shinichi Minami , Kozo Katayama , Masataka Kato
发明人： Yoshiaki Kamigaki , Shinichi Minami , Kozo Katayama , Masataka Kato
IPC分类号： H01L29/76
CPC分类号： G11C16/0475 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L29/42332 , H01L29/7887
摘要： A multi-storage nonvolatile memory of high density, high speed and high reliability has a memory transistor and switch transistors disposed on both the sides of the memory transistor. The memory transistor includes a gate insulating film having discrete traps and a memory gate electrode, whereas the switch transistors include switch gate electrodes. The gate insulating film has the discrete traps for storing information charge, can locally inject carriers, and one memory cell constitutes a multi-storage cell for storing at least information of 2 bits. The switch transistors having the switch gate electrodes realize source side injection. The memory transistor is fommed together with the switch transistors in self-aligned diffusion. The memory gate electrode of the memory transistor is connected to a word line so as to perform word-line erase.

10. 发明授权

US06936888B2 Nonvolatile memory device with multi-bit memory cells having plural side gates 有权
标题翻译：具有多个存储单元的非易失性存储器件具有多个侧栅极
公开(公告)号：US06936888B2
公开(公告)日：2005-08-30
申请号：US10676158
申请日：2003-10-02
申请人： Kozo Katayama , Yoshiaki Kamigaki , Shinichi Minami
发明人： Kozo Katayama , Yoshiaki Kamigaki , Shinichi Minami
IPC分类号： B42D15/10 , G06K19/07 , G06K19/077 , G11C16/02 , G11C16/04 , G11C16/06 , G11C16/10 , G11C16/14 , G11C16/26 , H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792 , H01L29/76
CPC分类号： H01L27/115 , G11C16/0475 , G11C16/10 , G11C16/14 , G11C16/26 , H01L29/7923
摘要： A nonvolatile memory device has a plurality of nonvolatile memory cells in which a memory gate electrode is formed over a first semiconductor region with a gate insulating film and a gate nitride film interposed therebetween. First and second switch gate electrodes, and first and second signal electrodes used as source/drain electrodes are formed on both sides of the memory gate electrode. Electrons are injected into the gate nitride film from the source side to store information in the memory cells. The memory gate electrode and the switch gate electrodes extend in the same direction. The application of a high electric field to a memory cell which is not selected for writing can be avoided owing to the switch gate electrodes being held in a cut-off state.
摘要翻译：非易失性存储器件具有多个非易失性存储单元，其中存储栅极电极形成在第一半导体区域上，栅极绝缘膜和栅极氮化物膜介于其间。第一和第二开关栅电极以及用作源/漏电极的第一和第二信号电极形成在存储栅电极的两侧。从源极将电子注入到栅极氮化物膜中，以将信息存储在存储单元中。存储栅电极和开关栅电极沿相同方向延伸。由于开关栅极被保持在截止状态，因此可以避免对未被选择用于写入的存储单元施加高电场。

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