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1. 发明申请

US20110235420A1 SIMULTANEOUS MULTI-STATE READ OR VERIFY IN NON-VOLATILE STORAGE 有权
标题翻译：在非易失性存储中同时进行多状态读取或验证
公开(公告)号：US20110235420A1
公开(公告)日：2011-09-29
申请号：US12732121
申请日：2010-03-25
申请人： Eran Sharon , Yan Li , Nima Mokhlesi
发明人： Eran Sharon , Yan Li , Nima Mokhlesi
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C16/3459 , G11C11/5642 , G11C16/0483 , G11C16/3454 , G11C2211/5624 , G11C2211/5631
摘要： Methods and devices for simultaneously verifying or reading multiple states in non-volatile storage are disclosed. Methods and devices for efficiently reducing or eliminating cross-coupling effects in non-volatile storage are disclosed. Methods and devices for efficiently performing reads at a number of voltages to search for the threshold voltage of a memory cell are disclosed. Memory cells on different NAND strings that are read at the same time may be tested for different threshold voltage levels. Memory cells may be tested for different threshold voltages by applying different gate-to-source voltages to memory cells being tested for different threshold voltages. Memory cells may be tested for different threshold voltages by applying different drain to source voltages to the memory cells. Different amounts of compensation for cross-coupling affects may be applied to memory cells on different NAND strings that are read or programmed at the same time.
摘要翻译：公开了用于同时验证或读取非易失性存储器中的多个状态的方法和装置。公开了用于有效地减少或消除非易失性存储器中的交叉耦合效应的方法和装置。公开了用于有效执行多个电压读取以搜索存储器单元的阈值电压的方法和装置。可以在不同的NAND串上同时读取的存储单元测试不同的阈值电压电平。可以通过对不同阈值电压进行测试的存储器单元施加不同的栅极至源极电压来对不同的阈值电压测试存储器单元。可以通过对存储器单元施加不同的漏极到源极电压来对不同的阈值电压测试存储器单元。交叉耦合影响的不同量的补偿可以应用于同时读取或编程的不同NAND串上的存储单元。

2. 发明申请

US20120250415A1 SIMULTANEOUS MULTI-STATE READ OR VERIFY IN NON-VOLATILE STORAGE 有权
标题翻译：在非易失性存储中同时进行多状态读取或验证
公开(公告)号：US20120250415A1
公开(公告)日：2012-10-04
申请号：US13491166
申请日：2012-06-07
申请人： Eran Sharon , Yan Li , Nima Mokhlesi
发明人： Eran Sharon , Yan Li , Nima Mokhlesi
IPC分类号： G11C16/04
CPC分类号： G11C16/3459 , G11C11/5642 , G11C16/0483 , G11C16/3454 , G11C2211/5624 , G11C2211/5631
摘要： Methods and devices for simultaneously verifying or reading multiple states in non-volatile storage are disclosed. Methods and devices for efficiently reducing or eliminating cross-coupling effects in non-volatile storage are disclosed. Methods and devices for efficiently performing reads at a number of voltages to search for the threshold voltage of a memory cell are disclosed. Memory cells on different NAND strings that are read at the same time may be tested for different threshold voltage levels. Memory cells may be tested for different threshold voltages by applying different gate-to-source voltages to memory cells being tested for different threshold voltages. Memory cells may be tested for different threshold voltages by applying different drain to source voltages to the memory cells. Different amounts of compensation for cross-coupling affects may be applied to memory cells on different NAND strings that are read or programmed at the same time.
摘要翻译：公开了用于同时验证或读取非易失性存储器中的多个状态的方法和装置。公开了用于有效地减少或消除非易失性存储器中的交叉耦合效应的方法和装置。公开了用于有效执行多个电压读取以搜索存储器单元的阈值电压的方法和装置。可以在不同的NAND串上同时读取的存储单元测试不同的阈值电压电平。可以通过对不同阈值电压进行测试的存储器单元施加不同的栅极至源极电压来对不同的阈值电压测试存储器单元。可以通过对存储器单元施加不同的漏极到源极电压来对不同的阈值电压测试存储器单元。交叉耦合影响的不同量的补偿可以应用于同时读取或编程的不同NAND串上的存储单元。

3. 发明授权

US08233324B2 Simultaneous multi-state read or verify in non-volatile storage 有权
标题翻译：在非易失性存储中同时进行多状态读取或验证
公开(公告)号：US08233324B2
公开(公告)日：2012-07-31
申请号：US12732121
申请日：2010-03-25
申请人： Eran Sharon , Yan Li , Nima Mokhlesi
发明人： Eran Sharon , Yan Li , Nima Mokhlesi
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C16/3459 , G11C11/5642 , G11C16/0483 , G11C16/3454 , G11C2211/5624 , G11C2211/5631
摘要： Methods and devices for simultaneously verifying or reading multiple states in non-volatile storage are disclosed. Methods and devices for efficiently reducing or eliminating cross-coupling effects in non-volatile storage are disclosed. Methods and devices for efficiently performing reads at a number of voltages to search for the threshold voltage of a memory cell are disclosed. Memory cells on different NAND strings that are read at the same time may be tested for different threshold voltage levels. Memory cells may be tested for different threshold voltages by applying different gate-to-source voltages to memory cells being tested for different threshold voltages. Memory cells may be tested for different threshold voltages by applying different drain to source voltages to the memory cells. Different amounts of compensation for cross-coupling affects may be applied to memory cells on different NAND strings that are read or programmed at the same time.
摘要翻译：公开了用于同时验证或读取非易失性存储器中的多个状态的方法和装置。公开了用于有效地减少或消除非易失性存储器中的交叉耦合效应的方法和装置。公开了用于有效执行多个电压读取以搜索存储器单元的阈值电压的方法和装置。可以在不同的NAND串上同时读取的存储单元测试不同的阈值电压电平。可以通过对不同阈值电压进行测试的存储器单元施加不同的栅极至源极电压来对不同的阈值电压测试存储器单元。可以通过对存储器单元施加不同的漏极到源极电压来对不同的阈值电压测试存储器单元。交叉耦合影响的不同量的补偿可以应用于同时读取或编程的不同NAND串上的存储单元。

4. 发明授权

US08509000B2 Simultaneous multi-state read or verify in non-volatile storage 有权
标题翻译：在非易失性存储中同时进行多状态读取或验证
公开(公告)号：US08509000B2
公开(公告)日：2013-08-13
申请号：US13491166
申请日：2012-06-07
申请人： Eran Sharon , Yan Li , Nima Mokhlesi
发明人： Eran Sharon , Yan Li , Nima Mokhlesi
IPC分类号： G11C16/04
CPC分类号： G11C16/3459 , G11C11/5642 , G11C16/0483 , G11C16/3454 , G11C2211/5624 , G11C2211/5631
摘要： Methods and devices for simultaneously verifying or reading multiple states in non-volatile storage are disclosed. Methods and devices for efficiently reducing or eliminating cross-coupling effects in non-volatile storage are disclosed. Methods and devices for efficiently performing reads at a number of voltages to search for the threshold voltage of a memory cell are disclosed. Memory cells on different NAND strings that are read at the same time may be tested for different threshold voltage levels. Memory cells may be tested for different threshold voltages by applying different gate-to-source voltages to memory cells being tested for different threshold voltages. Memory cells may be tested for different threshold voltages by applying different drain to source voltages to the memory cells. Different amounts of compensation for cross-coupling affects may be applied to memory cells on different NAND strings that are read or programmed at the same time.
摘要翻译：公开了用于同时验证或读取非易失性存储器中的多个状态的方法和装置。公开了用于有效地减少或消除非易失性存储器中的交叉耦合效应的方法和装置。公开了用于有效执行多个电压读取以搜索存储器单元的阈值电压的方法和装置。可以在不同的NAND串上同时读取的存储单元测试不同的阈值电压电平。可以通过对不同阈值电压进行测试的存储器单元施加不同的栅极至源极电压来对不同阈值电压进行存储单元的测试。可以通过对存储器单元施加不同的漏极到源极电压来对不同的阈值电压测试存储器单元。交叉耦合影响的不同量的补偿可以应用于同时读取或编程的不同NAND串上的存储单元。

5. 发明授权

US07885112B2 Nonvolatile memory and method for on-chip pseudo-randomization of data within a page and between pages 有权
标题翻译：非易失性存储器和用于片内和页之间的数据的片上伪随机化的方法
公开(公告)号：US07885112B2
公开(公告)日：2011-02-08
申请号：US11852229
申请日：2007-09-07
申请人： Yan Li , Yupin Kawing Fong , Nima Mokhlesi
发明人： Yan Li , Yupin Kawing Fong , Nima Mokhlesi
IPC分类号： G11C11/34
CPC分类号： G11C11/5628 , G11C7/1006 , G11C16/10 , G11C16/3418 , G11C16/3427 , G11C2211/5647
摘要： Features within an integrated-circuit memory chip enables scrambling or randomization of data stored in an array of nonvolatile memory cells. In one embodiment, randomization within each page helps to control source loading errors during sensing and floating gate to floating gate coupling among neighboring cells. Randomization from page to page helps to reduce program disturbs, user read disturbs, and floating gate to floating gate coupling that result from repeated and long term storage of specific data patterns. In another embodiment, randomization is implemented both within a page and between pages. The scrambling or randomization may be predetermined, or code generated pseudo randomization or user driven randomization in different embodiments. These features are accomplished within the limited resource and budget of the integrated-circuit memory chip.
摘要翻译：集成电路存储芯片内的特征使得能够对存储在非易失性存储单元阵列中的数据进行加扰或随机化。在一个实施例中，每个页面内的随机化有助于控制感测期间的源负载误差和在相邻小区之间的浮动栅极到浮动栅极耦合。从页面到页面的随机化有助于减少程序干扰，用户读取干扰以及由特定数据模式的重复和长期存储引起的浮动栅极耦合的浮动栅极。在另一个实施例中，在页面之间和页面之间实现随机化。在不同的实施例中，加扰或随机化可以是预定的，或代码生成的伪随机化或用户驱动的随机化。这些功能在集成电路存储芯片的有限资源和预算内完成。

6. 发明授权

US07606966B2 Methods in a pseudo random and command driven bit compensation for the cycling effects in flash memory 有权
标题翻译：闪存中循环效应的伪随机和命令驱动位补偿方法
公开(公告)号：US07606966B2
公开(公告)日：2009-10-20
申请号：US11530399
申请日：2006-09-08
申请人： Yan Li , Yupin Kawing Fong , Nima Mokhlesi
发明人： Yan Li , Yupin Kawing Fong , Nima Mokhlesi
IPC分类号： G06F13/10
CPC分类号： G11C7/1006 , G11C16/3418
摘要： Easily implemented randomization within a flash memory EEPROM reduces the NAND string resistance effect, program disturbs, user read disturbs, and floating gate to floating gate coupling that result from repeated and long term storage of specific data patterns. The randomization may be code generated pseudo randomization or user driven randomization in different embodiments. User driven commands, the timing of which cannot be predicted may be used to trigger and achieve a high level of randomization. Randomly altering the encoding scheme of the data prevents repeated and long term storage of specific data patterns. Even if a user wishes to store the same information for long periods, or to repeatedly store it, it will be randomly encoded with different encoding schemes, and the data pattern will therefore be varied.
摘要翻译：易于实现的闪速存储器EEPROM内的随机化可以减少由于特定数据模式的重复和长期存储而导致的NAND串电阻效应，程序干扰，用户读取干扰以及浮动栅极与浮动栅极耦合。在不同的实施例中，随机化可以是代码生成的伪随机化或用户驱动的随机化。用户驱动的命令，其定时不能预测可用于触发和实现高水平的随机化。随机改变数据的编码方案可防止特定数据模式的重复和长期存储。即使用户希望长时间存储相同的信息，也可以重复存储，将以不同的编码方式进行随机编码，因此数据模式将会变化。

7. 发明申请

US20090067244A1 NONVOLATILE MEMORY AND METHOD FOR ON-CHIP PSEUDO-RANDOMIZATION OF DATA WITHIN A PAGE AND BETWEEN PAGES 有权
标题翻译：非页面存储器和方法，用于在页面和页面之间的数据的片上PSEUDO-RANDOMIZATION
公开(公告)号：US20090067244A1
公开(公告)日：2009-03-12
申请号：US11852229
申请日：2007-09-07
申请人： Yan Li , Yupin Kawing Fong , Nima Mokhlesi
发明人： Yan Li , Yupin Kawing Fong , Nima Mokhlesi
IPC分类号： G11C16/08
CPC分类号： G11C11/5628 , G11C7/1006 , G11C16/10 , G11C16/3418 , G11C16/3427 , G11C2211/5647
摘要： Features within an integrated-circuit memory chip enables scrambling or randomization of data stored in an array of nonvolatile memory cells. In one embodiment, randomization within each page helps to control source loading errors during sensing and floating gate to floating gate coupling among neighboring cells. Randomization from page to page helps to reduce program disturbs, user read disturbs, and floating gate to floating gate coupling that result from repeated and long term storage of specific data patterns. In another embodiment, randomization is implemented both within a page and between pages. The scrambling or randomization may be predetermined, or code generated pseudo randomization or user driven randomization in different embodiments. These features are accomplished within the limited resource and budget of the integrated-circuit memory chip.
摘要翻译：集成电路存储芯片内的特征使得能够对存储在非易失性存储单元阵列中的数据进行加扰或随机化。在一个实施例中，每个页面内的随机化有助于控制感测期间的源负载误差和在相邻小区之间的浮动栅极到浮动栅极耦合。从页面到页面的随机化有助于减少程序干扰，用户读取干扰以及由特定数据模式的重复和长期存储引起的浮动栅极耦合的浮动栅极。在另一个实施例中，在页面之间和页面之间实现随机化。在不同的实施例中，加扰或随机化可以是预定的，或代码生成的伪随机化或用户驱动的随机化。这些功能在集成电路存储芯片的有限资源和预算内完成。

8. 发明授权

US07734861B2 Pseudo random and command driven bit compensation for the cycling effects in flash memory 有权
标题翻译：伪随机和命令驱动位补偿闪存中的循环效应
公开(公告)号：US07734861B2
公开(公告)日：2010-06-08
申请号：US11530392
申请日：2006-09-08
申请人： Yan Li , Yupin Kawing Fong , Nima Mokhlesi
发明人： Yan Li , Yupin Kawing Fong , Nima Mokhlesi
IPC分类号： G06F13/10
CPC分类号： G11C16/3418 , G11C7/1006 , G11C11/5621 , G11C16/0483 , G11C16/3427
摘要： Easily implemented randomization within a flash memory EEPROM reduces the NAND string resistance effect, program disturbs, user read disturbs, and floating gate to floating gate coupling that result from repeated and long term storage of specific data patterns. The randomization may be code generated pseudo randomization or user driven randomization in different embodiments. User driven commands, the timing of which cannot be predicted may be used to trigger and achieve a high level of randomization. Randomly altering the encoding scheme of the data prevents repeated and long term storage of specific data patterns. Even if a user wishes to store the same information for long periods, or to repeatedly store it, it will be randomly encoded with different encoding schemes, and the data pattern will therefore be varied.
摘要翻译：易于实现的闪速存储器EEPROM内的随机化可以减少由于特定数据模式的重复和长期存储而导致的NAND串电阻效应，程序干扰，用户读取干扰以及浮动栅极与浮动栅极耦合。在不同的实施例中，随机化可以是代码生成的伪随机化或用户驱动的随机化。用户驱动的命令，其定时不能预测可用于触发和实现高水平的随机化。随机改变数据的编码方案可防止特定数据模式的重复和长期存储。即使用户希望长时间存储相同的信息，也可以重复存储，将以不同的编码方式进行随机编码，因此数据模式将会变化。

9. 发明授权

US08885410B2 Direct multi-level cell programming 有权
标题翻译：直接多级单元编程
公开(公告)号：US08885410B2
公开(公告)日：2014-11-11
申请号：US13598264
申请日：2012-08-29
申请人： Alon Marcu , Eran Sharon , Idan Alrod , Yan Li , Hadas Oshinsky
发明人： Alon Marcu , Eran Sharon , Idan Alrod , Yan Li , Hadas Oshinsky
IPC分类号： G11C16/04 , G11C16/26
CPC分类号： G11C16/10 , G06F12/0246 , G06F2212/7203 , G11C11/5628 , G11C16/0483 , G11C16/26 , G11C2211/5641 , G11C2211/5643
摘要： A method is performed in a data storage device that includes a controller coupled to a non-volatile memory. The non-volatile memory includes a group of storage elements. Each storage element is configured to store multiple data bits. Data is sent from the controller to the non-volatile memory and first bits corresponding to a first portion of the data are stored into the group of storage elements during a first write stage. Each storage element of the group of storage elements stores at least one bit of the first bits upon completion of the first write stage. Second bits corresponding to a second portion of the data are sent to a second memory without sending the first bits to the second memory. The second bits are retrieved from the second memory and at least the second bits are stored into the group of storage elements during a second write stage.
摘要翻译：在包括耦合到非易失性存储器的控制器的数据存储设备中执行方法。非易失性存储器包括一组存储元件。每个存储元件被配置为存储多个数据位。数据从控制器发送到非易失性存储器，并且对应于数据的第一部分的第一位在第一写入阶段被存储到存储元件组中。存储元件组中的每个存储元件在第一写入阶段完成时存储第一位的至少一个位。对应于数据的第二部分的第二位被发送到第二存储器，而不将第一位发送到第二存储器。从第二存储器检索第二位，并且在第二写入阶段期间至少将第二位存储到存储元件组中。

10. 发明授权

US08750042B2 Combined simultaneous sensing of multiple wordlines in a post-write read (PWR) and detection of NAND failures 有权
标题翻译：在写入后读取（PWR）和NAND故障检测中组合同时检测多个字线
公开(公告)号：US08750042B2
公开(公告)日：2014-06-10
申请号：US13332780
申请日：2011-12-21
申请人： Eran Sharon , Yan Li , Dana Lee , Idan Alrod
发明人： Eran Sharon , Yan Li , Dana Lee , Idan Alrod
IPC分类号： G11C29/04
CPC分类号： G11C29/04 , G11C11/5642 , G11C16/3459 , G11C29/50004 , G11C2211/5641
摘要： Techniques for a post-write read are presented. In an exemplary embodiment, a combined simultaneous sensing of multiple word lines is used in order to identify a problem in one or more of these word lines. That is, sensing voltages are concurrently applied to the control gates of more than one memory cell whose resultant conductance is measured on the same bit line. The combined sensing result is use for measuring certain statistics of the cell voltage distribution (CVD) of multiple word lines and comparing it to the expected value. In case the measured statistics are different than expected, this may indicate that one or more of the sensed word lines may exhibit a failure and more thorough examination of the group of word lines can be performed.
摘要翻译：介绍了写入后读取技术。在示例性实施例中，使用多个字线的组合同时感测以便识别这些字线中的一个或多个中的问题。也就是说，感测电压同时施加到多个存储单元的控制栅极，其结果电导在同一位线上被测量。组合的感测结果用于测量多个字线的单元电压分布（CVD）的某些统计量并将其与预期值进行比较。在测量的统计量与预期不同的情况下，这可以指示感测字线中的一个或多个可能表现出故障，并且可以执行对该组字线的更彻底的检查。

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