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1. 发明申请

US20140029362A1 MECHANISMS FOR BULIT-IN SELF TEST AND REPAIR FOR MEMORY DEVICES 有权
标题翻译：用于自动测试和修理内存设备的机制
公开(公告)号：US20140029362A1
公开(公告)日：2014-01-30
申请号：US13560571
申请日：2012-07-27
申请人： Saman ADHAM , Chao-Jung HUNG
发明人： Saman ADHAM , Chao-Jung HUNG
IPC分类号： G11C29/04
CPC分类号： G11C29/4401 , G11C17/146 , G11C17/16 , G11C29/785 , G11C2029/4402
摘要： This description relates to a system for storing repair data of a random access memory (RAM) array in a one-time programming memory (OTPM). The system includes the RAM array, wherein the RAM array includes a main memory, redundant rows and columns, and a first repair register memory. The system further includes a built-in self-test-and-repair (BISTR) module having a second repair register memory, wherein the BISTR module is used to test and repair the RAM array. The system further includes the one-time programming memory (OTPM) for storing repair data from more than one test and repair stages for the RAM array, wherein the repair data from different test and repair stages are stored in a same data segment.
摘要翻译：该描述涉及用于存储随机存取存储器（RAM）阵列在一次性编程存储器（OTPM）中的修复数据的系统。该系统包括RAM阵列，其中RAM阵列包括主存储器，冗余行和列以及第一修复寄存器存储器。该系统还包括具有第二修复寄存器存储器的内置自检和修复（BISTR）模块，其中BISTR模块用于测试和修复RAM阵列。该系统还包括用于存储来自RAM阵列的多于一个测试和修复阶段的修复数据的一次性编程存储器（OTPM），其中来自不同测试和修复阶段的修复数据被存储在相同的数据段中。

2. 发明授权

US08942051B2 Mechanisms for built-in self test and repair for memory devices 有权
标题翻译：用于内存自检和修复内存设备的机制
公开(公告)号：US08942051B2
公开(公告)日：2015-01-27
申请号：US13560571
申请日：2012-07-27
申请人： Saman Adham , Chao-Jung Hung
发明人： Saman Adham , Chao-Jung Hung
IPC分类号： G11C29/00
CPC分类号： G11C29/4401 , G11C17/146 , G11C17/16 , G11C29/785 , G11C2029/4402
摘要： This description relates to a system for storing repair data of a random access memory (RAM) array in a one-time programming memory (OTPM). The system includes the RAM array, wherein the RAM array includes a main memory, redundant rows and columns, and a first repair register memory. The system further includes a built-in self-test-and-repair (BISTR) module having a second repair register memory, wherein the BISTR module is used to test and repair the RAM array. The system further includes the one-time programming memory (OTPM) for storing repair data from more than one test and repair stages for the RAM array, wherein the repair data from different test and repair stages are stored in a same data segment.
摘要翻译：该描述涉及用于存储随机存取存储器（RAM）阵列在一次性编程存储器（OTPM）中的修复数据的系统。该系统包括RAM阵列，其中RAM阵列包括主存储器，冗余行和列以及第一修复寄存器存储器。该系统还包括具有第二修复寄存器存储器的内置自检和修复（BISTR）模块，其中BISTR模块用于测试和修复RAM阵列。该系统还包括用于存储来自RAM阵列的多于一个测试和修复阶段的修复数据的一次性编程存储器（OTPM），其中来自不同测试和修复阶段的修复数据被存储在相同的数据段中。

3. 发明授权

US5313469A Self-testable digital integrator 失效
标题翻译：自检数字集成商
公开(公告)号：US5313469A
公开(公告)日：1994-05-17
申请号：US75629
申请日：1993-06-11
申请人： Saman Adham , Janusz Rajski , Jerzy Tyszer , Mark Kassab
发明人： Saman Adham , Janusz Rajski , Jerzy Tyszer , Mark Kassab
IPC分类号： G01R31/3183 , G01R31/28
CPC分类号： G01R31/318321
摘要： A self-testable digital integrator comprises binary adding apparatus and storage apparatus. The adding apparatus and the storage apparatus are functionally interconnected such that the storage apparatus feeds digital words to the adding apparatus for addition thereof and the adding apparatus feeds resulting digital words to the storage apparatus for storage thereof to perform a digital integration operation. The digital integrator further comprises a first combinational network responsive to a first state of a test mode signal to feed an external input signal to the adding apparatus for integration thereof, and responsive to a second state of the test mode signal to feed to the adding apparatus a test pattern signal derived from selected bias of the digital words fed from the adding apparatus to the storage apparatus. The digital integrator also comprises a second combinational network responsive to the second state of the test mode signal to feed back a carry-out bit of the adding apparatus to a carry-in port of the adding apparatus for test result compaction. The digital integrator optionally comprises a third combinational network responsive to the second state of the test mode signal to feed a carry-out bit of the adding apparatus to the first combinational network, the first combinational network being responsive to the second state of the test mode signal and to the carry-out bit to modify the test pattern signal. The self-testable digital integrator is particularly useful as a component of a digital decimator used to decimate Double Integration Sigma Delta modulation signals.
摘要翻译：一种可自检的数字积分器包括二进制加法装置和存储装置。所述添加装置和所述存储装置在功能上互连，使得所述存储装置将数字字馈送到所述添加装置以添加，并且所述添加装置将所生成的数字字馈送到所述存储装置以进行存储以进行数字集成操作。数字积分器还包括响应于测试模式信号的第一状态的第一组合网络，以将外部输入信号馈送到加法装置以进行积分，并响应于测试模式信号的第二状态馈送到添加装置从从加法装置馈送到存储装置的数字字的选定偏置导出的测试图案信号。数字积分器还包括响应于测试模式信号的第二状态的第二组合网络，以将加法装置的进位位反馈到用于测试结果压缩的加法装置的进位端口。数字积分器可选地包括响应于测试模式信号的第二状态的第三组合网络，以将加法装置的进位位馈送到第一组合网络，第一组合网络响应于测试模式的第二状态信号和进位位修改测试码信号。自检数字积分器作为用于抽取双积分Sigma Delta调制信号的数字抽取器的组件特别有用。

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