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1. 发明授权

US09147495B2 Two-bit read-only memory cell 有权
标题翻译：两位只读存储单元
公开(公告)号：US09147495B2
公开(公告)日：2015-09-29
申请号：US13778258
申请日：2013-02-27
申请人： LSI Corporation
发明人： Rajiv Kumar Roy , Vikash
IPC分类号： G11C11/4097 , G11C17/14 , G11C11/56
CPC分类号： G11C17/146 , G11C11/4097 , G11C11/5692
摘要： A read-only memory (ROM) cell has first and second transistors connected in series between a true bit line and a voltage reference (e.g., ground), and third and fourth transistors connected in series between a complement bit line and the voltage reference. The gates of the first and third transistors are connected to a first word line, and the gates of the second and fourth transistors are connected to a second word line. The ROM cell is programmed to store any possible combination of two bits of information by appropriately (i) connecting the node between the first and second transistors to either the true bit line, the complement bit line, or the voltage reference and (ii) connecting the node between the third and fourth transistors to either the true bit line, the complement bit line, or the voltage reference.
摘要翻译：只读存储器（ROM）单元具有串联在真位线和电压基准（例如，接地）之间的第一和第二晶体管，以及串联连接在补码位线和电压基准之间的第三和第四晶体管。第一和第三晶体管的栅极连接到第一字线，第二和第四晶体管的栅极连接到第二字线。 ROM单元被编程为通过适当地（i）将第一和第二晶体管之间的节点连接到真位线，补码位线或电压基准来存储两位信息的任何可能的组合，以及（ii）连接第三和第四晶体管之间的节点到真位线，补码位线或电压基准。

2. 发明申请

US20140241028A1 TWO-BIT READ-ONLY MEMORY CELL 有权
标题翻译：两位只读存储器单元
公开(公告)号：US20140241028A1
公开(公告)日：2014-08-28
申请号：US13778258
申请日：2013-02-27
申请人： LSI CORPORATION
发明人： Rajiv Kumar Roy , Vikash
IPC分类号： G11C5/06
CPC分类号： G11C17/146 , G11C11/4097 , G11C11/5692
摘要： A read-only memory (ROM) cell has first and second transistors connected in series between a true bit line and a voltage reference (e.g., ground), and third and fourth transistors connected in series between a complement bit line and the voltage reference. The gates of the first and third transistors are connected to a first word line, and the gates of the second and fourth transistors are connected to a second word line. The ROM cell is programmed to store any possible combination of two bits of information by appropriately (i) connecting the node between the first and second transistors to either the true bit line, the complement bit line, or the voltage reference and (ii) connecting the node between the third and fourth transistors to either the true bit line, the complement bit line, or the voltage reference.
摘要翻译：只读存储器（ROM）单元具有串联在真位线和电压基准（例如，接地）之间的第一和第二晶体管，以及串联连接在补码位线和电压基准之间的第三和第四晶体管。第一和第三晶体管的栅极连接到第一字线，第二和第四晶体管的栅极连接到第二字线。 ROM单元被编程为通过适当地（i）将第一和第二晶体管之间的节点连接到真位线，补码位线或电压基准来存储两位信息的任何可能的组合，以及（ii）连接第三和第四晶体管之间的节点到真位线，补码位线或电压基准。

3. 发明授权

US08879303B2 Pre-charge tracking of global read lines in high speed SRAM 有权
标题翻译：高速SRAM中全局读取线的预充电跟踪
公开(公告)号：US08879303B2
公开(公告)日：2014-11-04
申请号：US13733578
申请日：2013-01-03
申请人： LSI Corporation
发明人： Kamal Chandwani , Vikash , Rahul Sahu
IPC分类号： G11C11/00 , G11C7/00 , G11C7/02 , G11C8/00 , G11C7/12 , G11C11/419
CPC分类号： G11C7/12 , G11C7/08 , G11C7/227 , G11C11/419
摘要： In embodiments of the invention, a memory circuit includes a static random access memory (SRAM), rows of M sense amplifiers, a global read precharge tracking control circuit controlling a precharge of global read lines, a sense amplifier output tracking circuit generating a reset sense amplifier signal for the sense amplifier control circuits, and a read delay circuit generating a trigger signal for the global read precharge tracking control circuit and the sense amplifier output tracking circuit and performing a fixed delay tracking of a read operation in a read cycle. A dummy global read line is coupled to the global read precharge tracking control circuit and returns from a half way to the top of the SRAM forming a tracking dummy global read line that determines a completion of the precharge of the global read lines before the sense amplifiers start discharging the global read lines in the read cycle.
摘要翻译：在本发明的实施例中，存储器电路包括静态随机存取存储器（SRAM），M个读出放大器行，控制全局读取线的预充电的全局读取预充电跟踪控制电路，产生复位感测的读出放大器输出跟踪电路用于读出放大器控制电路的放大器信号，以及产生用于全局读取预充电跟踪控制电路和读出放大器输出跟踪电路的触发信号的读延迟电路，并且在读周期中执行读操作的固定延迟跟踪。虚拟全局读取线耦合到全局读取预充电跟踪控制电路，并从半路返回到SRAM的顶部，形成跟踪虚拟全局读取线，其确定读出放大器之前的全局读取线的预充电完成开始读取读取周期中的全局读取行。

4. 发明申请

US20140204660A1 MEMORY HAVING SENSE AMPLIFIER FOR OUTPUT TRACKING BY CONTROLLED FEEDBACK LATCH 有权
标题翻译：具有感应放大器的存储器，用于通过控制反馈锁存器进行输出跟踪
公开(公告)号：US20140204660A1
公开(公告)日：2014-07-24
申请号：US13747814
申请日：2013-01-23
申请人： LSI CORPORATION
发明人： Kamal Chandwani , Rahul Sahu , Vikash
IPC分类号： G11C11/419
CPC分类号： G11C11/412 , G11C7/06 , G11C7/08 , G11C7/14 , G11C11/407 , G11C11/409 , G11C11/413 , G11C11/419
摘要： In described embodiments, a memory circuit includes a static random access memory (SRAM) including N banks of memory cells, rows of M sense amplifiers, a controlled feedback latch storing a previous state of input data in a read cycle, a pull down select block coupled to the controlled feedback latch and the dummy sense amplifier, a dummy output latch coupled to the pull-down select block to store the read data, and a SRAM reset generation circuit coupled to the sense amplifier control circuits and the controlled feedback latch. The dummy output latch is a latch that is the same as a sense amplifier latch used in the local input/output circuit, thereby, no margin is involved between a reset of the sense amplifiers and the read data latched at the dummy output latch in the read cycle.
摘要翻译：在所描述的实施例中，存储器电路包括包括N组存储单元的静态随机存取存储器（SRAM），M个读出放大器行，在读周期中存储输入数据的先前状态的受控反馈锁存器，下拉选择块耦合到受控反馈锁存器和虚拟读出放大器，耦合到下拉选择块以存储读取数据的虚拟输出锁存器，以及耦合到读出放大器控制电路和受控反馈锁存器的SRAM复位产生电路。虚拟输出锁存器是与在本地输入/输出电路中使用的读出放大器锁存器相同的锁存器，因此，在读出放大器的复位和在虚拟输出锁存器中锁存的读取数据之间不存在余量阅读周期。

5. 发明申请

US20140185366A1 PRE-CHARGE TRACKING OF GLOBAL READ LINES IN HIGH SPEED SRAM 有权
标题翻译：高速SRAM中全局读取线的预充电跟踪
公开(公告)号：US20140185366A1
公开(公告)日：2014-07-03
申请号：US13733578
申请日：2013-01-03
申请人： LSI CORPORATION
发明人： Kamal Chandwani , Vikash , Rahul Sahu
IPC分类号： G11C7/12 , G11C11/419
CPC分类号： G11C7/12 , G11C7/08 , G11C7/227 , G11C11/419
摘要： In embodiments of the invention, a memory circuit includes a static random access memory (SRAM), rows of M sense amplifiers, a global read precharge tracking control circuit controlling a precharge of global read lines, a sense amplifier output tracking circuit generating a reset sense amplifier signal for the sense amplifier control circuits, and a read delay circuit generating a trigger signal for the global read precharge tracking control circuit and the sense amplifier output tracking circuit and performing a fixed delay tracking of a read operation in a read cycle. A dummy global read line is coupled to the global read precharge tracking control circuit and returns from a half way to the top of the SRAM forming a tracking dummy global read line that determines a completion of the precharge of the global read lines before the sense amplifiers start discharging the global read lines in the read cycle.
摘要翻译：在本发明的实施例中，存储器电路包括静态随机存取存储器（SRAM），M个读出放大器行，控制全局读取线的预充电的全局读取预充电跟踪控制电路，产生复位感测的读出放大器输出跟踪电路用于读出放大器控制电路的放大器信号，以及产生用于全局读取预充电跟踪控制电路和读出放大器输出跟踪电路的触发信号的读延迟电路，并且在读周期中执行读操作的固定延迟跟踪。虚拟全局读取线耦合到全局读取预充电跟踪控制电路，并从半路返回到SRAM的顶部，形成跟踪虚拟全局读取线，其确定读出放大器之前的全局读取线的预充电完成开始读取读取周期中的全局读取行。

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