专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US09472255B2 Semiconductor device including a clock generating circuit for generating an internal signal having a coarse delay line, a fine delay line and a selector circuit 有权
标题翻译：半导体器件包括用于产生具有粗延迟线的内部信号的时钟发生电路，精细延迟线和选择器电路
公开(公告)号：US09472255B2
公开(公告)日：2016-10-18
申请号：US14193345
申请日：2014-02-28
申请人： PS4 LUXCO S.A.R.L.
发明人： Katsuhiro Kitagawa
IPC分类号： G06F1/00 , G11C7/22 , G11C5/06 , G11C7/10 , H03L7/081 , H03L7/087
CPC分类号： G11C7/222 , G11C5/063 , G11C7/1051 , G11C7/1057 , G11C7/1066 , G11C7/22 , G11C2207/2254 , H03L7/0814 , H03L7/0818 , H03L7/087
摘要： A semiconductor device includes a data input/output circuit that has an ODT function and a DLL circuit that generates an internal clock for determining an operation timing of the data input/output circuit. The DLL circuit has a first mode for controlling a phase of the internal clock in a precise manner and a second mode for operating with low power consumption. When the data input/output circuit does not perform an ODT operation, the DLL circuit operates in the first mode, and when the data input/output circuit performs the ODT operation, the DLL circuit operates in the second mode. In this manner, the operation mode of the DLL circuit is switched over depending on the ODT operation, so that the power consumption in the ODT operation in which strict phase control is not required can be reduced.
摘要翻译：半导体器件包括具有ODT功能的数据输入/输出电路和产生用于确定数据输入/输出电路的操作定时的内部时钟的DLL电路。 DLL电路具有用于以精确的方式控制内部时钟的相位的第一模式和用于以低功耗操作的第二模式。当数据输入/输出电路不执行ODT操作时，DLL电路以第一模式工作，并且当数据输入/输出电路执行ODT操作时，DLL电路以第二模式工作。以这种方式，根据ODT操作来切换DLL电路的操作模式，从而可以减少不需要严格相位控制的ODT操作中的功耗。

2. 发明授权

US09467142B2 Semiconductor device with buffer and replica circuits 有权
标题翻译：具有缓冲器和复制电路的半导体器件
公开(公告)号：US09467142B2
公开(公告)日：2016-10-11
申请号：US14662962
申请日：2015-03-19
申请人： PS4 LUXCO S.A.R.L.
发明人： Toru Hatakeyama , Toru Ishikawa
IPC分类号： H03K19/0175 , H03K19/00 , G11C5/06 , G11C7/10
CPC分类号： H03K19/0027 , G11C5/06 , G11C7/1087
摘要： A semiconductor device, includes an input buffer, first and second PMOS transistors serially interconnected between a first power supply node and an output node of the input buffer. First and second NMOS transistors are serially interconnected between a second power supply node and the output node of the input buffer. A replica circuit includes a third and fourth PMOS transistors serially interconnected between the first power supply node and an output node of the replica circuit. Third and fourth NMOS transistors are serially interconnected between the second power supply node and the output node of the replica circuit. The input node of the replica circuit is connected to the output node of the replica circuit and a comparison circuit compares a voltage at the output node of the replica circuit to a reference voltage.
摘要翻译：半导体器件包括输入缓冲器，在第一电源节点和输入缓冲器的输出节点之间串联互连的第一和第二PMOS晶体管。第一和第二NMOS晶体管在第二电源节点和输入缓冲器的输出节点之间串联连接。复制电路包括在第一电源节点和复制电路的输出节点之间串联互连的第三和第四PMOS晶体管。第三和第四NMOS晶体管在第二电源节点和复制电路的输出节点之间串联连接。复制电路的输入节点连接到复制电路的输出节点，比较电路将复制电路输出节点的电压与参考电压进行比较。

3. 发明授权

US09455019B2 Semiconductor device having CAL latency function 有权
标题翻译：具有CAL延迟功能的半导体器件
公开(公告)号：US09455019B2
公开(公告)日：2016-09-27
申请号：US14733924
申请日：2015-06-08
申请人： PS4 Luxco S.a.r.l.
发明人： Chikara Kondo
IPC分类号： G11C8/00 , G11C11/4076 , G11C7/10 , G11C7/22 , G11C8/18 , G11C11/408
CPC分类号： G11C11/4076 , G11C7/1039 , G11C7/22 , G11C8/18 , G11C11/408 , G11C11/4085 , G11C11/4087 , G11C11/4091 , G11C11/4093 , G11C11/4096
摘要： One semiconductor device includes a command receiver receiving the command signal to generate a first internal command signal, and a latency control circuit activating a second internal chip select signal after elapse of first cycles of a clock signal since a first internal chip select signal is activated. The latency control circuit activates a second control signal when the chip select signal is maintained in an inactive state during second cycles of the clock signal that is larger than the first cycles. The command receiver is activated based on a first control signal. The first control signal is activated in response to the first internal chip select signal. The first control signal is deactivated in response to the second control signal.
摘要翻译：一个半导体器件包括接收命令信号以产生第一内部命令信号的命令接收器，以及等待时间控制电路，其在第一内部片选信号被激活之后经过时钟信号的第一周期之后激活第二内部片选信号。当时钟信号的大于第一周期的第二周期期间，当芯片选择信号保持在非活动状态时，等待时间控制电路激活第二控制信号。基于第一控制信号激活命令接收器。第一控制信号响应于第一内部芯片选择信号被激活。第一控制信号响应于第二控制信号被去激活。

4. 发明授权

US09449951B2 Semiconductor device 有权
公开(公告)号：US09449951B2
公开(公告)日：2016-09-20
申请号：US14567580
申请日：2014-12-11
申请人： PS4 Luxco S.a.r.l.
发明人： Yukitoshi Hirose , Yushi Inoue , Shiro Harashima , Takuya Moriya , Chihoko Yokobe
IPC分类号： H01L23/495 , H01L25/065 , H01L23/488 , H01L23/498 , H01L21/56 , H01L25/10 , H01L23/00 , H01L23/538 , H01L23/552 , H01L23/31
CPC分类号： H01L25/0657 , H01L21/561 , H01L23/3128 , H01L23/488 , H01L23/49816 , H01L23/49838 , H01L23/5384 , H01L23/552 , H01L24/16 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/97 , H01L25/105 , H01L2224/05553 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/48228 , H01L2224/48465 , H01L2224/49171 , H01L2224/73204 , H01L2224/73265 , H01L2224/85203 , H01L2224/85205 , H01L2224/97 , H01L2225/0651 , H01L2225/0652 , H01L2225/06524 , H01L2225/06548 , H01L2225/06562 , H01L2225/1023 , H01L2225/1058 , H01L2924/10161 , H01L2924/12041 , H01L2924/15173 , H01L2924/15182 , H01L2924/15183 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/30107 , H01L2924/3025 , H01L2924/00012 , H01L2224/85 , H01L2224/83 , H01L2924/00 , H01L2224/48247 , H01L2924/00014 , H01L2224/92247
摘要： A semiconductor device includes an insulating substrate including a first surface and an opposing second surface, and a semiconductor chip. The semiconductor chip is mounted over the first surface, includes signal electrodes, power-supply electrodes and ground electrodes, which connect to pads on the first surface of the insulating substrate. Lands provided on the second surface of the insulating substrate include signal lands, power-supply lands and ground lands through vias penetrate from the first surface to the second surface of the insulating substrate, and include signal vias electrically connected the signal connection pads to the signal lands, power-supply vias electrically connected the power-supply connection pads to the power-supply lands and ground vias electrically connected the ground connection pads to the ground lands. At least one of the signal vias are closer to the connection pads than immediately adjacent one of the power-supply vias or the ground vias.

5. 再颁专利

USRE46141E1 Semiconductor device and timing control method for the same 有权
标题翻译：半导体器件及其时序控制方法相同
公开(公告)号：USRE46141E1
公开(公告)日：2016-09-06
申请号：US14207015
申请日：2014-03-12
申请人： PS4 Luxco S.a.r.l.
发明人： Hideyuki Yoko , Ryuuji Takishita
IPC分类号： G05F1/10 , G05F3/02 , G11C11/4074 , G11C11/4076 , H03K3/356 , H03K3/012
CPC分类号： H03K3/012 , G11C11/4074 , G11C11/4076 , G11C2207/2227 , H03K3/356113
摘要： A semiconductor device includes a power-supply control portion and a latch portion. The power-supply control portion supplies power to an internal circuit in response to an input signal synchronized with rising of clock. The latch portion latches the input signal in synchronization with falling of the clock and supplies the latched input signal to the internal circuit.
摘要翻译：半导体器件包括电源控制部分和闩锁部分。电源控制部分响应于与时钟的上升同步的输入信号向内部电路供电。锁存部分与时钟的下降同步地锁存输入信号，并将锁存的输入信号提供给内部电路。

6. 发明授权

US09385130B2 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US09385130B2
公开(公告)日：2016-07-05
申请号：US13357764
申请日：2012-01-25
申请人： Yoichi Fukushima
发明人： Yoichi Fukushima
IPC分类号： H01L27/108 , H01L21/768
CPC分类号： H01L27/10855 , H01L21/76847 , H01L21/76855 , H01L21/76897 , H01L27/10814 , H01L27/10894
摘要： In order to achieve the reduction of contact resistance by forming a metal silicide layer with a sufficient thickness in an interface between a polycrystalline silicon plug and an upper conductive plug, the polycrystalline silicon plug contains germanium, which is ion-implanted before forming the metal silicide layer.
摘要翻译：为了通过在多晶硅塞和上导电塞之间的界面形成足够厚度的金属硅化物层来实现接触电阻的降低，多晶硅塞包含锗，其在形成金属硅化物之前被离子注入层。

7. 发明授权

US09368189B2 Semiconductor device including output circuit constituted of plural unit buffer circuits in which impedance thereof are adjustable 有权
标题翻译：包括由其阻抗可调的多个单位缓冲电路构成的输出电路的半导体装置
公开(公告)号：US09368189B2
公开(公告)日：2016-06-14
申请号：US14295213
申请日：2014-06-03
申请人： PS4 Luxco S.a.r.l.
发明人： Hideyuki Yokou , Koji Uemura , Manabu Ishimatsu
IPC分类号： H03K19/003 , G11C11/4076 , H03K17/16 , H03K19/00 , G11C11/4093 , G11C5/14 , G11C29/02 , H03K19/0185
CPC分类号： G11C11/4076 , G11C5/147 , G11C11/4093 , G11C29/022 , G11C29/028 , G11C2207/2254 , H03K17/167 , H03K19/0005 , H03K19/018571
摘要： A semiconductor device includes an output circuit having a plurality of unit buffer circuits, an impedance of each unit buffer circuit of the plurality of unit buffer circuits being adjustable, a control circuit configured to selectively activate one or more unit buffer circuits of the plurality of unit buffer circuits, and an impedance adjustment unit configured to adjust the impedance of each of the unit buffer circuits of the plurality of unit buffer circuits. The impedance adjustment unit includes a first power line, a replica circuit, and a load current generation circuit. The replica circuit and the load current generation circuit are coupled in common to the first power line, the replica circuit has a replica impedance that is substantially equal to the impedance of the output circuit, and the load current generation circuit changes current flowing therethrough.
摘要翻译：半导体器件包括具有多个单元缓冲电路的输出电路，多个单元缓冲电路中的每个单元缓冲电路的阻抗是可调节的，控制电路被配置为选择性地激活多个单元中的一个或多个单元缓冲电路缓冲电路和阻抗调整单元，被配置为调整多个单元缓冲电路中的每个单元缓冲电路的阻抗。阻抗调整单元包括第一电力线，复制电路和负载电流产生电路。复制电路和负载电流产生电路共同耦合到第一电力线，复制电路具有基本上等于输出电路的阻抗的复制阻抗，并且负载电流产生电路改变流过其中的电流。

8. 发明授权

US09368174B2 Data strobe control device 有权
标题翻译：数据选通控制装置
公开(公告)号：US09368174B2
公开(公告)日：2016-06-14
申请号：US13868463
申请日：2013-04-23
申请人： PS4 Luxco S.a.r.l.
发明人： Yoji Nishio
IPC分类号： G11C7/10 , G11C8/18 , G11C7/22 , G11C11/4076 , G11C11/4093 , G11C29/02
CPC分类号： G11C8/18 , G11C7/10 , G11C7/1087 , G11C7/1093 , G11C7/222 , G11C11/4076 , G11C11/4093 , G11C29/022 , G11C29/023 , G11C29/028
摘要： A control device that comprises a first data strobe input terminal to be connected in common to data strobe terminals that are included respectively in first memory devices, and a plurality of first sub-units each coupled to the first data strobe input terminal and each holding a data strobe delay value corresponding to an associated one of the first memory devices, and the data strobe delay values of the sub-units being independent from each other.
摘要翻译：一种控制装置，包括：第一数据选通输入端子，其共同连接到分别包括在第一存储器件中的数据选通端子;以及多个第一子单元，每个第一子单元分别耦合到第一数据选通输入端子，数据选通延迟值对应于相关联的第一存储器件之一，并且子单元的数据选通延迟值彼此独立。

9. 发明授权

US09337139B2 Semiconductor device having compensation capacitor to stabilize power supply voltage 有权
标题翻译：具有补偿电容器以稳定电源电压的半导体器件
公开(公告)号：US09337139B2
公开(公告)日：2016-05-10
申请号：US13800978
申请日：2013-03-13
申请人： PS4 Luxco S.a.r.l.
发明人： Tomohiro Kitano , Hisayuki Nagamine
IPC分类号： H01L23/522 , G11C5/14 , G11C5/04 , G11C5/06 , H01L23/48 , H01L23/31 , H01L25/065
CPC分类号： H01L23/5223 , G11C5/04 , G11C5/06 , G11C5/14 , H01L23/3128 , H01L23/481 , H01L25/0657 , H01L2224/14181 , H01L2224/16145 , H01L2224/16225 , H01L2924/13091 , H01L2924/15311 , H01L2924/00
摘要： Disclosed herein is a device that includes: first and second memory cell arrays arranged in a first direction; a plurality of first bump electrodes disposed between the first and second memory cell arrays and arranged in line in a second direction crossing the first direction; a plurality of second bump electrodes disposed between the first bump electrodes and the second memory cell arrays and arranged in line in the second direction; a first area being between the first and second bump electrodes; a plurality of third bump electrodes disposed in the first area; and a first capacitor formed in the third area.
摘要翻译：本文公开了一种装置，其包括：沿第一方向排列的第一和第二存储单元阵列; 多个第一凸起电极，设置在第一和第二存储单元阵列之间并且沿与第一方向交叉的第二方向成直线排列; 多个第二凸起电极，设置在所述第一凸块电极和所述第二存储单元阵列之间并且沿所述第二方向排成一列; 第一区域，位于第一和第二凸块电极之间; 设置在所述第一区域中的多个第三凸起电极; 以及形成在第三区域中的第一电容器。

10. 发明授权

US09330978B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US09330978B2
公开(公告)日：2016-05-03
申请号：US13253390
申请日：2011-10-05
申请人： Koji Taniguchi
发明人： Koji Taniguchi
IPC分类号： H01L29/78 , H01L27/06 , H01L21/8234 , H01L21/762 , H01L27/108 , H01L29/10
CPC分类号： H01L21/823437 , H01L21/76232 , H01L27/10814 , H01L27/10876 , H01L29/1083 , H01L29/7813
摘要： A semiconductor device includes a semiconductor substrate, a gate electrode, a dummy gate electrode, and a first impurity diffusion region. The semiconductor substrate has first and second grooves. The gate electrode is in the first groove. The dummy gate electrode is in the second groove. The dummy gate electrode has a first top surface. The first impurity diffusion region in the semiconductor substrate is positioned between the first and second grooves. The first top surface is positioned at a lower level than a bottom of the first impurity diffusion region.
摘要翻译：半导体器件包括半导体衬底，栅电极，虚拟栅极电极和第一杂质扩散区域。半导体衬底具有第一和第二沟槽。栅电极位于第一槽中。虚拟栅电极在第二槽中。虚拟栅电极具有第一顶表面。半导体衬底中的第一杂质扩散区域位于第一和第二沟槽之间。第一顶表面位于比第一杂质扩散区的底部更低的水平。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式