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1. 发明授权

US09472255B2 Semiconductor device including a clock generating circuit for generating an internal signal having a coarse delay line, a fine delay line and a selector circuit 有权
标题翻译：半导体器件包括用于产生具有粗延迟线的内部信号的时钟发生电路，精细延迟线和选择器电路
公开(公告)号：US09472255B2
公开(公告)日：2016-10-18
申请号：US14193345
申请日：2014-02-28
申请人： PS4 LUXCO S.A.R.L.
发明人： Katsuhiro Kitagawa
IPC分类号： G06F1/00 , G11C7/22 , G11C5/06 , G11C7/10 , H03L7/081 , H03L7/087
CPC分类号： G11C7/222 , G11C5/063 , G11C7/1051 , G11C7/1057 , G11C7/1066 , G11C7/22 , G11C2207/2254 , H03L7/0814 , H03L7/0818 , H03L7/087
摘要： A semiconductor device includes a data input/output circuit that has an ODT function and a DLL circuit that generates an internal clock for determining an operation timing of the data input/output circuit. The DLL circuit has a first mode for controlling a phase of the internal clock in a precise manner and a second mode for operating with low power consumption. When the data input/output circuit does not perform an ODT operation, the DLL circuit operates in the first mode, and when the data input/output circuit performs the ODT operation, the DLL circuit operates in the second mode. In this manner, the operation mode of the DLL circuit is switched over depending on the ODT operation, so that the power consumption in the ODT operation in which strict phase control is not required can be reduced.
摘要翻译：半导体器件包括具有ODT功能的数据输入/输出电路和产生用于确定数据输入/输出电路的操作定时的内部时钟的DLL电路。 DLL电路具有用于以精确的方式控制内部时钟的相位的第一模式和用于以低功耗操作的第二模式。当数据输入/输出电路不执行ODT操作时，DLL电路以第一模式工作，并且当数据输入/输出电路执行ODT操作时，DLL电路以第二模式工作。以这种方式，根据ODT操作来切换DLL电路的操作模式，从而可以减少不需要严格相位控制的ODT操作中的功耗。

2. 发明授权

US08917127B2 Semiconductor device having delay line 有权
标题翻译：具有延迟线的半导体器件
公开(公告)号：US08917127B2
公开(公告)日：2014-12-23
申请号：US14188123
申请日：2014-02-24
申请人： PS4 Luxco S.A.R.L.
发明人： Katsuhiro Kitagawa
IPC分类号： H03L7/06
CPC分类号： H03L7/185 , H03K5/131 , H03K5/133 , H03L7/0814
摘要： Disclosed herein is a device that includes a plurality of one-shot pulse generation circuits connected in series between an input node and an output node. Each of the one-shot pulse generation circuits receives an input clock signal supplied from previously connected one-shot pulse generation circuit to output an output clock signal to subsequently connected one-shot pulse generation circuit. Both of a rising edge and a falling edge of the output clock signal are controlled based on one of a rising edge and a falling edge of the input clock signal. A time period from one of the rising edge and the falling edge of the output clock signal to the other of the rising edge and the falling edge of the output clock signal being variable.
摘要翻译：本文公开了一种包括在输入节点和输出节点之间串联连接的多个单触发脉冲发生电路的装置。每个单触发脉冲发生电路接收从先前连接的单触发脉冲发生电路提供的输入时钟信号，以将输出时钟信号输出到随后连接的单触发脉冲发生电路。基于输入时钟信号的上升沿和下降沿之一来控制输出时钟信号的上升沿和下降沿。从输出时钟信号的上升沿和下降沿之一到输出时钟信号的上升沿和下降沿中的另一个的时间段是可变的。

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