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1. 发明申请

US20160056114A1 TRENCHED FARADAY SHIELDING 有权
标题翻译：高尔夫球场防盗
公开(公告)号：US20160056114A1
公开(公告)日：2016-02-25
申请号：US14463982
申请日：2014-08-20
申请人： Zihao M. Gao , David C. Burdeaux , Wayne R. Burger , Robert A. Pryor , Philippe Renaud
发明人： Zihao M. Gao , David C. Burdeaux , Wayne R. Burger , Robert A. Pryor , Philippe Renaud
IPC分类号： H01L23/60 , H01L29/66 , H01L29/06 , H01L29/40 , H01L21/306 , H01L21/71 , H01L21/265 , H01L29/10 , H01L29/78 , H01L21/283
CPC分类号： H01L23/60 , H01L21/26586 , H01L21/283 , H01L21/30604 , H01L21/71 , H01L29/0634 , H01L29/0653 , H01L29/0696 , H01L29/0847 , H01L29/1045 , H01L29/1095 , H01L29/402 , H01L29/404 , H01L29/407 , H01L29/4175 , H01L29/66659 , H01L29/66681 , H01L29/7817 , H01L29/7823 , H01L29/7835 , H01L2924/0002 , H01L2924/00
摘要： A device includes a semiconductor substrate having a surface with a trench, first and second conduction terminals supported by the semiconductor substrate, a control electrode supported by the semiconductor substrate between the first and second conduction terminals and configured to control flow of charge carriers during operation between the first and second conduction terminals, and a Faraday shield supported by the semiconductor substrate and disposed between the control electrode and the second conduction terminal. At least a portion of the Faraday shield is disposed in the trench.
摘要翻译：一种器件包括具有沟槽的表面的半导体衬底，由半导体衬底支撑的第一和第二导电端子，由第一和第二导电端子之间的半导体衬底支撑的控制电极，并且被配置为在第一和第二导电端子之间的运行期间控制电荷载流子的流动第一和第二导电端子以及由半导体衬底支撑并设置在控制电极和第二导电端子之间的法拉第屏蔽。法拉第屏蔽的至少一部分设置在沟槽中。

2. 发明授权

US09520367B2 Trenched Faraday shielding 有权
标题翻译：倾斜的法拉第屏蔽
公开(公告)号：US09520367B2
公开(公告)日：2016-12-13
申请号：US14463982
申请日：2014-08-20
申请人： Zihao M. Gao , David C. Burdeaux , Wayne R. Burger , Robert A. Pryor , Philippe Renaud
发明人： Zihao M. Gao , David C. Burdeaux , Wayne R. Burger , Robert A. Pryor , Philippe Renaud
IPC分类号： H01L23/60 , H01L29/78 , H01L29/66 , H01L29/06 , H01L21/283 , H01L21/306 , H01L21/71 , H01L29/40 , H01L29/417 , H01L29/08 , H01L21/265 , H01L29/10
CPC分类号： H01L23/60 , H01L21/26586 , H01L21/283 , H01L21/30604 , H01L21/71 , H01L29/0634 , H01L29/0653 , H01L29/0696 , H01L29/0847 , H01L29/1045 , H01L29/1095 , H01L29/402 , H01L29/404 , H01L29/407 , H01L29/4175 , H01L29/66659 , H01L29/66681 , H01L29/7817 , H01L29/7823 , H01L29/7835 , H01L2924/0002 , H01L2924/00
摘要： A device includes a semiconductor substrate having a surface with a trench, first and second conduction terminals supported by the semiconductor substrate, a control electrode supported by the semiconductor substrate between the first and second conduction terminals and configured to control flow of charge carriers during operation between the first and second conduction terminals, and a Faraday shield supported by the semiconductor substrate and disposed between the control electrode and the second conduction terminal. At least a portion of the Faraday shield is disposed in the trench.
摘要翻译：一种器件包括具有沟槽的表面的半导体衬底，由半导体衬底支撑的第一和第二导电端子，由第一和第二导电端子之间的半导体衬底支撑的控制电极，并且被配置为在第一和第二导电端子之间的运行期间控制电荷载流子的流动第一和第二导电端子以及由半导体衬底支撑并设置在控制电极和第二导电端子之间的法拉第屏蔽。法拉第屏蔽的至少一部分设置在沟槽中。

3. 发明授权

US07525152B2 RF power transistor device with metal electromigration design and method thereof 有权
标题翻译：具有金属电迁移设计的RF功率晶体管器件及其方法
公开(公告)号：US07525152B2
公开(公告)日：2009-04-28
申请号：US11678330
申请日：2007-02-23
申请人： Christopher P. Dragon , Wayne R. Burger , Robert A. Pryor
发明人： Christopher P. Dragon , Wayne R. Burger , Robert A. Pryor
IPC分类号： H01L29/76
CPC分类号： H01L23/66 , H01L23/528 , H01L24/02 , H01L29/41758 , H01L29/4238 , H01L29/7835 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01033 , H01L2924/01074 , H01L2924/01079 , H01L2924/13091 , H01L2924/30105
摘要： An RF power transistor with a metal design (70) comprises a drain pad (72) and a plurality of metal drain fingers (74) extending from the drain pad, wherein at least one metal drain finger comprises one or more sections of metal (74-1, 74-2, 100-1, 100-2, 100-3), each section of metal including of one or more branch (54-1, 54-2, 116-1, 116-2, 116-11, 116-21, 116-41) of metal having a metal width maintained within a bamboo regime.
摘要翻译：具有金属设计（70）的RF功率晶体管包括从所述漏极焊盘延伸的漏极焊盘（72）和多个金属排出指（74），其中至少一个金属排出指包括一个或多个金属部分（74 -1,74-2,100-1,100-2,100-3），每个金属部分包括一个或多个分支（54-1,54-2,116-1,116-2,116-11），116-21,116-41）金属的宽度维持在竹制。

4. 发明申请

US20120037969A1 MONOLITHIC MICROWAVE INTEGRATED CIRCUIT 有权
标题翻译：单片微波集成电路
公开(公告)号：US20120037969A1
公开(公告)日：2012-02-16
申请号：US12855479
申请日：2010-08-12
申请人： Paul W. Sanders , Wayne R. Burger , Thuy B. Dao , Joel E. Keys , Michael F. Petras , Robert A. Pryor , Xiaowei Ren
发明人： Paul W. Sanders , Wayne R. Burger , Thuy B. Dao , Joel E. Keys , Michael F. Petras , Robert A. Pryor , Xiaowei Ren
IPC分类号： H01L27/06 , H01L21/82
CPC分类号： H01L23/66 , H01L21/76898 , H01L21/823475 , H01L23/481 , H01L23/5223 , H01L23/5226 , H01L23/5227 , H01L24/48 , H01L24/49 , H01L27/0617 , H01L27/0629 , H01L27/0727 , H01L28/10 , H01L28/40 , H01L29/7816 , H01L2223/6616 , H01L2223/6655 , H01L2223/6683 , H01L2224/48091 , H01L2224/49175 , H01L2225/06541 , H01L2924/00014 , H01L2924/12044 , H01L2924/13062 , H01L2924/14 , H01L2924/1423 , H01L2924/30107 , H03F3/195 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： Low Q associated with passive components of monolithic integrated circuits (ICs) when operated at microwave frequencies can be avoided or mitigated using high resistivity (e.g., ≧100 Ohm-cm) semiconductor substrates (60) and lower resistance inductors (44′, 45′) for the IC (46). This eliminates significant in-substrate electromagnetic coupling losses from planar inductors (44, 45) and interconnections (50-1′, 52-1′, 94, 94′, 94″) overlying the substrate (60). The active transistor(s) (41′) are formed in the substrate (60) proximate the front face (63). Planar capacitors (42′, 43′) are also formed over the front face (63) of the substrate (60). Various terminals (42-1′, 42-2′, 43-1, 43-2′,50′, 51′, 52′, 42-1′, 42-2′, etc.) of the transistor(s) (41′), capacitor(s) (42′, 43′) and inductor(s) (44′, 45′) are coupled to a ground plane (69) on the rear face (62) of the substrate (60) using through-substrate-vias (98, 98′) to minimize parasitic resistance. Parasitic resistance associated with the planar inductors (44′, 45′) and heavy current carrying conductors (52-1′) is minimized by placing them on the outer surface of the IC where they can be made substantially thicker and of lower resistance. The result is a monolithic microwave IC (46, 58) previously unobtainable.
摘要翻译：使用高电阻率（例如≥100欧姆 - 厘米）的半导体衬底（60）和较低电阻电感（44'，45'）可以避免或减轻以微波频率操作时与单片集成电路（IC）的无源部件相关的低Q，）用于IC（46）。这消除了覆盖衬底（60）的平面电感器（44,45）和互连（50-1'，52-1'，94,94'，94“）的显着的衬底内电磁耦合损耗。有源晶体管（41'）在靠近前表面（63）的基底（60）中形成。平面电容器（42'，43'）也形成在衬底（60）的前表面（63）上方。晶体管的各个端子（42-1'，42-2'，43-1,43-2'，50'，51'，52'，42-1'，42-2'等）（41'），电容器（42'，43'）和电感器（44'，45'）耦合到衬底（60）的背面（62）上的接地平面（69）使用贯通衬底通孔（98,98'）来最小化寄生电阻。通过将平面电感器（44'，45'）和大电流承载导体（52-1'）相关联的寄生电阻放置在IC的外表面上，使其可以被制成基本上更厚且电阻更低。其结果是先前无法获得的单片微波IC（46,58）。

5. 发明授权

US09064712B2 Monolithic microwave integrated circuit 有权
标题翻译：单片微波集成电路
公开(公告)号：US09064712B2
公开(公告)日：2015-06-23
申请号：US12855479
申请日：2010-08-12
申请人： Paul W. Sanders , Wayne R. Burger , Thuy B. Dao , Joel E. Keys , Michael F. Petras , Robert A. Pryor , Xiaowei Ren
发明人： Paul W. Sanders , Wayne R. Burger , Thuy B. Dao , Joel E. Keys , Michael F. Petras , Robert A. Pryor , Xiaowei Ren
IPC分类号： H01L23/522 , H01L27/06 , H01L23/48 , H01L23/66 , H03F3/195 , H01L23/00
CPC分类号： H01L23/66 , H01L21/76898 , H01L21/823475 , H01L23/481 , H01L23/5223 , H01L23/5226 , H01L23/5227 , H01L24/48 , H01L24/49 , H01L27/0617 , H01L27/0629 , H01L27/0727 , H01L28/10 , H01L28/40 , H01L29/7816 , H01L2223/6616 , H01L2223/6655 , H01L2223/6683 , H01L2224/48091 , H01L2224/49175 , H01L2225/06541 , H01L2924/00014 , H01L2924/12044 , H01L2924/13062 , H01L2924/14 , H01L2924/1423 , H01L2924/30107 , H03F3/195 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： Low Q associated with passive components of monolithic integrated circuits (ICs) when operated at microwave frequencies can be avoided or mitigated using high resistivity (e.g., ≧100 Ohm-cm) semiconductor substrates (60) and lower resistance inductors (44′, 45′) for the IC (46). This eliminates significant in-substrate electromagnetic coupling losses from planar inductors (44, 45) and interconnections (50-1′, 52-1′, 94, 94′, 94″) overlying the substrate (60). The active transistor(s) (41′) are formed in the substrate (60) proximate the front face (63). Planar capacitors (42′, 43′) are also formed over the front face (63) of the substrate (60). Various terminals (42-1′, 42-2′, 43-1, 43-2′,50′, 51′, 52′, 42-1′, 42-2′, etc.) of the transistor(s) (41′), capacitor(s) (42′, 43′) and inductor(s) (44′, 45′) are coupled to a ground plane (69) on the rear face (62) of the substrate (60) using through-substrate-vias (98, 98′) to minimize parasitic resistance. Parasitic resistance associated with the planar inductors (44′, 45′) and heavy current carrying conductors (52-1′) is minimized by placing them on the outer surface of the IC where they can be made substantially thicker and of lower resistance. The result is a monolithic microwave IC (46, 58) previously unobtainable.
摘要翻译：使用高电阻率（例如≥100欧姆 - 厘米）的半导体衬底（60）和较低电阻电感（44'，45'）可以避免或减轻以微波频率操作时与单片集成电路（IC）的无源部件相关的低Q，）用于IC（46）。这消除了覆盖衬底（60）的平面电感器（44,45）和互连（50-1'，52-1'，94,94'，94“）的显着的衬底内电磁耦合损耗。有源晶体管（41'）在靠近前表面（63）的基底（60）中形成。平面电容器（42'，43'）也形成在衬底（60）的前表面（63）上方。晶体管的各个端子（42-1'，42-2'，43-1,43-2'，50'，51'，52'，42-1'，42-2'等）（41'），电容器（42'，43'）和电感器（44'，45'）耦合到衬底（60）的背面（62）上的接地平面（69）使用贯通衬底通孔（98,98'）来最小化寄生电阻。通过将平面电感器（44'，45'）和大电流承载导体（52-1'）相关联的寄生电阻放置在IC的外表面上，使其可以被制成基本上更厚且电阻更低。其结果是先前无法获得的单片微波IC（46,58）。

6. 发明申请

US20070205506A1 RF POWER TRANSISTOR DEVICE WITH METAL ELECTROMIGRATION DESIGN AND METHOD THEREOF 有权
标题翻译：具有金属电解设计的RF功率晶体管器件及其方法
公开(公告)号：US20070205506A1
公开(公告)日：2007-09-06
申请号：US11678330
申请日：2007-02-23
申请人： Christopher P. Dragon , Wayne R. Burger , Robert A. Pryor
发明人： Christopher P. Dragon , Wayne R. Burger , Robert A. Pryor
IPC分类号： H01L23/34
CPC分类号： H01L23/66 , H01L23/528 , H01L24/02 , H01L29/41758 , H01L29/4238 , H01L29/7835 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01033 , H01L2924/01074 , H01L2924/01079 , H01L2924/13091 , H01L2924/30105
摘要： An RF power transistor with a metal design (70) comprises a drain pad (72) and a plurality of metal drain fingers (74) extending from the drain pad, wherein at least one metal drain finger comprises one or more sections of metal (74-1, 74-2, 100-1, 100-2, 100-3), each section of metal including of one or more branch (54-1, 54-2, 116-1, 116-2, 116-11, 116-21, 116-41) of metal having a metal width maintained within a bamboo regime.
摘要翻译：具有金属设计（70）的RF功率晶体管包括从所述漏极焊盘延伸的漏极焊盘（72）和多个金属排出指（74），其中至少一个金属排出指包括一个或多个金属部分（74 - 1，74 - 2，100 - 1，100 - 2，100 - 3），每个金属部分包括一个或多个分支（54 - 1，54 - 2，116 - 1，116 - 2，116 - ，116-21,116-41）金属的金属宽度保持在竹制。

7. 发明申请

US20100140814A1 RF DEVICE AND METHOD WITH TRENCH UNDER BOND PAD FEATURE 有权
标题翻译：射频设备和方法，在绑定功能下进行TRENCH
公开(公告)号：US20100140814A1
公开(公告)日：2010-06-10
申请号：US12328319
申请日：2008-12-04
申请人： Jeffrey K. Jones , Margaret A. Szymanowski , Michele L. Miera , Xiaowei Ren , Wayne R. Burger , Mark A. Bennett , Colin Kerr
发明人： Jeffrey K. Jones , Margaret A. Szymanowski , Michele L. Miera , Xiaowei Ren , Wayne R. Burger , Mark A. Bennett , Colin Kerr
IPC分类号： H01L21/768 , H01L23/488
CPC分类号： H01L24/05 , H01L24/03 , H01L29/0649 , H01L2224/05076 , H01L2224/05558 , H01L2224/05576 , H01L2924/01006 , H01L2924/01014 , H01L2924/01015 , H01L2924/01021 , H01L2924/01027 , H01L2924/01032 , H01L2924/01033 , H01L2924/01057 , H01L2924/01082 , H01L2924/05042 , H01L2924/1306 , H01L2924/13062 , H01L2924/13091 , H01L2924/14 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H01L2924/00
摘要： Electronic elements (44, 44′, 44″) having an active device region (46) and bonding pad (BP) region (60) on a common substrate (45) desirably include a dielectric region underlying the BP (35) to reduce the parasitic impedance of the BP (35) and its interconnection (41) as the electronic elements (44, 44′, 44″) are scaled to higher power and/or operating frequency. Mechanical stress created by plain (e.g., oxide only) dielectric regions (36′) can adversely affect performance, manufacturing yield, pad-to-device proximity and occupied area. This can be avoided by providing a composite dielectric region (62, 62′, 62″) having electrically isolated inclusions (65, 65′, 65′) of a thermal expansion coefficient (TEC) less than that of the dielectric material (78, 78′, 78″) in which they are embedded and/or closer to the substrate (45) TEC. For silicon substrates (45), poly or amorphous silicon is suitable for the inclusions (65, 65′, 65″) and silicon oxide for the dielectric material (78, 78′, 78″). The inclusions (65, 65′, 65″) preferably have a blade-like shape separated by and enclosed within the dielectric material (78, 78′, 78″).
摘要翻译：具有在公共衬底（45）上的有源器件区（46）和焊盘（BP）区（60）的电子元件（44,44'，44“）理想地包括位于BP（35）下方的电介质区域，以减少作为电子元件（44,44'，44“）的BP（35）及其互连（41）的寄生阻抗被缩放到更高的功率和/或工作频率。由平坦（例如，仅氧化物）介电区域（36'）产生的机械应力可能不利地影响性能，制造产量，焊盘到设备的接近度和占用面积。这可以通过提供具有电绝缘的包含物（65,65'，65'）的复合电介质区域（65,65'，65'）来避免，所述电绝缘夹杂物的热膨胀系数（TEC）小于电介质材料（78， 78'，78“），其中它们被嵌入和/或更靠近衬底（45）TEC。对于硅衬底（45），多晶硅或非晶硅适合用于介电材料（78,78'，78“）的夹杂物（65,65'，65”）和氧化硅。夹杂物（65,65'，65“）优选具有由电介质材料（78,78'，78”）分隔开并封闭在其中的刀片形状。

8. 发明申请

US20100140714A1 LOW LOSS SUBSTRATE FOR INTEGRATED PASSIVE DEVICES 有权
标题翻译：用于集成无源器件的低损耗基板
公开(公告)号：US20100140714A1
公开(公告)日：2010-06-10
申请号：US12328325
申请日：2008-12-04
申请人： Xiaowei Ren , Wayne R. Burger , Colin Kerr , Mark A. Bennett
发明人： Xiaowei Ren , Wayne R. Burger , Colin Kerr , Mark A. Bennett
IPC分类号： H01L29/78 , H01L21/76 , H01L27/00
CPC分类号： H01L27/08 , H01L21/763 , H01L27/0207 , H01L27/0617 , H01L27/0629 , H01L28/10
摘要： Electronic elements (44, 44′, 44″) having an active device region (46) and integrated passive device (IPD) region (60) on a common substrate (45) preferably include a composite dielectric region (62, 62′, 62″) in the IPD region underlying the IPD (35) to reduce electromagnetic (E-M) (33) coupling to the substrate (45). Mechanical stress created by plain dielectric regions (36′) and its deleterious affect on performance, manufacturing yield and occupied area may be avoided by providing electrically isolated inclusions (65, 65′, 65″) in the composite dielectric region (62, 62′, 62″) of a material having a thermal expansion coefficient (TEC) less than that of the dielectric material (78, 78′, 78″) in the composite dielectric region (62, 62′, 62″). For silicon substrates (45), non-single crystal silicon is suitable for the inclusions (65, 65′, 65″) and silicon oxide for the dielectric material (78, 78′, 78″). The inclusions (65, 65′, 65″) preferably have a blade-like shape separated by and enclosed within the dielectric material (78, 78′, 78″).
摘要翻译：在共用衬底（45）上具有有源器件区域（46）和集成无源器件（IPD）区域（60）的电子元件（44,44'，44“）优选地包括复合电介质区域（62,62'，62 “）在IPD（IP）（35）下方的IPD区域中以减少耦合到衬底（45）的电磁（EM）（33）。可以通过在复合介电区域（62,62'）中提供电隔离的夹杂物（65,65'，65“）来避免由平坦介电区域（36'）产生的机械应力及其对性能，制造产量和占用面积的有害影响，，62“）具有比所述复合介电区域（62,62'，62”）中的电介质材料（78,78'，78“）的热膨胀系数小的热膨胀系数（TEC）的材料。对于硅衬底（45），非单晶硅适用于电介质材料（78,78'，78“）的夹杂物（65,65'，65”）和氧化硅。夹杂物（65,65'，65“）优选具有由电介质材料（78,78'，78”）分隔开并封闭在其中的刀片形状。

9. 发明授权

US08906773B2 Integrated circuits including integrated passive devices and methods of manufacture thereof 有权
标题翻译：集成电路，包括集成无源器件及其制造方法
公开(公告)号：US08906773B2
公开(公告)日：2014-12-09
申请号：US13712051
申请日：2012-12-12
申请人： Xiaowei Ren , Wayne R. Burger
发明人： Xiaowei Ren , Wayne R. Burger
IPC分类号： H01L21/20 , H01L27/108
CPC分类号： H01L23/5223 , H01L28/75 , H01L28/84 , H01L2924/0002 , H01L2924/00
摘要： Embodiments of integrated passive devices (e.g., metal insulator metal, or MIM, capacitors) and methods of their formation include depositing a composite electrode over a semiconductor substrate (e.g., on a dielectric layer above the substrate surface), and depositing an insulator layer over the composite electrode. The composite electrode includes an underlying electrode and an overlying electrode deposited on a top surface of the underlying electrode. The underlying electrode is formed from a first conductive material (e.g., AlCuW), and the overlying electrode is formed from a second, different conductive material (e.g., AlCu). The top surface of the underlying electrode may have a relatively rough surface morphology, and the top surface of the overlying electrode may have a relatively smooth surface morphology. For high frequency, high power applications, both the composite electrode and the insulator layer may be thicker than in some conventional integrated passive devices.
摘要翻译：集成无源器件（例如，金属绝缘体金属或MIM，电容器）的实施例及其形成方法包括在半导体衬底（例如，在衬底表面上方的电介质层上）沉积复合电极，以及将绝缘体层沉积在复合电极。复合电极包括底层电极和沉积在下面电极的顶表面上的上覆电极。底层电极由第一导电材料（例如，AlCuW）形成，并且上覆电极由第二不同的导电材料（例如AlCu）形成。底层电极的顶表面可能具有相对粗糙的表面形态，并且上覆电极的顶表面可具有相对平滑的表面形态。对于高频，高功率应用，复合电极和绝缘体层可能比一些传统的集成无源器件更厚。

10. 发明授权

US06744117B2 High frequency semiconductor device and method of manufacture 有权
标题翻译：高频半导体器件及其制造方法
公开(公告)号：US06744117B2
公开(公告)日：2004-06-01
申请号：US10086061
申请日：2002-02-28
申请人： Christopher P. Dragon , Wayne R. Burger , Daniel J. Lamey
发明人： Christopher P. Dragon , Wayne R. Burger , Daniel J. Lamey
IPC分类号： H01L23552
CPC分类号： H01L29/402 , H01L29/4175 , H01L29/41758 , H01L29/41775 , H01L29/4232 , H01L29/42372 , H01L29/4238 , H01L29/78 , H01L29/7835
摘要： A semiconductor device (10) having a gate (15), a source (19), and a drain (20) with a gate bus (25) and first ground shield (24) patterned from a first metal layer and a second ground shield (31) patterned from a second metal layer. The first ground shield (24) and the second ground shield (31) lower the capacitance of device (10) making it suitable for high frequency applications and housing in a plastic package.
摘要翻译：一种具有栅极（15），源极（19）和漏极（20）的半导体器件（10），其具有从第一金属层和第二接地屏蔽层图案化的栅极总线（25）和第一接地屏蔽（24）（31）从第二金属层图案化。第一接地屏蔽（24）和第二接地屏蔽（31）降低器件（10）的电容，使其适合于高频应用和塑料封装中的外壳。

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