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1. 发明申请

US20100140814A1 RF DEVICE AND METHOD WITH TRENCH UNDER BOND PAD FEATURE 有权
标题翻译：射频设备和方法，在绑定功能下进行TRENCH
公开(公告)号：US20100140814A1
公开(公告)日：2010-06-10
申请号：US12328319
申请日：2008-12-04
申请人： Jeffrey K. Jones , Margaret A. Szymanowski , Michele L. Miera , Xiaowei Ren , Wayne R. Burger , Mark A. Bennett , Colin Kerr
发明人： Jeffrey K. Jones , Margaret A. Szymanowski , Michele L. Miera , Xiaowei Ren , Wayne R. Burger , Mark A. Bennett , Colin Kerr
IPC分类号： H01L21/768 , H01L23/488
CPC分类号： H01L24/05 , H01L24/03 , H01L29/0649 , H01L2224/05076 , H01L2224/05558 , H01L2224/05576 , H01L2924/01006 , H01L2924/01014 , H01L2924/01015 , H01L2924/01021 , H01L2924/01027 , H01L2924/01032 , H01L2924/01033 , H01L2924/01057 , H01L2924/01082 , H01L2924/05042 , H01L2924/1306 , H01L2924/13062 , H01L2924/13091 , H01L2924/14 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H01L2924/00
摘要： Electronic elements (44, 44′, 44″) having an active device region (46) and bonding pad (BP) region (60) on a common substrate (45) desirably include a dielectric region underlying the BP (35) to reduce the parasitic impedance of the BP (35) and its interconnection (41) as the electronic elements (44, 44′, 44″) are scaled to higher power and/or operating frequency. Mechanical stress created by plain (e.g., oxide only) dielectric regions (36′) can adversely affect performance, manufacturing yield, pad-to-device proximity and occupied area. This can be avoided by providing a composite dielectric region (62, 62′, 62″) having electrically isolated inclusions (65, 65′, 65′) of a thermal expansion coefficient (TEC) less than that of the dielectric material (78, 78′, 78″) in which they are embedded and/or closer to the substrate (45) TEC. For silicon substrates (45), poly or amorphous silicon is suitable for the inclusions (65, 65′, 65″) and silicon oxide for the dielectric material (78, 78′, 78″). The inclusions (65, 65′, 65″) preferably have a blade-like shape separated by and enclosed within the dielectric material (78, 78′, 78″).
摘要翻译：具有在公共衬底（45）上的有源器件区（46）和焊盘（BP）区（60）的电子元件（44,44'，44“）理想地包括位于BP（35）下方的电介质区域，以减少作为电子元件（44,44'，44“）的BP（35）及其互连（41）的寄生阻抗被缩放到更高的功率和/或工作频率。由平坦（例如，仅氧化物）介电区域（36'）产生的机械应力可能不利地影响性能，制造产量，焊盘到设备的接近度和占用面积。这可以通过提供具有电绝缘的包含物（65,65'，65'）的复合电介质区域（65,65'，65'）来避免，所述电绝缘夹杂物的热膨胀系数（TEC）小于电介质材料（78， 78'，78“），其中它们被嵌入和/或更靠近衬底（45）TEC。对于硅衬底（45），多晶硅或非晶硅适合用于介电材料（78,78'，78“）的夹杂物（65,65'，65”）和氧化硅。夹杂物（65,65'，65“）优选具有由电介质材料（78,78'，78”）分隔开并封闭在其中的刀片形状。

2. 发明申请

US20100140714A1 LOW LOSS SUBSTRATE FOR INTEGRATED PASSIVE DEVICES 有权
标题翻译：用于集成无源器件的低损耗基板
公开(公告)号：US20100140714A1
公开(公告)日：2010-06-10
申请号：US12328325
申请日：2008-12-04
申请人： Xiaowei Ren , Wayne R. Burger , Colin Kerr , Mark A. Bennett
发明人： Xiaowei Ren , Wayne R. Burger , Colin Kerr , Mark A. Bennett
IPC分类号： H01L29/78 , H01L21/76 , H01L27/00
CPC分类号： H01L27/08 , H01L21/763 , H01L27/0207 , H01L27/0617 , H01L27/0629 , H01L28/10
摘要： Electronic elements (44, 44′, 44″) having an active device region (46) and integrated passive device (IPD) region (60) on a common substrate (45) preferably include a composite dielectric region (62, 62′, 62″) in the IPD region underlying the IPD (35) to reduce electromagnetic (E-M) (33) coupling to the substrate (45). Mechanical stress created by plain dielectric regions (36′) and its deleterious affect on performance, manufacturing yield and occupied area may be avoided by providing electrically isolated inclusions (65, 65′, 65″) in the composite dielectric region (62, 62′, 62″) of a material having a thermal expansion coefficient (TEC) less than that of the dielectric material (78, 78′, 78″) in the composite dielectric region (62, 62′, 62″). For silicon substrates (45), non-single crystal silicon is suitable for the inclusions (65, 65′, 65″) and silicon oxide for the dielectric material (78, 78′, 78″). The inclusions (65, 65′, 65″) preferably have a blade-like shape separated by and enclosed within the dielectric material (78, 78′, 78″).
摘要翻译：在共用衬底（45）上具有有源器件区域（46）和集成无源器件（IPD）区域（60）的电子元件（44,44'，44“）优选地包括复合电介质区域（62,62'，62 “）在IPD（IP）（35）下方的IPD区域中以减少耦合到衬底（45）的电磁（EM）（33）。可以通过在复合介电区域（62,62'）中提供电隔离的夹杂物（65,65'，65“）来避免由平坦介电区域（36'）产生的机械应力及其对性能，制造产量和占用面积的有害影响，，62“）具有比所述复合介电区域（62,62'，62”）中的电介质材料（78,78'，78“）的热膨胀系数小的热膨胀系数（TEC）的材料。对于硅衬底（45），非单晶硅适用于电介质材料（78,78'，78“）的夹杂物（65,65'，65”）和氧化硅。夹杂物（65,65'，65“）优选具有由电介质材料（78,78'，78”）分隔开并封闭在其中的刀片形状。

3. 发明授权

US08283748B2 Low loss substrate for integrated passive devices 有权
标题翻译：集成无源器件的低损耗衬底
公开(公告)号：US08283748B2
公开(公告)日：2012-10-09
申请号：US13277847
申请日：2011-10-20
申请人： Xiaowei Ren , Wayne R. Burger , Colin Kerr , Mark A. Bennett
发明人： Xiaowei Ren , Wayne R. Burger , Colin Kerr , Mark A. Bennett
IPC分类号： H01L21/70
CPC分类号： H01L27/08 , H01L21/763 , H01L27/0207 , H01L27/0617 , H01L27/0629 , H01L28/10
摘要： Electronic elements having an active device region and integrated passive device (IPD) region on a common substrate preferably include a composite dielectric region in the IPD region underlying the IPD to reduce electro-magnetic (E-M) coupling to the substrate. Mechanical stress created by plain dielectric regions and its deleterious affect on performance, manufacturing yield and occupied area may be avoided by providing electrically isolated inclusions in the composite dielectric region of a material having a thermal expansion coefficient (TEC) less than that of the dielectric material in the composite dielectric region. For silicon substrates, non-single crystal silicon is suitable for the inclusions and silicon oxide for the dielectric material. The inclusions preferably have a blade-like shape separated by and enclosed within the dielectric material.
摘要翻译：具有有源器件区域和在公共衬底上的集成无源器件（IPD）区域的电子元件优选地包括在IPD下面的IPD区域中的复合电介质区域，以减少与衬底的电磁（E-M）耦合。通过在具有小于介电材料的热膨胀系数（TEC）的材料的复合介电区域中提供电隔离的夹杂物，可以避免由平坦介质区域产生的机械应力及其对性能，制造产量和占用面积的有害影响在复合电介质区域中。对于硅衬底，非单晶硅适用于介电材料的夹杂物和氧化硅。夹杂物优选具有由介电材料分离并封闭在电介质材料内的刀片状形状。

4. 发明授权

US08134241B2 Electronic elements and devices with trench under bond pad feature 有权
标题翻译：电子元件和具有沟槽底部焊盘功能的器件
公开(公告)号：US08134241B2
公开(公告)日：2012-03-13
申请号：US13179295
申请日：2011-07-08
申请人： Jeffrey K. Jones , Margaret A. Szymanowski , Michele L. Miera , Xiaowei Ren , Wayne R. Burger , Mark A. Bennett , Colin Kerr
发明人： Jeffrey K. Jones , Margaret A. Szymanowski , Michele L. Miera , Xiaowei Ren , Wayne R. Burger , Mark A. Bennett , Colin Kerr
IPC分类号： H01L23/48
CPC分类号： H01L24/05 , H01L24/03 , H01L29/0649 , H01L2224/05076 , H01L2224/05558 , H01L2224/05576 , H01L2924/01006 , H01L2924/01014 , H01L2924/01015 , H01L2924/01021 , H01L2924/01027 , H01L2924/01032 , H01L2924/01033 , H01L2924/01057 , H01L2924/01082 , H01L2924/05042 , H01L2924/1306 , H01L2924/13062 , H01L2924/13091 , H01L2924/14 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H01L2924/00
摘要： Electronic elements having an active device region and bonding pad (BP) region on a common substrate desirably include a dielectric region underlying the BP to reduce the parasitic impedance of the BP and its interconnection as the electronic elements are scaled to higher power and/or operating frequency. Mechanical stress created by plain (e.g., oxide only) dielectric regions can adversely affect performance, manufacturing yield, pad-to-device proximity and occupied area. This can be avoided by providing a composite dielectric region having electrically isolated inclusions of a thermal expansion coefficient (TEC) less than that of the dielectric material in which they are embedded and/or closer to the substrate TEC. For silicon substrates, poly or amorphous silicon is suitable for the inclusions and silicon oxide for the dielectric material. The inclusions preferably have a blade-like shape separated by and enclosed within the dielectric material.
摘要翻译：在共同衬底上具有有源器件区域和焊盘（BP）区域的电子元件期望地包括位于BP之下的电介质区域，以在电子元件被缩放到更高功率和/或操作时降低BP的寄生阻抗及其互连频率。由平原（例如，仅氧化物）电介质区域产生的机械应力可能不利地影响性能，制造产量，焊盘到设备的接近度和占用面积。这可以通过提供具有比它们被嵌入和/或更靠近衬底TEC的介电材料的热膨胀系数小的热膨胀系数（TEC）的电隔离夹杂物的复合电介质区域来避免。对于硅衬底，聚硅或非晶硅适用于介电材料的夹杂物和氧化硅。夹杂物优选具有由介电材料分离并封闭在电介质材料内的刀片状形状。

5. 发明授权

US08071461B2 Low loss substrate for integrated passive devices 有权
标题翻译：集成无源器件的低损耗衬底
公开(公告)号：US08071461B2
公开(公告)日：2011-12-06
申请号：US12328325
申请日：2008-12-04
申请人： Xiaowei Ren , Wayne R. Burger , Colin Kerr , Mark A. Bennett
发明人： Xiaowei Ren , Wayne R. Burger , Colin Kerr , Mark A. Bennett
IPC分类号： H01L21/76
CPC分类号： H01L27/08 , H01L21/763 , H01L27/0207 , H01L27/0617 , H01L27/0629 , H01L28/10
摘要： Electronic elements (44, 44′, 44″) having an active device region (46) and integrated passive device (IPD) region (60) on a common substrate (45) preferably include a composite dielectric region (62, 62′, 62″) in the IPD region underlying the IPD (35) to reduce electromagnetic (E-M) (33) coupling to the substrate (45). Mechanical stress created by plain dielectric regions (36′) and its deleterious affect on performance, manufacturing yield and occupied area may be avoided by providing electrically isolated inclusions (65, 65′, 65″) in the composite dielectric region (62, 62′, 62″) of a material having a thermal expansion coefficient (TEC) less than that of the dielectric material (78, 78′, 78″) in the composite dielectric region (62, 62′, 62″). For silicon substrates (45), non-single crystal silicon is suitable for the inclusions (65, 65′, 65″) and silicon oxide for the dielectric material (78, 78′, 78″). The inclusions (65, 65′, 65″) preferably have a blade-like shape separated by and enclosed within the dielectric material (78, 78′, 78″).
摘要翻译：在共用衬底（45）上具有有源器件区域（46）和集成无源器件（IPD）区域（60）的电子元件（44,44'，44“）优选地包括复合电介质区域（62,62'，62 “）在IPD（IP）（35）下方的IPD区域中以减少耦合到衬底（45）的电磁（EM）（33）。可以通过在复合介电区域（62,62'）中提供电隔离的夹杂物（65,65'，65“）来避免由平坦介电区域（36'）产生的机械应力及其对性能，制造产量和占用面积的有害影响，，62“）具有比所述复合介电区域（62,62'，62”）中的电介质材料（78,78'，78“）的热膨胀系数小的热膨胀系数（TEC）的材料。对于硅衬底（45），非单晶硅适用于电介质材料（78,78'，78“）的夹杂物（65,65'，65”）和氧化硅。夹杂物（65,65'，65“）优选具有由电介质材料（78,78'，78”）分隔开并封闭在其中的刀片形状。

6. 发明申请

US20120038023A1 LOW LOSS SUBSTRATE FOR INTEGRATED PASSIVE DEVICES 有权
标题翻译：用于集成无源器件的低损耗基板
公开(公告)号：US20120038023A1
公开(公告)日：2012-02-16
申请号：US13277847
申请日：2011-10-20
申请人： Xiaowei Ren , Wayne R. Burger , Colin Kerr , Mark A. Bennett
发明人： Xiaowei Ren , Wayne R. Burger , Colin Kerr , Mark A. Bennett
IPC分类号： H01L29/06
CPC分类号： H01L27/08 , H01L21/763 , H01L27/0207 , H01L27/0617 , H01L27/0629 , H01L28/10
摘要： Electronic elements having an active device region and integrated passive device (IPD) region on a common substrate preferably include a composite dielectric region in the IPD region underlying the IPD to reduce electro-magnetic (E-M) coupling to the substrate. Mechanical stress created by plain dielectric regions and its deleterious affect on performance, manufacturing yield and occupied area may be avoided by providing electrically isolated inclusions in the composite dielectric region of a material having a thermal expansion coefficient (TEC) less than that of the dielectric material in the composite dielectric region. For silicon substrates, non-single crystal silicon is suitable for the inclusions and silicon oxide for the dielectric material. The inclusions preferably have a blade-like shape separated by and enclosed within the dielectric material.
摘要翻译：具有有源器件区域和在公共衬底上的集成无源器件（IPD）区域的电子元件优选地包括在IPD下面的IPD区域中的复合电介质区域，以减少与衬底的电磁（E-M）耦合。通过在具有小于介电材料的热膨胀系数（TEC）的材料的复合介电区域中提供电隔离的夹杂物，可以避免由平坦介质区域产生的机械应力及其对性能，制造产量和占用面积的有害影响在复合电介质区域中。对于硅衬底，非单晶硅适用于介电材料的夹杂物和氧化硅。夹杂物优选具有由介电材料分离并封闭在电介质材料内的刀片状形状。

7. 发明申请

US20110266687A1 ELECTRONIC ELEMENTS AND DEVICES WITH TRENCH UNDER BOND PAD FEATURE 有权
标题翻译：电子元件和装置，具有绑定功能的底板
公开(公告)号：US20110266687A1
公开(公告)日：2011-11-03
申请号：US13179295
申请日：2011-07-08
申请人： Jeffrey K. Jones , Margaret A. Szymanowski , Michele L. Miera , Xiaowei Ren , Wayne R. Burger , Mark A. Bennett , Colin Kerr
发明人： Jeffrey K. Jones , Margaret A. Szymanowski , Michele L. Miera , Xiaowei Ren , Wayne R. Burger , Mark A. Bennett , Colin Kerr
IPC分类号： H01L23/488
CPC分类号： H01L24/05 , H01L24/03 , H01L29/0649 , H01L2224/05076 , H01L2224/05558 , H01L2224/05576 , H01L2924/01006 , H01L2924/01014 , H01L2924/01015 , H01L2924/01021 , H01L2924/01027 , H01L2924/01032 , H01L2924/01033 , H01L2924/01057 , H01L2924/01082 , H01L2924/05042 , H01L2924/1306 , H01L2924/13062 , H01L2924/13091 , H01L2924/14 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H01L2924/00
摘要： Electronic elements having an active device region and bonding pad (BP) region on a common substrate desirably include a dielectric region underlying the BP to reduce the parasitic impedance of the BP and its interconnection as the electronic elements are scaled to higher power and/or operating frequency. Mechanical stress created by plain (e.g., oxide only) dielectric regions can adversely affect performance, manufacturing yield, pad-to-device proximity and occupied area. This can be avoided by providing a composite dielectric region having electrically isolated inclusions of a thermal expansion coefficient (TEC) less than that of the dielectric material in which they are embedded and/or closer to the substrate TEC. For silicon substrates, poly or amorphous silicon is suitable for the inclusions and silicon oxide for the dielectric material. The inclusions preferably have a blade-like shape separated by and enclosed within the dielectric material.
摘要翻译：在共同衬底上具有有源器件区域和焊盘（BP）区域的电子元件期望地包括位于BP之下的电介质区域，以在电子元件被缩放到更高功率和/或操作时降低BP的寄生阻抗及其互连频率。由平原（例如，仅氧化物）电介质区域产生的机械应力可能不利地影响性能，制造产量，焊盘到设备的接近度和占用面积。这可以通过提供具有比它们被嵌入和/或更靠近衬底TEC的介电材料的热膨胀系数小的热膨胀系数（TEC）的电隔离夹杂物的复合电介质区域来避免。对于硅衬底，聚硅或非晶硅适用于介电材料的夹杂物和氧化硅。夹杂物优选具有由介电材料分离并封闭在电介质材料内的刀片状形状。

8. 发明授权

US07998852B2 Methods for forming an RF device with trench under bond pad feature 有权
标题翻译：用于在接合垫特征下形成具有沟槽的RF器件的方法
公开(公告)号：US07998852B2
公开(公告)日：2011-08-16
申请号：US12328319
申请日：2008-12-04
申请人： Jeffrey K. Jones , Margaret A. Szymanowski , Michele L. Miera , Xiaowei Ren , Wayne R. Burger , Mark A. Bennett , Colin Kerr
发明人： Jeffrey K. Jones , Margaret A. Szymanowski , Michele L. Miera , Xiaowei Ren , Wayne R. Burger , Mark A. Bennett , Colin Kerr
IPC分类号： H01L21/44
CPC分类号： H01L24/05 , H01L24/03 , H01L29/0649 , H01L2224/05076 , H01L2224/05558 , H01L2224/05576 , H01L2924/01006 , H01L2924/01014 , H01L2924/01015 , H01L2924/01021 , H01L2924/01027 , H01L2924/01032 , H01L2924/01033 , H01L2924/01057 , H01L2924/01082 , H01L2924/05042 , H01L2924/1306 , H01L2924/13062 , H01L2924/13091 , H01L2924/14 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H01L2924/00
摘要： Electronic elements (44, 44′, 44″) having an active device region (46) and bonding pad (BP) region (60) on a common substrate (45) desirably include a dielectric region underlying the BP (35) to reduce the parasitic impedance of the BP (35) and its interconnection (41) as the electronic elements (44, 44′, 44″) are scaled to higher power and/or operating frequency. Mechanical stress created by plain (e.g., oxide only) dielectric regions (36′) can adversely affect performance, manufacturing yield, pad-to-device proximity and occupied area. This can be avoided by providing a composite dielectric region (62, 62′, 62″) having electrically isolated inclusions (65, 65′, 65′) of a thermal expansion coefficient (TEC) less than that of the dielectric material (78, 78′, 78″) in which they are embedded and/or closer to the substrate (45) TEC. For silicon substrates (45), poly or amorphous silicon is suitable for the inclusions (65, 65′, 65″) and silicon oxide for the dielectric material (78, 78′, 78″). The inclusions (65, 65′, 65″) preferably have a blade-like shape separated by and enclosed within the dielectric material (78, 78′, 78″).
摘要翻译：具有在公共衬底（45）上的有源器件区（46）和焊盘（BP）区（60）的电子元件（44,44'，44“）理想地包括位于BP（35）下方的电介质区域，以减少作为电子元件（44,44'，44“）的BP（35）及其互连（41）的寄生阻抗被缩放到更高的功率和/或工作频率。由平坦（例如，仅氧化物）介电区域（36'）产生的机械应力可能不利地影响性能，制造产量，焊盘到设备的接近度和占用面积。这可以通过提供具有电绝缘夹杂物（65,65'，65'）的复合电介质区域（65,65'，65'）来避免，所述电绝缘夹杂物的热膨胀系数（TEC）小于电介质材料（78， 78'，78“），其中它们被嵌入和/或更靠近衬底（45）TEC。对于硅衬底（45），多晶硅或非晶硅适合用于介电材料（78,78'，78“）的夹杂物（65,65'，65”）和氧化硅。夹杂物（65,65'，65“）优选具有由电介质材料（78,78'，78”）分隔开并封闭在其中的刀片形状。

9. 发明授权

US11342829B2 Ocean current and tidal power electric generator 有权
公开(公告)号：US11342829B2
公开(公告)日：2022-05-24
申请号：US16478105
申请日：2018-01-16
申请人： Colin Kerr
发明人： Colin Kerr
IPC分类号： H02K44/10 , H02K44/08 , F03B13/12 , H02K44/12 , H02K44/16
摘要： Embodiments of an apparatus for generating electric power from flowing seawater are disclosed. Embodiments form fluid channels having magnetic fields through which seawater will flow. Electrodes are arranged with respect to the fluid channels and connected together such that electric power is generated as seawater flows through the channels.

10. 发明授权

US06712166B2 Energy management system 失效
标题翻译：能源管理系统
公开(公告)号：US06712166B2
公开(公告)日：2004-03-30
申请号：US09798144
申请日：2001-03-02
申请人： Allan Rush , Michael Perry , Colin Kerr
发明人： Allan Rush , Michael Perry , Colin Kerr
IPC分类号： B62M110
CPC分类号： B60K6/12 , B60T1/10 , B60T10/04 , F16D57/06 , F16D61/00 , Y02T10/6208
摘要： An energy management system operable in three modes of operation to either drive or retard the drive shaft (110) of a vehicle, or in a neutral mode, to have no driving or retarding influence on the drive shaft. The system includes energy accumulating means (100, 101) which is operable to store and release energy through receipt and release of fluid, pumping means (104) in fluid communication with the energy communication means (100, 101), a reservoir (107) of fluid in communication with the pumping means (104), and coupling means for coupling the pumping means (110) to the drive shaft (110). Whereby in the retarding mode of the system, the drive shaft (110) drives the pumping means (104) to pump fluid to the energy accumulating means (100, 101), and whereby in the driving mode of the system, the energy accumulating means (100, 101) releases fluid to drive the pumping means (104) which drives the drive shaft (110). Whereby in the neutral mode of the system, the pumping means (104) is inoperative to exert any driving or retarding influence on the drive shaft (110). A retarding system is also provided, as is a terrain logging facility for logging the terrain of a route over which a vehicle travels.
摘要翻译：一种能够以三种操作模式操作的能量管理系统，用于驱动或延迟车辆的驱动轴（110）或中立模式，以对驱动轴没有驱动或延迟影响。该系统包括能量累积装置（100,101），其可操作以通过接收和释放流体来储存和释放能量，泵送装置（104）与能量通信装置（100,101）流体连通，储存器（107）的与泵送装置（104）连通的流体，以及用于将泵送装置（110）联接到驱动轴（110）的联接装置。在该系统的延迟模式中，驱动轴（110）驱动泵送装置（104）将流体泵送到能量积聚装置（100,101），并且由此在系统的驱动模式下，能量积累装置（100,101）释放流体以驱动驱动驱动轴（110）的泵送装置（104）。在系统的中立模式下，泵送装置（104）不起作用以对驱动轴（110）施加任何驱动或延迟影响。还提供了延迟系统，以及用于记录车辆行驶的路线的地形的地形测井设备。

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