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    • 3. 发明授权
      US07838356B2 Gate dielectric first replacement gate processes and integrated circuits therefrom 有权
    • Gate dielectric first replacement gate processes and integrated circuits therefrom
    • 栅介质第一替代栅极工艺及其集成电路
    • US07838356B2
    • 2010-11-23
    • US12347197
    • 2008-12-31
    • Brian K. Kirkpatrick , Freidoon Mehrad , Shaofeng Yu
    • Brian K. Kirkpatrick , Freidoon Mehrad , Shaofeng Yu
    • H01L21/8238
    • H01L21/823842 , H01L29/513 , H01L29/66545 , H01L29/66553 , H01L29/6656
    • A method for fabricating a CMOS integrated circuit (IC) and ICs therefrom includes the steps of providing a substrate having a semiconductor surface, wherein the semiconductor surface has PMOS regions for PMOS devices and NMOS regions for NMOS devices. A gate dielectric layer is formed on the PMOS regions and NMOS regions. An original gate electrode layer is formed on the gate dielectric layer. A gate masking layer is applied on the gate electrode layer. Etching is used to pattern the original gate electrode layer to simultaneously form original gate electrodes for the PMOS devices and NMOS devices. Source and drain regions are formed for the PMOS devices and NMOS devices. The original gate electrodes are removed for at least one of the PMOS devices and NMOS devices to form trenches using an etch process, such as a hydroxide-based solution, wherein at least a portion and generally substantially all of the gate dielectric layer is preserved. A metal comprising replacement gates is formed in the trenches, and fabrication of the IC is completed.
    • 一种用于制造CMOS集成电路（IC）及其IC的方法包括提供具有半导体表面的衬底的步骤，其中半导体表面具有用于PMOS器件的PMOS区域和用于NMOS器件的NMOS区域。 栅极电介质层形成在PMOS区域和NMOS区域上。 在栅极电介质层上形成原始栅电极层。 栅极掩模层被施加在栅极电极层上。 蚀刻用于对原始栅极电极层进行图案化以同时形成用于PMOS器件和NMOS器件的原始栅电极。 为PMOS器件和NMOS器件形成源极和漏极区域。 为了至少一个PMOS器件和NMOS器件去除原始栅电极，以使用诸如基于氢氧化物的溶液的蚀刻工艺形成沟槽，其中保留了栅极电介质层的至少一部分和基本上全部的栅极电介质层。 在沟槽中形成包括置换栅极的金属，并且完成IC的制造。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 4. 发明申请
      US20110031557A1 GATE DIELECTRIC FIRST REPLACEMENT GATE PROCESSES AND INTEGRATED CIRCUITS THEREFROM 有权
    • GATE DIELECTRIC FIRST REPLACEMENT GATE PROCESSES AND INTEGRATED CIRCUITS THEREFROM
    • 门式电介质第一次更换门电路及集成电路
    • US20110031557A1
    • 2011-02-10
    • US12908140
    • 2010-10-20
    • Brian K. Kirkpatrick , Freidoon Mehrad , Shaofeng Yu
    • Brian K. Kirkpatrick , Freidoon Mehrad , Shaofeng Yu
    • H01L27/092 , H01L21/8238
    • H01L21/823842 , H01L29/513 , H01L29/66545 , H01L29/66553 , H01L29/6656
    • A method for fabricating a CMOS integrated circuit (IC) and ICs therefrom includes the steps of providing a substrate having a semiconductor surface, wherein the semiconductor surface has PMOS regions for PMOS devices and NMOS regions for NMOS devices. A gate dielectric layer is formed on the PMOS regions and NMOS regions. An original gate electrode layer is formed on the gate dielectric layer. A gate masking layer is applied on the gate electrode layer. Etching is used to pattern the original gate electrode layer to simultaneously form original gate electrodes for the PMOS devices and NMOS devices. Source and drain regions are formed for the PMOS devices and NMOS devices. The original gate electrodes are removed for at least one of the PMOS devices and NMOS devices to form trenches using an etch process, such as a hydroxide-based solution, wherein at least a portion and generally substantially all of the gate dielectric layer is preserved. A metal comprising replacement gates is formed in the trenches, and fabrication of the IC is completed.
    • 一种用于制造CMOS集成电路（IC）及其IC的方法包括提供具有半导体表面的衬底的步骤，其中半导体表面具有用于PMOS器件的PMOS区域和用于NMOS器件的NMOS区域。 栅极电介质层形成在PMOS区域和NMOS区域上。 在栅极电介质层上形成原始栅电极层。 栅极掩模层被施加在栅极电极层上。 蚀刻用于对原始栅极电极层进行图案化以同时形成用于PMOS器件和NMOS器件的原始栅电极。 为PMOS器件和NMOS器件形成源极和漏极区域。 为了至少一个PMOS器件和NMOS器件去除原始栅电极，以使用诸如基于氢氧化物的溶液的蚀刻工艺形成沟槽，其中保留了栅极电介质层的至少一部分和基本上全部的栅极电介质层。 在沟槽中形成包括置换栅极的金属，并且完成IC的制造。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 5. 发明授权
      US08372703B2 Gate dielectric first replacement gate processes and integrated circuits therefrom 有权
    • Gate dielectric first replacement gate processes and integrated circuits therefrom
    • 栅介质第一替代栅极工艺及其集成电路
    • US08372703B2
    • 2013-02-12
    • US12908140
    • 2010-10-20
    • Brian K. Kirkpatrick , Freidoon Mehrad , Shaofeng Yu
    • Brian K. Kirkpatrick , Freidoon Mehrad , Shaofeng Yu
    • H01L21/8238
    • H01L21/823842 , H01L29/513 , H01L29/66545 , H01L29/66553 , H01L29/6656
    • A method for fabricating a CMOS integrated circuit (IC) and ICs therefrom includes the steps of providing a substrate having a semiconductor surface, wherein the semiconductor surface has PMOS regions for PMOS devices and NMOS regions for NMOS devices. A gate dielectric layer is formed on the PMOS regions and NMOS regions. An original gate electrode layer is formed on the gate dielectric layer. A gate masking layer is applied on the gate electrode layer. Etching is used to pattern the original gate electrode layer to simultaneously form original gate electrodes for the PMOS devices and NMOS devices. Source and drain regions are formed for the PMOS devices and NMOS devices. The original gate electrodes are removed for at least one of the PMOS devices and NMOS devices to form trenches using an etch process, such as a hydroxide-based solution, wherein at least a portion and generally substantially all of the gate dielectric layer is preserved. A metal comprising replacement gates is formed in the trenches, and fabrication of the IC is completed.
    • 一种用于制造CMOS集成电路（IC）及其IC的方法包括提供具有半导体表面的衬底的步骤，其中半导体表面具有用于PMOS器件的PMOS区域和用于NMOS器件的NMOS区域。 栅极电介质层形成在PMOS区域和NMOS区域上。 在栅极电介质层上形成原始栅电极层。 栅极掩模层被施加在栅极电极层上。 蚀刻用于对原始栅极电极层进行图案化以同时形成用于PMOS器件和NMOS器件的原始栅电极。 为PMOS器件和NMOS器件形成源极和漏极区域。 为了至少一个PMOS器件和NMOS器件去除原始栅电极，以使用诸如基于氢氧化物的溶液的蚀刻工艺形成沟槽，其中保留了栅极电介质层的至少一部分和基本上全部的栅极电介质层。 在沟槽中形成包括置换栅极的金属，并且完成IC的制造。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 6. 发明授权
      US07943456B2 Selective wet etch process for CMOS ICs having embedded strain inducing regions and integrated circuits therefrom 有权
    • Selective wet etch process for CMOS ICs having embedded strain inducing regions and integrated circuits therefrom
    • 具有嵌入式应变诱导区域和集成电路的CMOS IC的选择性湿蚀刻工艺
    • US07943456B2
    • 2011-05-17
    • US12347173
    • 2008-12-31
    • Shaofeng Yu , Freidoon Mehrad , Brian K. Kirkpatrick
    • Shaofeng Yu , Freidoon Mehrad , Brian K. Kirkpatrick
    • H01L21/8238 , H01L29/80
    • H01L21/823807 , H01L21/823814 , H01L29/165 , H01L29/66628 , H01L29/66636 , H01L29/7848
    • A method for fabricating a CMOS integrated circuit (IC) and ICs therefrom includes providing a substrate having a semiconductor surface including PMOS regions for PMOS devices and NMOS regions for NMOS devices. A gate stack including a gate electrode layer is formed on a gate dielectric layer in or on both the PMOS regions and the NMOS regions. An n-type doping is used to create n-type wet etch sensitized regions on opposing sides of the gate stack in both the PMOS and said NMOS regions. Wet etching removes the n-type wet etch sensitized regions in (i) at least a portion of said PMOS regions to form a plurality of PMOS source/drain recesses or (ii) in at least a portion of said NMOS regions to form a plurality of NMOS source/drain recesses, or (i) and (ii). At least one of a compressive strain inducing epitaxial layer is formed in the plurality of PMOS source/drain recesses and a tensile strain inducing epitaxial layer is formed in the plurality of NMOS source/drain recesses. The fabrication of the IC is then completed.
    • 一种用于制造CMOS集成电路（IC）和其IC的方法包括提供具有包括用于PMOS器件的PMOS区域和NMOS器件的NMOS区域的半导体表面的衬底。 包括栅极电极层的栅极堆叠形成在PMOS区域和NMOS区域中的栅极电介质层中或栅极电介质层上。 使用n型掺杂来在PMOS和NMOS区域中的栅极堆叠的相对侧上产生n型湿法蚀刻增感区域。 湿式蚀刻去除在（i）所述PMOS区域的至少一部分中的n型湿法蚀刻增感区域以形成多个PMOS源极/漏极凹槽，或（ii）在所述NMOS区域的至少一部分中形成多个 的NMOS源/漏极凹槽，或（i）和（ii）。 至少一个压应变诱导外延层形成在多个PMOS源极/漏极凹槽中，并且在多个NMOS源极/漏极凹槽中形成拉伸应变诱发外延层。 然后完成IC的制造。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 9. 发明授权
      US07732284B1 Post high-k dielectric/metal gate clean 有权
    • Post high-k dielectric/metal gate clean
    • 后高k电介质/金属门清洁
    • US07732284B1
    • 2010-06-08
    • US12344421
    • 2008-12-26
    • Brian K. Kirkpatrick , Jinhan Choi , Deborah J. Riley
    • Brian K. Kirkpatrick , Jinhan Choi , Deborah J. Riley
    • H01L21/00
    • H01L21/02071 , H01L21/31111 , H01L29/517 , H01L29/78 , Y10S438/906
    • A method for fabricating a CMOS integrated circuit (IC) includes the step of providing a substrate having a semiconductor surface. A gate stack including a metal gate electrode on a metal including high-k dielectric layer is formed on the semiconductor surface. Dry etching is used to pattern the gate stack to define a patterned gate electrode stack having exposed sidewalls of the metal gate electrode. The dry etching forms post etch residuals some of which are deposited on the substrate. The substrate including the patterned gate electrode stack is exposed to a solution cleaning sequence including a first clean step including a first acid and a fluoride for removing at least a portion of the post etch residuals, wherein the first clean step has a high selectivity to avoid etching the exposed sidewalls of the metal gate electrode. A second clean after the first clean consists essentially of a fluoride which removes residual high-k material on the semiconductor surface.
    • 制造CMOS集成电路（IC）的方法包括提供具有半导体表面的衬底的步骤。 在半导体表面上形成包括金属栅电极在包含高k电介质层的金属上的栅叠层。 使用干蚀刻来图案化栅极堆叠以限定具有金属栅电极的暴露侧壁的图案化栅电极堆叠。 干蚀刻形成后蚀刻残留物，其中一些沉积在基底上。 包括图案化的栅极电极堆叠的衬底暴露于溶液清洁序列，其包括包括第一酸和氟化物的第一清洁步骤，用于去除至少一部分后蚀刻残留物，其中第一清洁步骤具有高选择性以避免 蚀刻金属栅电极的暴露的侧壁。 第一次清洁后的第二次清洁基本上由氟化物组成，其除去半导体表面上残留的高k材料。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
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