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1. 发明申请

US20130070969A1 METHOD AND SYSTEM FOR PEOPLE FLOW STATISTICS 有权
标题翻译：人流统计方法与系统
公开(公告)号：US20130070969A1
公开(公告)日：2013-03-21
申请号：US13578324
申请日：2010-02-10
申请人： Zhigang Hu , Yong Zhu , Ye Ren , Weiwei Cai , Yonghua Jia
发明人： Zhigang Hu , Yong Zhu , Ye Ren , Weiwei Cai , Yonghua Jia
IPC分类号： G06K9/00
CPC分类号： G06K9/00335 , G06K9/00248 , G06K9/00778 , G06K9/6282
摘要： A method and system for people flow statistics is disclosed in the invention, wherein said method comprises: multi-types of classifiers connected in parallel are used to perform the human head detection in the current image, the respective human heads in the current image are determined; the respective determined human heads are tracked to form the human head target movement tracks; and the people flow is counted at the direction of the human head target movement track. It can be seen, a plurality of classifiers connected in parallel are used in the invention, multi-types of human head targets, such as dark colored hair, light colored hair and caps of various colors, and the like, can be detected simultaneously.
摘要翻译：本发明公开了人流统计的方法和系统，其中所述方法包括：并行连接的多类分类器用于在当前图像中执行人头检测，确定当前图像中各个人头 ; 跟踪各自确定的人头以形成人头目标运动轨迹; 人流量按人头目标运动轨迹的方向计算。可以看出，在本发明中使用并联连接的多个分类器，可以同时检测多种类型的人头目标，例如深色头发，浅色头发和各种颜色的帽等。

2. 发明授权

US08798327B2 Method and system for people flow statistics 有权
标题翻译：人流统计方法与系统
公开(公告)号：US08798327B2
公开(公告)日：2014-08-05
申请号：US13578324
申请日：2010-02-10
申请人： Zhigang Hu , Yong Zhu , Ye Ren , Weiwei Cai , Yonghua Jia
发明人： Zhigang Hu , Yong Zhu , Ye Ren , Weiwei Cai , Yonghua Jia
IPC分类号： G06K9/00 , H04W4/00
CPC分类号： G06K9/00335 , G06K9/00248 , G06K9/00778 , G06K9/6282
摘要： A method and system for people flow statistics is disclosed in the invention, wherein said method comprises: multi-types of classifiers connected in parallel are used to perform the human head detection in the current image, the respective human heads in the current image are determined; the respective determined human heads are tracked to form the human head target movement tracks; and the people flow is counted at the direction of the human head target movement track. It can be seen, a plurality of classifiers connected in parallel are used in the invention, multi-types of human head targets, such as dark colored hair, light colored hair and caps of various colors, and the like, can be detected simultaneously.
摘要翻译：本发明公开了人流统计的方法和系统，其中所述方法包括：并行连接的多类分类器用于在当前图像中执行人头检测，确定当前图像中各个人头 ; 跟踪各自确定的人头以形成人头目标运动轨迹; 人流量按人头目标运动轨迹的方向计算。可以看出，在本发明中使用并联连接的多个分类器，可以同时检测多种类型的人头目标，例如深色头发，浅色头发和各种颜色的帽等。

3. 发明申请

US20090013207A1 PREDICTING MICROPROCESSOR LIFETIME RELIABILITY USING ARCHITECTURE-LEVEL STRUCTURE-AWARE TECHNIQUES 审中-公开
标题翻译：使用建筑级结构技术预测微处理器的寿命可靠性
公开(公告)号：US20090013207A1
公开(公告)日：2009-01-08
申请号：US12189416
申请日：2008-08-11
申请人： Pradip Bose , Zhigang Hu , Jude A. Rivers , Jeonghee Shin , Victor Zyuban
发明人： Pradip Bose , Zhigang Hu , Jude A. Rivers , Jeonghee Shin , Victor Zyuban
IPC分类号： G06F11/00
CPC分类号： G06F11/008
摘要： A method of predicting the lifetime reliability of an integrated circuit device with respect to one or more failure mechanisms includes breaking down the integrated circuit device into structures; breaking down each structure into elements and devices; evaluating each device to determine whether the device is vulnerable to the failure mechanisms and eliminating devices determined not to be vulnerable; estimating, for each determined vulnerable device, the impact of a failure of the device on the functionality of the specific element associated therewith, and classifying the failure into a fatal failure or a non-fatal failure, wherein a fatal failure causes the element employing the given device to fail; determining, for those devices whose failures are fatal, an effective stress degree and/or time; determining one or more of a failure rate and a probability of fatal failure for the devices, and aggregating the same across the structures and the failure mechanisms.
摘要翻译：一种预测集成电路器件相对于一个或多个故障机制的寿命可靠性的方法包括将集成电路器件分解成结构; 将每个结构分解成元素和设备; 评估每个设备以确定设备是否容易受到故障机制的影响，并消除确定不易受到攻击的设备; 对于每个确定的易受攻击的设备，估计设备故障对与其相关联的特定元件的功能的影响，以及将故障分类为致命故障或非致命故障，其中致命故障导致使用给定设备失败; 确定对于那些故障致命的设备，有效的应力程度和/或时间; 确定设备的故障率和致命故障的概率中的一个或多个，并且在整个结构和故障机制中聚合它们。

4. 发明申请

US20060041769A1 Method and apparatus for reducing leakage power in a cache memory using adaptive time-based decay 有权
公开(公告)号：US20060041769A1
公开(公告)日：2006-02-23
申请号：US11245513
申请日：2005-10-07
申请人： Zhigang Hu , Stefanos Kaxiras , Margaret Martonosi
发明人： Zhigang Hu , Stefanos Kaxiras , Margaret Martonosi
IPC分类号： G06F1/30
CPC分类号： G11C5/143 , G11C11/417
摘要： An adaptive cache decay technique is disclosed that removes power from cache lines that have not been accessed for a variable time interval, referred to as the cache line decay interval, assuming that these cache lines are unlikely to be accessed in the future. The decay interval may be increased or decreased for each cache line to increase cache performance or save power, respectively. A default decay interval is initially established for the cache and the default decay interval may then be adjusted for a given cache line based on the performance of the cache line following a cache decay. The cache decay performance is evaluated by determining if a cache line was decayed too quickly. If a cache line is decayed and the same cache contents are again required, then the cache line was decayed too quickly and the cache line decay interval is increased. If a cache line is decayed and the cache line is then accessed to obtain a different cache content, the cache line decay interval can be decreased. When a cache line is later accessed after being decayed, a cache miss is incurred and a test is performed to evaluate the cache decay performance by determining if the same cache contents are again accessed (e.g., whether the address associated with a subsequent access is the same address of the previously stored contents). The cache decay interval is then adjusted accordingly.

5. 发明授权

US07921331B2 Write filter cache method and apparatus for protecting the microprocessor core from soft errors 有权
标题翻译：用于保护微处理器内核免受软错误的写入过滤器高速缓存方法和装置
公开(公告)号：US07921331B2
公开(公告)日：2011-04-05
申请号：US12138099
申请日：2008-06-12
申请人： Pradip Bose , Zhigang Hu , Xiaodong Li , Jude A. Rivers
发明人： Pradip Bose , Zhigang Hu , Xiaodong Li , Jude A. Rivers
IPC分类号： G06F11/00 , G06F11/08
CPC分类号： G06F12/0804 , G06F11/1497 , G06F2212/1032
摘要： A write filter cache system for protecting a microprocessor core from soft errors and method thereof are provided. In one aspect, data coming from a processor core to be written in primary cache memory, for instance, L1 cache memory system, is buffered in a write filter cache placed between the primary cache memory and the processor core. The data from the write filter is move to the main cache memory only if it is verified that main thread's data is soft error free, for instance, by comparing the main thread's data with that of its redundant thread. The main cache memory only keeps clean data associated with accepted checkpoints.
摘要翻译：提供了一种用于保护微处理器内核免受软错误的写过滤器高速缓存系统及其方法。在一个方面，来自处理器核心的要写入主高速缓存存储器（例如，L1高速缓存存储器系统）的数据被缓存在放置在主高速缓冲存储器和处理器核心之间的写入过滤器高速缓存中。只有在验证主线程的数据是软错误的情况下，例如通过将主线程的数据与其冗余线程的数据进行比较，才能将写入过滤器的数据移动到主缓存器。主缓存只保留与接受检查点关联的干净数据。

6. 发明申请

US20090089602A1 METHOD AND SYSTEM OF PEAK POWER ENFORCEMENT VIA AUTONOMOUS TOKEN-BASED CONTROL AND MANAGEMENT 有权
标题翻译：通过自动基于方法的控制和管理，峰值功率执行的方法和系统
公开(公告)号：US20090089602A1
公开(公告)日：2009-04-02
申请号：US11862559
申请日：2007-09-27
申请人： Pradip Bose , Alper Buyuktosunoglu , Chen-Yong Cher , Zhigang Hu , Hans Jacobson , Prabhakar N. Kudva , Vijayalakshmi Srinivasan , Victor Zyuban
发明人： Pradip Bose , Alper Buyuktosunoglu , Chen-Yong Cher , Zhigang Hu , Hans Jacobson , Prabhakar N. Kudva , Vijayalakshmi Srinivasan , Victor Zyuban
IPC分类号： G06F1/28
CPC分类号： G06F1/3287 , G06F1/206 , G06F9/3836 , G06F9/3869 , G06F9/5094 , Y02D10/16 , Y02D10/171 , Y02D10/22 , Y02D50/20
摘要： A method of power management of a system of connected components includes initializing a token allocation map across the connected components, wherein each component is assigned a power budget as determined by a number of allocated tokens in the token allocation map, monitoring utilization sensor inputs and command state vector inputs, determining, at first periodic time intervals, a current performance level, a current power consumption level and an assigned power budget for the system based on the utilization sensor inputs and the command state vector inputs, and determining, at second periodic time intervals, a token re-allocation map based on the current performance level, the current power consumption level and the assigned power budget for the system, according to a re-assigned power budget of at least one of the connected components, while enforcing a power consumption limit based on a total number of allocated tokens in the system.
摘要翻译：一种连接组件的系统的电源管理方法包括：在所连接的组件之间初始化令牌分配映射，其中每个组件被分配由令牌分配映射中的分配的令牌数量确定的功率预算，监视利用率传感器输入和命令状态向量输入，基于所述利用传感器输入和所述命令状态向量输入，以第一周期性时间间隔确定所述系统的当前性能水平，当前功耗级别和所分配的功率预算，以及在所述第二周期时间间隔，基于当前性能水平的令牌重新分配图，当前功耗水平和系统的分配的功率预算，根据至少一个连接的组件的重新分配的功率预算，同时执行功率基于系统中分配的令牌总数的消耗限制。

7. 发明申请

US20080313407A1 LATENCY-AWARE REPLACEMENT SYSTEM AND METHOD FOR CACHE MEMORIES 审中-公开
标题翻译：用于高速缓存存储器的更新代替系统和方法
公开(公告)号：US20080313407A1
公开(公告)日：2008-12-18
申请号：US11762358
申请日：2007-06-13
申请人： Zhigang Hu , William Robert Reohr
发明人： Zhigang Hu , William Robert Reohr
IPC分类号： G06F13/00
CPC分类号： G06F12/127 , G06F12/0811 , G06F12/084 , G06F12/0864 , G06F2212/271
摘要： A method for replacing cache lines in a computer system having a non-uniform set associative cache memory is disclosed. The method incorporates access latency as an additional factor into the existing ranking guidelines for replacement of a line, the higher the rank of the line the sooner that it is likely to be evicted from the cache. Among a group of highest ranking cache lines in a cache set, the cache line chosen to be replaced is one that provides the lowest latency access to a requesting entity, such as a processor. The distance separating the requesting entity from the memory partition where the cache line is stored most affects access latency.
摘要翻译：公开了一种用于替换具有非均匀集合关联高速缓冲存储器的计算机系统中的高速缓存行的方法。该方法将访问延迟作为替代线路的现有排名指南的附加因素，该行的排名越高，越可能从缓存中逐出。在缓存集中的一组最高排名的高速缓存行中，选择要替换的高速缓存行是为请求实体（例如处理器）提供最低延迟访问的高速缓存行。将请求实体与存储高速缓存行存储的内存分区分开的距离最大程度上影响访问延迟。

8. 发明申请

US20080126771A1 Branch Target Extension for an Instruction Cache 审中-公开
标题翻译：指令缓存的分支目标扩展
公开(公告)号：US20080126771A1
公开(公告)日：2008-05-29
申请号：US11459683
申请日：2006-07-25
申请人： Lei Chen , Zhigang Hu , Lixin Zhang
发明人： Lei Chen , Zhigang Hu , Lixin Zhang
IPC分类号： G06F9/38
CPC分类号： G06F9/3844 , G06F9/3806 , G06F9/3814
摘要： An instruction cache (I-Cache) for a processor is configured to include a Branch Target Extension associated with each Instruction Sector. When an Instruction Sector is fetched, the Branch Target Extension is simultaneously fetched. If the Instruction Sector has a branch instruction that is predicted taken, then the branch target address in the branch extension is used to access the next Instruction Sector. In other embodiments, each Instruction Sector has a plurality of Branch Target Extensions each corresponding to a potential branch instruction in an Instruction Sector. In this case, the Branch Target Extensions are partitioned into an instruction index field for locating branch instruction in the Instruction Sector, a local predictor field for predicted taken status and a target address field for the branch target address. The least significant bits of the instruction fetch address are compared to the instruction indexes to determine a particular Branch Target Extension to use.
摘要翻译：用于处理器的指令高速缓存（I-Cache）被配置为包括与每个指令扇区相关联的分支目标扩展。当获取指令扇区时，同时提取分支目标扩展。如果指令扇区具有预测的分支指令，则分支扩展中的分支目标地址用于访问下一个指令扇区。在其他实施例中，每个指令扇区具有多个分支目标扩展，每个分支目标扩展对应于指令扇区中的潜在分支指令。在这种情况下，分支目标扩展被划分为用于定位指令扇区中的分支指令的指令索引字段，用于预测采用状态的本地预测器字段和用于分支目标地址的目标地址字段。将指令提取地址的最低有效位与指令索引进行比较，以确定要使用的特定分支目标扩展。

9. 发明申请

US20060041720A1 Latency-aware replacement system and method for cache memories 有权
标题翻译：延迟感知替换系统和缓存存储器的方法
公开(公告)号：US20060041720A1
公开(公告)日：2006-02-23
申请号：US10920844
申请日：2004-08-18
申请人： Zhigang Hu , William Reohr
发明人： Zhigang Hu , William Reohr
IPC分类号： G06F12/00
CPC分类号： G06F12/0811 , G06F12/0864 , G06F12/0897 , G06F12/127 , G06F2212/271
摘要： A method for replacing cache lines in a computer system having a non-uniform set associative cache memory is disclosed. The method incorporates access latency as an additional factor into the existing ranking guidelines for replacement of a line, the higher the rank of the line the sooner that it is likely to be evicted from the cache. Among a group of highest ranking cache lines in a cache set, the cache line chosen to be replaced is one that provides the lowest latency access to a requesting entity, such as a processor. The distance separating the requesting entity from the memory partition where the cache line is stored most affects access latency.
摘要翻译：公开了一种用于替换具有非均匀集合关联高速缓冲存储器的计算机系统中的高速缓存行的方法。该方法将访问延迟作为替代线路的现有排名指南的附加因素，该行的排名越高，越可能从缓存中逐出。在缓存集中的一组最高排名的高速缓存行中，选择要替换的高速缓存行是为请求实体（例如处理器）提供最低延迟访问的高速缓存行。将请求实体与存储高速缓存行存储的内存分区分开的距离最大程度上影响访问延迟。

10. 发明授权

US07472302B2 Method and apparatus for reducing leakage power in a cache memory using adaptive time-based decay 有权
标题翻译：使用自适应基于时间的衰减来减少高速缓冲存储器中的泄漏功率的方法和装置
公开(公告)号：US07472302B2
公开(公告)日：2008-12-30
申请号：US11245513
申请日：2005-10-07
申请人： Zhigang Hu , Stefanos Kaxiras , Margaret Martonosi
发明人： Zhigang Hu , Stefanos Kaxiras , Margaret Martonosi
IPC分类号： G06F1/32
CPC分类号： G11C5/143 , G11C11/417
摘要： An adaptive cache decay technique is disclosed that removes power from cache lines that have not been accessed for a variable time interval, referred to as the cache line decay interval, assuming that these cache lines are unlikely to be accessed in the future. The decay interval may be increased or decreased for each cache line to increase cache performance or save power, respectively. A default decay interval is initially established for the cache and the default decay interval may then be adjusted for a given cache line based on the performance of the cache line following a cache decay. The cache decay performance is evaluated by determining if a cache line was decayed too quickly. If a cache line is decayed and the same cache contents are again required, then the cache line was decayed too quickly and the cache line decay interval is increased. If a cache line is decayed and the cache line is then accessed to obtain a different cache content, the cache line decay interval can be decreased. When a cache line is later accessed after being decayed, a cache miss is incurred and a test is performed to evaluate the cache decay performance by determining if the same cache contents are again accessed (e.g., whether the address associated with a subsequent access is the same address of the previously stored contents). The cache decay interval is then adjusted accordingly.
摘要翻译：公开了一种自适应高速缓存衰减技术，其假设在将来不太可能访问这些高速缓存线，从而将高速缓存线路的功率从尚未被访问的可变时间间隔（称为高速缓存行衰减间隔）中移除。对于每个高速缓存线，衰减间隔可以增加或减小，以分别提高高速缓存性能或节省功率。初始建立高速缓存的默认衰减间隔，然后可以根据高速缓存衰减之后的高速缓存行的性能，为给定的高速缓存行调整默认衰减间隔。缓存衰减性能通过确定高速缓存行是否衰减太快来进行评估。如果缓存线被衰减并且再次需要相同的高速缓存内容，则高速缓存线被衰减太快，并且高速缓存行衰减间隔增加。如果缓存行被衰减并且然后访问高速缓存行以获得不同的高速缓存内容，则可以减少高速缓存行衰减间隔。当高速缓存行在衰减之后被访问时，产生高速缓存未命中，并且执行测试以通过确定是否再次访问相同的缓存内容来评估高速缓存衰减性能（例如，与后续访问相关联的地址是否为以前存储的内容的相同地址）。然后相应地调整缓存衰减间隔。

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