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1. 发明申请

US20090089602A1 METHOD AND SYSTEM OF PEAK POWER ENFORCEMENT VIA AUTONOMOUS TOKEN-BASED CONTROL AND MANAGEMENT 有权
标题翻译：通过自动基于方法的控制和管理，峰值功率执行的方法和系统
公开(公告)号：US20090089602A1
公开(公告)日：2009-04-02
申请号：US11862559
申请日：2007-09-27
申请人： Pradip Bose , Alper Buyuktosunoglu , Chen-Yong Cher , Zhigang Hu , Hans Jacobson , Prabhakar N. Kudva , Vijayalakshmi Srinivasan , Victor Zyuban
发明人： Pradip Bose , Alper Buyuktosunoglu , Chen-Yong Cher , Zhigang Hu , Hans Jacobson , Prabhakar N. Kudva , Vijayalakshmi Srinivasan , Victor Zyuban
IPC分类号： G06F1/28
CPC分类号： G06F1/3287 , G06F1/206 , G06F9/3836 , G06F9/3869 , G06F9/5094 , Y02D10/16 , Y02D10/171 , Y02D10/22 , Y02D50/20
摘要： A method of power management of a system of connected components includes initializing a token allocation map across the connected components, wherein each component is assigned a power budget as determined by a number of allocated tokens in the token allocation map, monitoring utilization sensor inputs and command state vector inputs, determining, at first periodic time intervals, a current performance level, a current power consumption level and an assigned power budget for the system based on the utilization sensor inputs and the command state vector inputs, and determining, at second periodic time intervals, a token re-allocation map based on the current performance level, the current power consumption level and the assigned power budget for the system, according to a re-assigned power budget of at least one of the connected components, while enforcing a power consumption limit based on a total number of allocated tokens in the system.
摘要翻译：一种连接组件的系统的电源管理方法包括：在所连接的组件之间初始化令牌分配映射，其中每个组件被分配由令牌分配映射中的分配的令牌数量确定的功率预算，监视利用率传感器输入和命令状态向量输入，基于所述利用传感器输入和所述命令状态向量输入，以第一周期性时间间隔确定所述系统的当前性能水平，当前功耗级别和所分配的功率预算，以及在所述第二周期时间间隔，基于当前性能水平的令牌重新分配图，当前功耗水平和系统的分配的功率预算，根据至少一个连接的组件的重新分配的功率预算，同时执行功率基于系统中分配的令牌总数的消耗限制。

2. 发明授权

US07930578B2 Method and system of peak power enforcement via autonomous token-based control and management 有权
标题翻译：通过自主的基于令牌的控制和管理来实现峰值功率的方法和系统
公开(公告)号：US07930578B2
公开(公告)日：2011-04-19
申请号：US11862559
申请日：2007-09-27
申请人： Pradip Bose , Alper Buyuktosunoglu , Chen-Yong Cher , Zhigang Hu , Hans Jacobson , Prabhakar N. Kudva , Vijayalakshmi Srinivasan , Victor Zyuban
发明人： Pradip Bose , Alper Buyuktosunoglu , Chen-Yong Cher , Zhigang Hu , Hans Jacobson , Prabhakar N. Kudva , Vijayalakshmi Srinivasan , Victor Zyuban
IPC分类号： G06F1/00 , G06F11/30 , G06F1/26 , G06F1/32
CPC分类号： G06F1/3287 , G06F1/206 , G06F9/3836 , G06F9/3869 , G06F9/5094 , Y02D10/16 , Y02D10/171 , Y02D10/22 , Y02D50/20
摘要： A method of power management of a system of connected components includes initializing a token allocation map across the connected components, wherein each component is assigned a power budget as determined by a number of allocated tokens in the token allocation map, monitoring utilization sensor inputs and command state vector inputs, determining, at first periodic time intervals, a current performance level, a current power consumption level and an assigned power budget for the system based on the utilization sensor inputs and the command state vector inputs, and determining, at second periodic time intervals, a token re-allocation map based on the current performance level, the current power consumption level and the assigned power budget for the system, according to a re-assigned power budget of at least one of the connected components, while enforcing a power consumption limit based on a total number of allocated tokens in the system.
摘要翻译：一种连接组件的系统的电源管理方法包括：在所连接的组件之间初始化令牌分配映射，其中每个组件被分配由令牌分配映射中的分配的令牌数量确定的功率预算，监视利用率传感器输入和命令状态向量输入，基于所述利用传感器输入和所述命令状态向量输入，以第一周期性时间间隔确定所述系统的当前性能水平，当前功耗级别和所分配的功率预算，以及在所述第二周期时间间隔，基于当前性能水平的令牌重新分配图，当前功耗水平和系统的分配的功率预算，根据至少一个连接的组件的重新分配的功率预算，同时执行功率基于系统中分配的令牌总数的消耗限制。

3. 发明申请

US20070043960A1 Systems and methods for mutually exclusive activation of microprocessor resources to control maximum power 失效
标题翻译：用于互相激活微处理器资源以控制最大功率的系统和方法
公开(公告)号：US20070043960A1
公开(公告)日：2007-02-22
申请号：US11207333
申请日：2005-08-19
申请人： Pradip Bose , Alper Buyuktosunoglu , Zhigang Hu , Hans Jacobson , Vijayalakshmi Srinivasan , Victor Zyuban
发明人： Pradip Bose , Alper Buyuktosunoglu , Zhigang Hu , Hans Jacobson , Vijayalakshmi Srinivasan , Victor Zyuban
IPC分类号： G06F1/00
CPC分类号： G06F1/3203 , G06F1/3287 , G06F1/329 , G06F9/30145 , G06F9/382 , G06F9/3836 , G06F9/3842 , G06F9/3867 , Y02D10/171 , Y02D10/24
摘要： A device for controlling power parameters in a microprocessor includes a resource activation control unit for controlling the maximum power of the microprocessor and two or more resources. The resource activation control unit controls the activation of the resources such that the consumed and dissipated power of the microprocessor does not exceed a power bound which is configurable to a predetermined value below the maximum power.
摘要翻译：用于控制微处理器中的功率参数的装置包括用于控制微处理器的最大功率和两个或更多个资源的资源激活控制单元。资源激活控制单元控制资源的激活，使得微处理器的消耗和耗散功率不超过可配置为低于最大功率的预定值的功率限制。

4. 发明授权

US07447923B2 Systems and methods for mutually exclusive activation of microprocessor resources to control maximum power 失效
标题翻译：用于互相激活微处理器资源以控制最大功率的系统和方法
公开(公告)号：US07447923B2
公开(公告)日：2008-11-04
申请号：US11207333
申请日：2005-08-19
申请人： Pradip Bose , Alper Buyuktosunoglu , Zhigang Hu , Hans Mikael Jacobson , Vijayalakshmi Srinivasan , Victor Zyuban
发明人： Pradip Bose , Alper Buyuktosunoglu , Zhigang Hu , Hans Mikael Jacobson , Vijayalakshmi Srinivasan , Victor Zyuban
IPC分类号： G06F1/00 , G06F1/26 , G06F1/32
CPC分类号： G06F1/3203 , G06F1/3287 , G06F1/329 , G06F9/30145 , G06F9/382 , G06F9/3836 , G06F9/3842 , G06F9/3867 , Y02D10/171 , Y02D10/24
摘要： A device for controlling power parameters in a microprocessor includes a resource activation control unit for controlling the maximum power of the microprocessor and two or more resources. The resource activation control unit controls the activation of the resources such that the consumed and dissipated power of the microprocessor does not exceed a power bound which is configurable to a predetermined value below the maximum power.
摘要翻译：用于控制微处理器中的功率参数的装置包括用于控制微处理器的最大功率和两个或更多个资源的资源激活控制单元。资源激活控制单元控制资源的激活，使得微处理器的消耗和耗散功率不超过可配置为低于最大功率的预定值的功率限制。

5. 发明授权

US08458501B2 Measuring data switching activity in a microprocessor 失效
标题翻译：测量微处理器中的数据交换活动
公开(公告)号：US08458501B2
公开(公告)日：2013-06-04
申请号：US12844372
申请日：2010-07-27
申请人： Pradip Bose , Alper Buyuktosunoglu , Christopher J. Gonzalez , Moinuddin K. Qureshi , Victor Zyuban
发明人： Pradip Bose , Alper Buyuktosunoglu , Christopher J. Gonzalez , Moinuddin K. Qureshi , Victor Zyuban
IPC分类号： G06F1/32 , G06F3/00
CPC分类号： G06F1/3206 , G06F1/324 , G06F1/3296 , Y02D10/126
摘要： A mechanism is provided for approximating data switching activity in a data processing system. A data switching activity identification mechanism in the data processing system receives an identification of a set of data storage devices and a set of bits in the set of data storage devices in the data processing system to be monitored for the data switching activity. The data switching activity identification mechanism sums a count of the identified bits that have changed state for the data storage device along with other counts of the identified bits that have changed state for other data storage devices in the set of data storage devices to form an approximation of data switching activity. A power manager in the data processing system then adjusts a set of operational parameters associated with the data processing system using the approximation of data switching activity.
摘要翻译：提供了一种用于近似数据处理系统中的数据交换活动的机制。数据处理系统中的数据交换活动识别机制在数据处理系统中接收数据存储设备的集合的标识和数据存储设备中的一组位，以对数据交换活动进行监控。数据交换活动识别机制对数据存储装置的已改变状态的已识别比特的计数与数据存储装置中的其他数据存储装置的已改变状态的识别比特的其他计数相加以形成近似值的数据交换活动。数据处理系统中的电源管理器然后使用数据交换活动的近似来调整与数据处理系统相关联的一组操作参数。

6. 发明申请

US20120030481A1 Measuring Data Switching Activity in a Microprocessor 失效
标题翻译：测量微处理器中的数据切换活动
公开(公告)号：US20120030481A1
公开(公告)日：2012-02-02
申请号：US12844372
申请日：2010-07-27
申请人： Pradip Bose , Alper Buyuktosunoglu , Christopher J. Gonzalez , Moinuddin K. Qureshi , Victor Zyuban
发明人： Pradip Bose , Alper Buyuktosunoglu , Christopher J. Gonzalez , Moinuddin K. Qureshi , Victor Zyuban
IPC分类号： G06F1/26
CPC分类号： G06F1/3206 , G06F1/324 , G06F1/3296 , Y02D10/126
摘要： A mechanism is provided for approximating data switching activity in a data processing system. A data switching activity identification mechanism in the data processing system receives an identification of a set of data storage devices and a set of bits in the set of data storage devices in the data processing system to be monitored for the data switching activity. The data switching activity identification mechanism sums a count of the identified bits that have changed state for the data storage device along with other counts of the identified bits that have changed state for other data storage devices in the set of data storage devices to form an approximation of data switching activity. A power manager in the data processing system then adjusts a set of operational parameters associated with the data processing system using the approximation of data switching activity.
摘要翻译：提供了一种用于近似数据处理系统中的数据交换活动的机制。数据处理系统中的数据交换活动识别机制在数据处理系统中接收数据存储设备的集合的标识和数据存储设备中的一组位，以对数据交换活动进行监控。数据交换活动识别机制对数据存储装置的已改变状态的已识别比特的计数与数据存储装置中的其他数据存储装置的已改变状态的识别比特的其他计数相加以形成近似值的数据交换活动。数据处理系统中的电源管理器然后使用数据交换活动的近似来调整与数据处理系统相关联的一组操作参数。

7. 发明申请

US20090013207A1 PREDICTING MICROPROCESSOR LIFETIME RELIABILITY USING ARCHITECTURE-LEVEL STRUCTURE-AWARE TECHNIQUES 审中-公开
标题翻译：使用建筑级结构技术预测微处理器的寿命可靠性
公开(公告)号：US20090013207A1
公开(公告)日：2009-01-08
申请号：US12189416
申请日：2008-08-11
申请人： Pradip Bose , Zhigang Hu , Jude A. Rivers , Jeonghee Shin , Victor Zyuban
发明人： Pradip Bose , Zhigang Hu , Jude A. Rivers , Jeonghee Shin , Victor Zyuban
IPC分类号： G06F11/00
CPC分类号： G06F11/008
摘要： A method of predicting the lifetime reliability of an integrated circuit device with respect to one or more failure mechanisms includes breaking down the integrated circuit device into structures; breaking down each structure into elements and devices; evaluating each device to determine whether the device is vulnerable to the failure mechanisms and eliminating devices determined not to be vulnerable; estimating, for each determined vulnerable device, the impact of a failure of the device on the functionality of the specific element associated therewith, and classifying the failure into a fatal failure or a non-fatal failure, wherein a fatal failure causes the element employing the given device to fail; determining, for those devices whose failures are fatal, an effective stress degree and/or time; determining one or more of a failure rate and a probability of fatal failure for the devices, and aggregating the same across the structures and the failure mechanisms.
摘要翻译：一种预测集成电路器件相对于一个或多个故障机制的寿命可靠性的方法包括将集成电路器件分解成结构; 将每个结构分解成元素和设备; 评估每个设备以确定设备是否容易受到故障机制的影响，并消除确定不易受到攻击的设备; 对于每个确定的易受攻击的设备，估计设备故障对与其相关联的特定元件的功能的影响，以及将故障分类为致命故障或非致命故障，其中致命故障导致使用给定设备失败; 确定对于那些故障致命的设备，有效的应力程度和/或时间; 确定设备的故障率和致命故障的概率中的一个或多个，并且在整个结构和故障机制中聚合它们。

8. 发明授权

US07472038B2 Method of predicting microprocessor lifetime reliability using architecture-level structure-aware techniques 失效
标题翻译：使用架构级结构感知技术预测微处理器使用寿命可靠性的方法
公开(公告)号：US07472038B2
公开(公告)日：2008-12-30
申请号：US11735533
申请日：2007-04-16
申请人： Pradip Bose , Zhigang Hu , Jude A. Rivers , Jeonghee Shin , Victor Zyuban
发明人： Pradip Bose , Zhigang Hu , Jude A. Rivers , Jeonghee Shin , Victor Zyuban
IPC分类号： G06F11/30 , G06F15/00 , G21C17/00
CPC分类号： G06F11/008
摘要： A method of predicting the lifetime reliability of an integrated circuit device with respect to one or more failure mechanisms includes breaking down the integrated circuit device into structures; breaking down each structure into elements and devices; evaluating each device to determine whether the device is vulnerable to the failure mechanisms and eliminating devices determined not to be vulnerable; estimating, for each determined vulnerable device, the impact of a failure of the device on the functionality of the specific element associated therewith, and classifying the failure into a fatal failure or a non-fatal failure, wherein a fatal failure causes the element employing the given device to fail; determining, for those devices whose failures are fatal, an effective stress degree and/or time; determining one or more of a failure rate and a probability of fatal failure for the devices, and aggregating the same across the structures and the failure mechanisms.
摘要翻译：一种预测集成电路器件相对于一个或多个故障机制的寿命可靠性的方法包括将集成电路器件分解成结构; 将每个结构分解成元素和设备; 评估每个设备以确定设备是否容易受到故障机制的影响，并消除确定不易受到攻击的设备; 对于每个确定的易受攻击的设备，估计设备故障对与其相关联的特定元件的功能的影响，以及将故障分类为致命故障或非致命故障，其中致命故障导致使用给定设备失败; 确定对于那些故障致命的设备，有效的应力程度和/或时间; 确定设备的故障率和致命故障的概率中的一个或多个，并且在整个结构和故障机制中聚合它们。

9. 发明申请

US20080256383A1 METHOD AND SYSTEM OF PREDICTING MICROPROCESSOR LIFETIME 失效
标题翻译：预测微生物生物利用度的方法与系统
公开(公告)号：US20080256383A1
公开(公告)日：2008-10-16
申请号：US11735533
申请日：2007-04-16
申请人： Pradip Bose , Zhigang Hu , Jude A. Rivers , Jeonghee Shin , Victor Zyuban
发明人： Pradip Bose , Zhigang Hu , Jude A. Rivers , Jeonghee Shin , Victor Zyuban
IPC分类号： G06F11/00
CPC分类号： G06F11/008
摘要： A method of predicting the lifetime reliability of an integrated circuit device with respect to one or more failure mechanisms includes breaking down the integrated circuit device into structures; breaking down each structure into elements and devices; evaluating each device to determine whether the device is vulnerable to the failure mechanisms and eliminating devices determined not to be vulnerable; estimating, for each determined vulnerable device, the impact of a failure of the device on the functionality of the specific element associated therewith, and classifying the failure into a fatal failure or a non-fatal failure, wherein a fatal failure causes the element employing the given device to fail; determining, for those devices whose failures are fatal, an effective stress degree and/or time; determining one or more of a failure rate and a probability of fatal failure for the devices, and aggregating the same across the structures and the failure mechanisms.
摘要翻译：一种预测集成电路器件相对于一个或多个故障机制的寿命可靠性的方法包括将集成电路器件分解成结构; 将每个结构分解成元素和设备; 评估每个设备以确定设备是否容易受到故障机制的影响，并消除确定不易受到攻击的设备; 对于每个确定的易受攻击的设备，估计设备故障对与其相关联的特定元件的功能的影响，以及将故障分类为致命故障或非致命故障，其中致命故障导致使用给定设备失败; 确定对于那些故障致命的设备，有效的应力程度和/或时间; 确定设备的故障率和致命故障的概率中的一个或多个，并且在整个结构和故障机制中聚合它们。

10. 发明申请

US20070220366A1 Method and apparatus for preventing soft error accumulation in register arrays 失效
标题翻译：用于防止寄存器阵列中软错误累积的方法和装置
公开(公告)号：US20070220366A1
公开(公告)日：2007-09-20
申请号：US11374871
申请日：2006-03-14
申请人： Pradip Bose , Jude Rivers , Balaram Sinharoy , Victor Zyuban
发明人： Pradip Bose , Jude Rivers , Balaram Sinharoy , Victor Zyuban
IPC分类号： G06F11/00
CPC分类号： G06F11/004 , G06F11/3409 , G06F2201/88
摘要： A computer implemented method, apparatus, and computer usable program code for preventing soft error accumulation. A number of cycles between references to a register are counted. Instructions are injected that reference the register for preventing soft error accumulation in response to a determination that the number of cycles is greater than a threshold.
摘要翻译：一种用于防止软错误累积的计算机实现的方法，装置和计算机可用程序代码。对寄存器的引用之间的一些周期进行计数。针对响应于循环数大于阈值的确定，注入参考寄存器以防止软错误累积的指令。

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