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1. 发明授权

US07683670B2 High-speed low-power integrated circuit interconnects 失效
标题翻译：高速低功耗集成电路互连
公开(公告)号：US07683670B2
公开(公告)日：2010-03-23
申请号：US11421457
申请日：2006-05-31
申请人： Zhibin Cheng , Satyajit Dutta , Peter J. Klim
发明人： Zhibin Cheng , Satyajit Dutta , Peter J. Klim
IPC分类号： H03K19/0175 , H03K19/094
CPC分类号： H03K19/018585 , H03K19/0013
摘要： Embodiments that decrease power consumption of interconnecting devices in integrated circuits are disclosed. Embodiments reduce power consumption in integrated circuits by generating full and reduced swing signals at an output of a driver module in response to a control signal during and deactivating one or more elements to conserve power after an input signal remains unchanged for a period of time. Another embodiment reduces power consumption in a circuit, the embodiment comprising a swing module coupled with a swing selector and an output controller. The swing module may generate full or low swing signals depending on the state of the swing selector. The output controller may increase the output impedance of the swing module after an input signal to the swing module remains unchanged for a quantity of time. Various apparatus embodiments include portable computing devices and cellular telephones.
摘要翻译：公开了降低集成电路中互连装置的功耗的实施例。实施例通过在驱动器模块的输出处响应于在一个或多个元件期间的控制信号并且在输入信号保持不变一段时间之后节省功率而在驱动器模块的输出处产生完全和减小的摆动信号来降低集成电路中的功耗。另一个实施例降低了电路中的功耗，该实施例包括与摆动选择器和输出控制器耦合的摆动模块。摆动模块可以根据摆动选择器的状态产生满摆幅或低摆动信号。输出控制器可以在摆动模块的输入信号保持不变一段时间之后增加摆动模块的输出阻抗。各种设备实施例包括便携式计算设备和蜂窝电话。

2. 发明申请

US20080123458A1 VIRTUAL POWER RAILS FOR INTEGRATED CIRCUITS 有权
标题翻译：用于集成电路的虚拟功率轨
公开(公告)号：US20080123458A1
公开(公告)日：2008-05-29
申请号：US11458616
申请日：2006-07-19
申请人： Zhibin Cheng , Satyajit Dutta , Peter J. Klim
发明人： Zhibin Cheng , Satyajit Dutta , Peter J. Klim
IPC分类号： G11C5/14 , G05F3/02
CPC分类号： G11C5/063 , G11C11/413
摘要： Methods and apparatuses to decrease power consumption and reduce leakage current of integrated circuits are disclosed. New leakage power saving techniques for various types of integrated circuits, including cache memory circuits, are discussed. Embodiments comprise methods and apparatuses to reduce power consumption in integrated circuits by using virtual voltage rails, or virtual power rails, to supply power to integrated circuit loads. The methods and apparatuses generally involve using one or two virtual power control devices to “head” and “foot”, or sandwich, the integrated circuit loads from firm power supply rails. In these method embodiments, one or more elements sense the voltage of the virtual power rails, or nodes, and make adjustments to control the voltage at certain “virtual” voltage potentials. While controlling the voltage in this manner, the virtual power control devices may serve to restrict unnecessary current flow through the integrated circuit loads.
摘要翻译：公开了降低功耗并降低集成电路泄漏电流的方法和装置。讨论了用于各种类型的集成电路（包括高速缓存存储器电路）的新的漏电省电技术。实施例包括通过使用虚拟电压轨或虚拟电源轨来降低集成电路的功率消耗的方法和装置，以向集成电路负载供电。所述方法和装置通常涉及使用一个或两个虚拟功率控制装置从牢固的电源轨道“集成”和“脚”或夹入集成电路负载。在这些方法实施例中，一个或多个元件感测虚拟电源轨或节点的电压，并进行调整以控制某些“虚拟”电压电位下的电压。在以这种方式控制电压的同时，虚拟功率控制装置可用于限制通过集成电路负载的不必要的电流。

3. 发明申请

US20070279097A1 HIGH-SPEED LOW-POWER INTEGRATED CIRCUIT INTERCONNECTS 失效
标题翻译：高速低功耗集成电路互连
公开(公告)号：US20070279097A1
公开(公告)日：2007-12-06
申请号：US11421457
申请日：2006-05-31
申请人： Zhibin Cheng , Satyajit Dutta , Peter J. Klim
发明人： Zhibin Cheng , Satyajit Dutta , Peter J. Klim
IPC分类号： H03K19/094
CPC分类号： H03K19/018585 , H03K19/0013
摘要： Methods and apparatuses to decrease power consumption of interconnecting devices in integrated circuits are disclosed. Embodiments comprise a method to reduce power consumption in integrated circuits by generating full and reduced swing signals at an output of a driver module in response to a control signal during and deactivating one or more elements to conserve power after an input signal remains unchanged for a period of time. Another embodiment comprises an apparatus to reduce power consumption in a circuit, the embodiment comprising a swing module coupled with a swing selector and an output controller. The swing module may generate full or low swing signals depending on the state of the swing selector. The output controller may increase the output impedance of the swing module after an input signal to the swing module remains unchanged for a quantity of time. Various apparatus embodiments include portable computing devices and cellular telephones.
摘要翻译：公开了降低集成电路中互连装置的功耗的方法和装置。实施例包括一种通过在驱动器模块的输出处响应于在一个或多个元件期间的控制信号和在激活一个或多个元件以节省功率以在输入信号保持不变一段时间之后在驱动器模块的输出处产生完全和减小的摆动信号来降低集成电路中的功耗的时间。另一个实施例包括一种降低电路功耗的装置，该实施例包括与摆动选择器和输出控制器耦合的摆动模块。摆动模块可以根据摆动选择器的状态产生满摆幅或低摆动信号。输出控制器可以在摆动模块的输入信号保持不变一段时间之后增加摆动模块的输出阻抗。各种设备实施例包括便携式计算设备和蜂窝电话。

4. 发明授权

US07542329B2 Virtual power rails for integrated circuits 有权
标题翻译：用于集成电路的虚拟电源轨
公开(公告)号：US07542329B2
公开(公告)日：2009-06-02
申请号：US11458616
申请日：2006-07-19
申请人： Zhibin Cheng , Satyajit Dutta , Peter J. Klim
发明人： Zhibin Cheng , Satyajit Dutta , Peter J. Klim
IPC分类号： G11C11/00
CPC分类号： G11C5/063 , G11C11/413
摘要： Methods and apparatuses to decrease power consumption and reduce leakage current of integrated circuits are disclosed. New leakage power saving techniques for various types of integrated circuits, including cache memory circuits, are discussed. Embodiments comprise methods and apparatuses to reduce power consumption in integrated circuits by using virtual voltage rails, or virtual power rails, to supply power to integrated circuit loads. The methods and apparatuses generally involve using one or two virtual power control devices to “head” and “foot”, or sandwich, the integrated circuit loads from firm power supply rails. In these method embodiments, one or more elements sense the voltage of the virtual power rails, or nodes, and make adjustments to control the voltage at certain “virtual” voltage potentials. While controlling the voltage in this manner, the virtual power control devices may serve to restrict unnecessary current flow through the integrated circuit loads.
摘要翻译：公开了降低功耗并降低集成电路泄漏电流的方法和装置。讨论了用于各种类型的集成电路（包括高速缓存存储器电路）的新的漏电省电技术。实施例包括通过使用虚拟电压轨或虚拟电源轨来降低集成电路的功率消耗的方法和装置，以向集成电路负载供电。所述方法和装置通常涉及使用一个或两个虚拟功率控制装置从牢固的电源轨道“集成”和“脚”或夹入集成电路负载。在这些方法实施例中，一个或多个元件感测虚拟电源轨或节点的电压，并进行调整以控制某些“虚拟”电压电位下的电压。在以这种方式控制电压的同时，虚拟功率控制装置可用于限制通过集成电路负载的不必要的电流。

5. 发明授权

US07366036B2 Memory device with control circuit for regulating power supply voltage 失效
标题翻译：具有用于调节电源电压的控制电路的存储器件
公开(公告)号：US07366036B2
公开(公告)日：2008-04-29
申请号：US11331618
申请日：2006-01-13
申请人： Zhibin Cheng , Satyajit Dutta , Peter J. Klim
发明人： Zhibin Cheng , Satyajit Dutta , Peter J. Klim
IPC分类号： G11C5/14
CPC分类号： G11C5/147 , G11C5/148
摘要： A Local Dynamic Power Controller (LDPC) generates and deliver to a load a full swing voltage supply signal and a reduced swing voltage supply signal. Both the full and reduce voltage supply signals are generated from a single power supply. The full swing voltage supply signal is supplied when the load is in full operational mode whereas the reduce voltage supply signal is provided when the load is in a sleep mode. As a consequence, power dissipated in the load is reduced.
摘要翻译：本地动态功率控制器（LDPC）产生负载全摆幅电压信号和降低的摆幅电压电源信号。全电源和降压电源都是从单个电源产生的。当负载处于完全工作模式时，提供全摆幅电压供应信号，而当负载处于睡眠模式时提供降压电压信号。因此，减少了在负载中消耗的功率。

6. 发明授权

US07692976B2 Memory device with control circuit for regulating power supply voltage 失效
标题翻译：具有用于调节电源电压的控制电路的存储器件
公开(公告)号：US07692976B2
公开(公告)日：2010-04-06
申请号：US11780038
申请日：2007-07-19
申请人： Zhibin B. Cheng , Satyajit Dutta , Peter J. Klim
发明人： Zhibin B. Cheng , Satyajit Dutta , Peter J. Klim
IPC分类号： G11C5/14
CPC分类号： G11C5/147 , G11C5/148
摘要： A Local Dynamic Power Controller (LDPC) generates and deliver to a load a full swing voltage supply signal and a reduced swing voltage supply signal. Both the full and reduce voltage supply signals are generated from a single power supply. The full swing voltage supply signal is supplied when the load is in full operational mode whereas the reduce voltage supply signal is provided when the load is in a sleep mode. As a consequence, power dissipated in the load is reduced.
摘要翻译：本地动态功率控制器（LDPC）产生负载全摆幅电压信号和降低的摆幅电压电源信号。全电源和降压电源都是从单个电源产生的。当负载处于完全工作模式时，提供全摆幅电压供应信号，而当负载处于睡眠模式时提供降压电压信号。因此，减少了在负载中消耗的功率。

7. 发明申请

US20120262197A1 TEST STRUCTURE AND METHODOLOGY FOR THREE-DIMENSIONAL SEMICONDUCTOR STRUCTURES 有权
公开(公告)号：US20120262197A1
公开(公告)日：2012-10-18
申请号：US13533191
申请日：2012-06-26
申请人： Kerry Bernstein , Jerome L. Cann , Christopher M. Durham , Paul D. Kartschoke , Peter J. Klim , Donald L. Wheater
发明人： Kerry Bernstein , Jerome L. Cann , Christopher M. Durham , Paul D. Kartschoke , Peter J. Klim , Donald L. Wheater
IPC分类号： G01R31/3187 , G01R1/067 , G01R31/00 , G01R31/02
CPC分类号： H01L22/32 , H01L21/4846 , H01L21/6835 , H01L21/76898 , H01L23/49827 , H01L24/11 , H01L24/13 , H01L25/0657 , H01L25/50 , H01L2221/6835 , H01L2224/13005 , H01L2224/16 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06596 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079
摘要： A plurality of peripheral test structure substrate (PTSS) through vias is formed within a peripheral test structure substrate. A peripheral test structure layer and at least one functional layer are formed on one side of the plurality of the PTSS through vias. The other side of the plurality of the PTSS through vias is exposed throughout fabrication of the peripheral test structure layer and the at least one functional layer to provide access points for testing functionality of the various layers throughout the manufacturing sequence. C4 bonding may be performed after manufacture of all of the at least one functional layer is completed. A 3D assembly carrier or a C4 carrier substrate is not required since the peripheral test structure substrate has sufficient mechanical strength to support the peripheral test structure layer and the at least one functional layer.

8. 发明授权

US08010932B2 Structure for automated transistor tuning in an integrated circuit design 有权
标题翻译：用于集成电路设计中自动晶体管调谐的结构
公开(公告)号：US08010932B2
公开(公告)日：2011-08-30
申请号：US12130476
申请日：2008-05-30
申请人： Christopher M. Durham , Peter J. Klim , Robert N. L. Krentler
发明人： Christopher M. Durham , Peter J. Klim , Robert N. L. Krentler
IPC分类号： G06F9/455
CPC分类号： G06F17/5063
摘要： A design structure for tuning an integrated circuit design holds a reference clock signal constant across the integrated circuit design and, while the reference clock signal is held constant, optimizes transistors forming a register within the integrated circuit design and thereafter optimizes transistors forming one or more clock buffers coupled to the reference clock signal.
摘要翻译：用于调谐集成电路设计的设计结构在集成电路设计中保持参考时钟信号恒定，并且当参考时钟信号保持恒定时，优化在集成电路设计中形成寄存器的晶体管，然后优化形成一个或多个时钟的晶体管耦合到参考时钟信号的缓冲器。

9. 发明申请

US20090106708A1 Structure for Reduced Area Active Above-Ground and Below-Supply Noise Suppression Circuits 失效
标题翻译：减小区域有效地面和低于电源噪声抑制电路的结构
公开(公告)号：US20090106708A1
公开(公告)日：2009-04-23
申请号：US12129532
申请日：2008-05-29
申请人： Rafik F. Dagher , Christopher M. Durham , Peter J. Klim
发明人： Rafik F. Dagher , Christopher M. Durham , Peter J. Klim
IPC分类号： G06F17/50 , H03K17/16
CPC分类号： H03K19/00361
摘要： A design structure for noise suppression. A design structure has a noise detection unit, a noise suppression unit, and a control unit. The noise suppression unit has an input and an output, wherein the input of the noise detection unit is connected to a signal and generates a signal change at the output if a change in the signal is detected. The noise suppression unit has an input and an output, wherein the input of the noise suppression unit is connected to the output of the noise detection unit and generates a correction to the signal in response to detecting the signal change at the output of the noise detection unit. The control unit has an input and an output, wherein input to the control unit is connected to the signal and turns off the noise suppression unit if a state change is detected in the signal.
摘要翻译：噪声抑制的设计结构。设计结构具有噪声检测单元，噪声抑制单元和控制单元。噪声抑制单元具有输入和输出，其中噪声检测单元的输入连接到信号，并且如果检测到信号的变化则在输出端产生信号变化。噪声抑制单元具有输入和输出，其中噪声抑制单元的输入连接到噪声检测单元的输出，并且响应于检测到噪声检测的输出处的信号变化而产生对该信号的校正单元。控制单元具有输入和输出，其中控制单元的输入连接到信号，并且如果在信号中检测到状态改变则关闭噪声抑制单元。

10. 发明申请

US20090102509A1 REDUCED AREA ACTIVE ABOVE-GROUND AND BELOW-SUPPLY NOISE SUPPRESSION CIRCUITS 失效
标题翻译：减少区域上下地下和低电压噪声抑制电路
公开(公告)号：US20090102509A1
公开(公告)日：2009-04-23
申请号：US11877219
申请日：2007-10-23
申请人： Rafik Dagher , Christopher M. Durham , Peter J. Klim
发明人： Rafik Dagher , Christopher M. Durham , Peter J. Klim
IPC分类号： H03K17/16 , H03K19/003
CPC分类号： H03K19/00361
摘要： A method and apparatus for noise suppression. A circuit has a noise detection unit, a noise suppression unit, and a control unit. The noise suppression unit has an input and an output, wherein the input of the noise detection unit is connected to a signal and generates a signal change at the output if a change in the signal is detected. The noise suppression unit has an input and an output, wherein the input of the noise suppression unit is connected to the output of the noise detection unit and generates a correction to the signal in response to detecting the signal change at the output of the noise detection unit. The control unit has an input and an output, wherein input to the control unit is connected to the signal and turns off the noise suppression unit if a state change is detected in the signal.
摘要翻译：一种用于噪声抑制的方法和装置。电路具有噪声检测单元，噪声抑制单元和控制单元。噪声抑制单元具有输入和输出，其中噪声检测单元的输入连接到信号，并且如果检测到信号的变化则在输出端产生信号变化。噪声抑制单元具有输入和输出，其中噪声抑制单元的输入连接到噪声检测单元的输出，并且响应于检测到噪声检测的输出处的信号变化而产生对该信号的校正单元。控制单元具有输入和输出，其中控制单元的输入连接到信号，并且如果在信号中检测到状态改变则关闭噪声抑制单元。

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