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1. 发明申请

US20050255667A1 Method of inducing stresses in the channel region of a transistor 失效
标题翻译：在晶体管的沟道区域中产生应力的方法
公开(公告)号：US20050255667A1
公开(公告)日：2005-11-17
申请号：US10846734
申请日：2004-05-14
申请人： Reza Arghavani , Zheng Yuan , Ellie Yieh , Shankar Venkataraman , Nitin Ingle
发明人： Reza Arghavani , Zheng Yuan , Ellie Yieh , Shankar Venkataraman , Nitin Ingle
IPC分类号： H01L21/336 , H01L21/76 , H01L21/8238 , H01L29/00 , H01L29/78
CPC分类号： H01L29/6656 , H01L21/823807 , H01L29/6659 , H01L29/7833 , H01L29/7846
摘要： A method of fabricating a semiconductor device, where the method includes forming on a transistor on a substrate, where the transistor includes a channel region configured to conduct charge between a source region and a drain region, forming a trench adjacent to the transistor, depositing a material on the substrate and within the trench, and annealing the material, where the material is tensile following the annealing and creates a tensile stress in the channel region. Also, a method of forming a trench isolation in a semiconductor device, where the method includes forming a trench in a substrate, forming a material within the trench at a lower deposition rate, forming the material on the substrate at a higher deposition rate after the depositing of the material within the trench, and annealing the material, where after the annealing the material in the trench is tensile.
摘要翻译：一种制造半导体器件的方法，其中所述方法包括在衬底上的晶体管上形成晶体管，其中所述晶体管包括被配置为在源极区域和漏极区域之间导电的沟道区域，形成与所述晶体管相邻的沟槽，材料在衬底上并在沟槽内，并退火材料，其中材料在退火之后是拉伸的，并且在沟道区域中产生拉伸应力。另外，在半导体器件中形成沟槽隔离的方法，其中所述方法包括在衬底中形成沟槽，以较低的沉积速率在沟槽内形成材料，在衬底上以更高的沉积速率在衬底上形成材料在沟槽内沉积材料并退火材料，其中在退火之后，沟槽中的材料是拉伸的。

2. 发明申请

US20050196929A1 Low-thermal-budget gapfill process 有权
标题翻译：低热量预算的填隙过程
公开(公告)号：US20050196929A1
公开(公告)日：2005-09-08
申请号：US10793559
申请日：2004-03-04
申请人： Zheng Yuan , Reza Arghavani , Ellie Yieh , Shankar Venkataraman
发明人： Zheng Yuan , Reza Arghavani , Ellie Yieh , Shankar Venkataraman
IPC分类号： H01L21/336
CPC分类号： H01L21/76224 , C23C16/403 , C23C16/45536 , C23C16/45544 , H01J37/32009 , H01L21/02178 , H01L21/0228 , H01L21/32055 , H01L21/67017 , H01L21/6719 , H01L21/763
摘要： A low-thermal-budget gapfill process is provided for filling a gap formed between two adjacent raised features on a strained-silicon substrate as part of a shallow-trench-isolation process. An electrically insulating liner is deposited using atomic-layer deposition and polysilicon is deposited over the electrically insulating liner, with both stages being conducted at temperatures below 700° C.
摘要翻译：提供了一种低热预算的间隙填充方法，用于填充在应变硅衬底上形成的两个相邻凸起特征之间的间隙，作为浅沟槽隔离工艺的一部分。使用原子层沉积沉积电绝缘衬垫，并且将多晶硅沉积在电绝缘衬垫上，其中两个阶段在低于700℃的温度下进行。

3. 发明申请

US20050277257A1 Gap filling with a composite layer 失效
标题翻译：间隙填充复合层
公开(公告)号：US20050277257A1
公开(公告)日：2005-12-15
申请号：US10857829
申请日：2004-06-01
申请人： Jeong Byun , Zheng Yuan , Shankar Venkataraman , M. Karim , Thanh Pham , Ellie Yieh
发明人： Jeong Byun , Zheng Yuan , Shankar Venkataraman , M. Karim , Thanh Pham , Ellie Yieh
IPC分类号： H01L21/76 , H01L21/762
CPC分类号： H01L21/76224
摘要： A method of filling a gap formed between adjacent raised surfaces on a substrate. In one embodiment the method comprises depositing a boron-doped silica glass (BSG) layer over the substrate to partially fill the gap using a thermal CVD process; exposing the BSG layer to a steam ambient at a temperature above the BSG layer's Eutectic temperature; removing an upper portion of the BSG layer by exposing the layer to a fluorine-containing etchant; and depositing an undoped silica glass (USG) layer over the BSG layer to fill the remainder of the gap.
摘要翻译：填充在基板上相邻的凸起表面之间形成的间隙的方法。在一个实施例中，该方法包括在衬底上沉积硼掺杂石英玻璃（BSG）层，以使用热CVD工艺部分填充间隙; 在高于BSG层的共晶温度的温度下将BSG层暴露于蒸汽环境; 通过将层暴露于含氟蚀刻剂来除去BSG层的上部; 以及在BSG层上沉积未掺杂的二氧化硅玻璃（USG）层以填补间隙的剩余部分。

4. 发明申请

US20070132054A1 MEMORY CELL HAVING STRESSED LAYERS 失效
标题翻译：具有压力层的记忆体
公开(公告)号：US20070132054A1
公开(公告)日：2007-06-14
申请号：US11609851
申请日：2006-12-12
申请人： Reza Arghavani , Ellie Yieh , Hichem M'Saad
发明人： Reza Arghavani , Ellie Yieh , Hichem M'Saad
IPC分类号： H01L29/00
CPC分类号： H01L29/7846 , H01L27/105 , H01L27/1052 , H01L29/66825 , H01L29/7883
摘要： A memory cell comprises a p-doped substrate with a pair of spaced apart n-doped regions on the substrate that form a source and drain about the channel. A stack of layers on the channel comprises, in sequence, (i) a tunnel oxide layer, (ii) a floating gate, (iii) an inter-gate dielectric, and (iv) a control gate. A polysilicon layer is on the source and drain. A cover layer covering the stack of layers comprises a spacer layer and a pre-metal-deposition layer. Optionally, contacts are used to contact each of the source, drain, and silicide layers, and each have exposed portions. A shallow isolation trench is provided about n-doped regions, the trench comprising a stressed silicon oxide layer having a tensile stress of at least about 200 MPa. The stressed layer reduces leakage of charge held in the floating gate during operation of the memory cell.
摘要翻译：存储单元包括在基板上具有一对间隔开的n掺杂区域的p掺杂衬底，其在沟道周围形成源极和漏极。通道上的层叠层包括（i）隧道氧化物层，（ii）浮动栅极，（iii）栅极间电介质和（iv）控制栅极。源极和漏极上的多晶硅层。覆盖层叠层的覆盖层包括间隔层和预金属沉积层。可选地，使用触点来接触源极，漏极和硅化物层中的每一个，并且每个都具有暴露部分。围绕n掺杂区域提供浅的隔离沟槽，沟槽包括具有至少约200MPa的拉伸应力的应力氧化硅层。应力层在存储器单元的操作期间减少了保持在浮动栅极中的电荷的泄漏。

5. 发明授权

US07678662B2 Memory cell having stressed layers 失效
标题翻译：具有应力层的记忆单元
公开(公告)号：US07678662B2
公开(公告)日：2010-03-16
申请号：US11609851
申请日：2006-12-12
申请人： Reza Arghavani , Ellie Yieh , Hichem M'Saad
发明人： Reza Arghavani , Ellie Yieh , Hichem M'Saad
IPC分类号： H01L21/76
CPC分类号： H01L29/7846 , H01L27/105 , H01L27/1052 , H01L29/66825 , H01L29/7883
摘要： A memory cell comprises a p-doped substrate with a pair of spaced apart n-doped regions on the substrate that form a source and drain about the channel. A stack of layers on the channel comprises, in sequence, (i) a tunnel oxide layer, (ii) a floating gate, (iii) an inter-gate dielectric, and (iv) a control gate. A polysilicon layer is on the source and drain. A cover layer covering the stack of layers comprises a spacer layer and a pre-metal-deposition layer. Optionally, contacts are used to contact each of the source, drain, and silicide layers, and each have exposed portions. A shallow isolation trench is provided about n-doped regions, the trench comprising a stressed silicon oxide layer having a tensile stress of at least about 200 MPa. The stressed layer reduces leakage of charge held in the floating gate during operation of the memory cell.
摘要翻译：存储单元包括在基板上具有一对间隔开的n掺杂区域的p掺杂衬底，其在沟道周围形成源极和漏极。通道上的层叠层包括（i）隧道氧化物层，（ii）浮动栅极，（iii）栅极间电介质和（iv）控制栅极。源极和漏极上的多晶硅层。覆盖层叠层的覆盖层包括间隔层和预金属沉积层。可选地，使用触点来接触源极，漏极和硅化物层中的每一个，并且每个都具有暴露部分。围绕n掺杂区域提供浅的隔离沟槽，沟槽包括具有至少约200MPa的拉伸应力的应力氧化硅层。应力层在存储器单元的操作期间减少了保持在浮动栅极中的电荷的泄漏。

6. 发明申请

US20050103266A1 Accelerated plasma clean 有权
标题翻译：加速等离子清洁
公开(公告)号：US20050103266A1
公开(公告)日：2005-05-19
申请号：US10968420
申请日：2004-10-18
申请人： Shankar Chandran , Scott Hendrickson , Gwendolyn Jones , Shankar Venkataraman , Ellie Yieh
发明人： Shankar Chandran , Scott Hendrickson , Gwendolyn Jones , Shankar Venkataraman , Ellie Yieh
IPC分类号： B08B9/08 , C23C16/44 , H01L21/304 , C25F1/00 , C23C16/00
CPC分类号： C23C16/4405 , Y10S134/902 , Y10S438/905
摘要： A method and apparatus that reduces the time required to clean a processing chamber employing a reactive plasma cleaning process. A plasma is formed in an Astron fluorine source generator from a flow of substantially pure inert-source gas. After formation of the plasma, a flow of a fluorine source gas is introduced therein such that the fluorine source flow accelerates at a rate no greater than 1.67 standard cubic centimeters per second2 (scc/s2). In this fashion, the plasma contains a plurality of radicals and dissociated inert-source gas atoms, defining a cleaning mixture. The ratio of inert-source gas to fluorine source is greater than 1:1.
摘要翻译：一种减少使用反应性等离子体清洗工艺清洁处理室所需时间的方法和装置。在基本上纯的惰性气体气体的流中，在Astron氟源发生器中形成等离子体。在形成等离子体之后，引入氟源气体的流动，使得氟源流以不大于1.67标准立方厘米/秒的速度加速（scc / s < 2 ）。以这种方式，等离子体包含多个自由基和解离的惰性气体原子，限定清洁混合物。惰性气体与氟源的比例大于1:1。

7. 发明授权

US06890850B2 Method of depositing dielectric materials in damascene applications 失效
标题翻译：在大马士革应用中沉积电介质材料的方法
公开(公告)号：US06890850B2
公开(公告)日：2005-05-10
申请号：US10196498
申请日：2002-07-15
申请人： Ju-Hyung Lee , Ping Xu , Shankar Venkataraman , Li-Qun Xia , Fei Han , Ellie Yieh , Srinivas D. Nemani , Kangsub Yim , Farhad K. Moghadam , Ashok K. Sinha , Yi Zheng
发明人： Ju-Hyung Lee , Ping Xu , Shankar Venkataraman , Li-Qun Xia , Fei Han , Ellie Yieh , Srinivas D. Nemani , Kangsub Yim , Farhad K. Moghadam , Ashok K. Sinha , Yi Zheng
IPC分类号： C23C16/42 , C23C16/30 , C23C16/40 , C23C16/56 , H01L21/311 , H01L21/312 , H01L21/316 , H01L21/768 , H01L23/522 , H01L21/4763 , H01L21/31 , H01L21/469
CPC分类号： H01L21/76834 , C23C16/30 , C23C16/401 , C23C16/56 , H01L21/02126 , H01L21/02211 , H01L21/02216 , H01L21/02274 , H01L21/02304 , H01L21/31138 , H01L21/31144 , H01L21/312 , H01L21/3122 , H01L21/3127 , H01L21/31633 , H01L21/76807 , H01L21/7681 , H01L21/76826 , H01L21/76828 , H01L21/76829
摘要： Methods are provided for depositing an oxygen-doped dielectric layer. The oxygen-doped dielectric layer may be used for a barrier layer or a hardmask. In one aspect, a method is provided for processing a substrate including positioning the substrate in a processing chamber, introducing a processing gas comprising an oxygen-containing organosilicon compound, carbon dioxide, or combinations thereof, and an oxygen-free organosilicon compound to the processing chamber, and reacting the processing gas to deposit an oxygen-doped dielectric material on the substrate, wherein the dielectric material has an oxygen content of about 15 atomic percent or less. The oxygen-doped dielectric material may be used as a barrier layer in damascene or dual damascene applications.
摘要翻译：提供了用于沉积氧掺杂介电层的方法。氧掺杂介电层可用于阻挡层或硬掩模。在一个方面，提供了一种处理衬底的方法，包括将衬底定位在处理室中，将包含含氧有机硅化合物，二氧化碳或其组合的处理气体和无氧有机硅化合物引入到处理并且使所述处理气体反应以在所述衬底上沉积掺杂氧的电介质材料，其中所述介电材料的氧含量为约15原子％或更低。氧掺杂的电介质材料可以用作镶嵌或双镶嵌应用中的阻挡层。

8. 发明授权

US06709721B2 Purge heater design and process development for the improvement of low k film properties 失效
标题翻译：吹扫加热器设计和工艺开发，用于改善低k膜性能
公开(公告)号：US06709721B2
公开(公告)日：2004-03-23
申请号：US09820586
申请日：2001-03-28
申请人： Juan Carlos Rocha-Alvarez , Chen-An Chen , Ellie Yieh , Shankar Venkataraman
发明人： Juan Carlos Rocha-Alvarez , Chen-An Chen , Ellie Yieh , Shankar Venkataraman
IPC分类号： C23C1640
CPC分类号： C23C16/45521 , C23C16/401 , C23C16/455 , C23C16/4585 , H01L21/02126 , H01L21/02211 , H01L21/02274 , H01L21/31633 , Y10T428/31
摘要： The present invention provides a method of depositing a carbon doped silicon oxide film having a low dielectric constant (k). A process gas mixture containing at least a carrier gas, an oxidizer, a carbon gas source, or combinations thereof, is supplied adjacent an edge of a substrate though a purge gas inlet in a substrate support to facilitate deposition of low k carbon doped silicon oxide film having a greater concentration of silicon oxide around the edge of the substrate than an inner portion of the substrate.
摘要翻译：本发明提供一种沉积具有低介电常数（k）的碳掺杂氧化硅膜的方法。含有至少载体气体，氧化剂，碳气体源或其组合的工艺气体混合物通过衬底支撑件中的吹扫气体入口邻近衬底的边缘提供，以便于沉积低k碳掺杂氧化硅膜比衬底的内部具有比衬底边缘更高浓度的氧化硅。

9. 发明授权

US06943127B2 CVD plasma assisted lower dielectric constant SICOH film 失效
标题翻译： CVD等离子体辅助低介电常数SICOH膜
公开(公告)号：US06943127B2
公开(公告)日：2005-09-13
申请号：US10302240
申请日：2002-11-22
申请人： Seon-Mee Cho , Peter Wai-Man Lee , Chi-I Lang , Dian Sugiarto , Chen-An Chen , Li-Qun Xia , Shankar Venkataraman , Ellie Yieh
发明人： Seon-Mee Cho , Peter Wai-Man Lee , Chi-I Lang , Dian Sugiarto , Chen-An Chen , Li-Qun Xia , Shankar Venkataraman , Ellie Yieh
IPC分类号： C23C16/30 , H01L21/316 , H01L21/42
CPC分类号： H01L21/02126 , C23C16/30 , H01L21/02211 , H01L21/02216 , H01L21/02274 , H01L21/02304 , H01L21/02362 , H01L21/31633 , Y10S438/931 , Y10T428/31909
摘要： A low dielectric constant film having silicon-carbon bonds and dielectric constant of about 3.0 or less, preferably about 2.5 or less, is provided. The low dielectric constant film is deposited by reacting a cyclic organosilicon compound and an aliphatic organosilicon compound with an oxidizing gas while applying RF power. The carbon content of the deposited film is between about 10 and about 30 atomic percent excluding hydrogen atoms, and is preferably between about 10 and about 20 atomic percent excluding hydrogen atoms.
摘要翻译：提供了具有约3.0或更小，优选约2.5或更小的硅 - 碳键和介电常数的低介电常数膜。通过使环状有机硅化合物和脂族有机硅化合物与氧化气体反应同时施加RF功率来沉积低介电常数膜。沉积膜的碳含量除氢原子以外约为10至约30原子百分比，优选除氢原子之外约10至约20原子％。

10. 发明授权

US06413583B1 Formation of a liquid-like silica layer by reaction of an organosilicon compound and a hydroxyl forming compound 有权
标题翻译：通过有机硅化合物和羟基形成化合物的反应形成液状二氧化硅层
公开(公告)号：US06413583B1
公开(公告)日：2002-07-02
申请号：US09338470
申请日：1999-06-22
申请人： Farhad K. Moghadam , David W. Cheung , Ellie Yieh , Li-Qun Xia , Wai-Fan Yau , Chi-I Lang , Shin-Puu Jeng , Frederic Gaillard , Shankar Venkataraman , Srinivas Nemani
发明人： Farhad K. Moghadam , David W. Cheung , Ellie Yieh , Li-Qun Xia , Wai-Fan Yau , Chi-I Lang , Shin-Puu Jeng , Frederic Gaillard , Shankar Venkataraman , Srinivas Nemani
IPC分类号： C23C1640
CPC分类号： H01L21/02126 , C23C16/401 , H01L21/02203 , H01L21/02208 , H01L21/02274 , H01L21/0228 , H01L21/02304 , H01L21/02362 , H01L21/31053 , H01L21/3122 , H01L21/31604 , H01L21/31612 , H01L21/76828 , H01L21/76834
摘要： A method for depositing silicon oxide layers having a low dielectric constant by reaction of an organosilicon compound and a hydroxyl forming compound at a substrate temperature less than about 400° C. The low dielectric constant films contain residual carbon and are useful for gap fill layers, pre-metal dielectric layers, inter-metal dielectric layers, and shallow trench isolation dielectric layers in sub-micron devices. The hydroxyl compound can be prepared prior to deposition from water or an organic compound. The silicon oxide layers are preferably deposited at a substrate temperature less than about 40° C. onto a liner layer produced from the organosilicon compound to provide gap fill layers having a dielectric constant less than about 3.0.
摘要翻译：一种通过在低于约400℃的衬底温度下通过有机硅化合物和羟基形成化合物的反应沉积低介电常数的氧化硅层的方法。低介电常数膜含有残余碳并可用于间隙填充层，预金属介电层，金属间介电层和亚微米器件中的浅沟槽隔离电介质层。羟基化合物可以在从水或有机化合物沉积之前制备。氧化硅层优选在低于约40℃的衬底温度下沉积到由有机硅化合物制备的衬里层上，以提供介电常数小于约3.0的间隙填充层。

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