专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20050259682A1 Broadcast system 审中-公开
标题翻译：广播系统
公开(公告)号：US20050259682A1
公开(公告)日：2005-11-24
申请号：US10182753
申请日：2001-02-02
申请人： Yuval Yosef , Haim Neerman , Doron Rajwan , Edan Ayal
发明人： Yuval Yosef , Haim Neerman , Doron Rajwan , Edan Ayal
IPC分类号： H04J3/16 , H04L12/18 , H04L29/08
CPC分类号： H04L12/1859 , H04L12/18 , H04L67/2823 , H04L67/2828 , H04L67/2842
摘要： A method of emulating an interactive connection, comprising: generating a request for interactive data from an interactive server, at a client; intercepting said request by an agent; responsive to said request, retrieving at least some of said data from a continuous retransmission of said data, by said agent; and displaying said data including said retrieved data at said client.
摘要翻译：一种模拟交互式连接的方法，包括：在客户端处产生来自交互式服务器的交互式数据的请求; 由代理人截取该请求; 响应于所述请求，由所述代理从所述数据的连续重传中检索所述数据中的至少一些; 以及在所述客户端显示包括所述检索的数据的所述数据。

2. 发明授权

US08166320B2 Power aware software pipelining for hardware accelerators 有权
标题翻译：功率感知软件流水线用于硬件加速器
公开(公告)号：US08166320B2
公开(公告)日：2012-04-24
申请号：US12704015
申请日：2010-02-11
申请人： Ron Gabor , Hong Jiang , Alon Naveh , Doron Rajwan , James Varga , Gady Yearim , Yuval Yosef
发明人： Ron Gabor , Hong Jiang , Alon Naveh , Doron Rajwan , James Varga , Gady Yearim , Yuval Yosef
IPC分类号： G06F1/32 , G06F1/00 , G06F9/30
CPC分类号： G06F1/3203
摘要： Forming a plurality of pipeline orderings, each pipeline ordering comprising one of a sequential, a parallel, or a sequential and parallel combination of a plurality of stages of a pipeline, analyzing the plurality of pipeline orderings to determine a total power of each of the orderings, and selecting one of the plurality of pipeline orderings based on the determined total power of each of the plurality of pipeline orderings.
摘要翻译：形成多个流水线排序，每个流水线排序包括流水线的多个阶段的顺序，并行或顺序和并行组合中的一个，分析多个流水线排序以确定每个排序的总功率并且基于所确定的多个流水线排序中的每一个的总功率来选择多个流水线排序中的一个。

3. 发明授权

US07725745B2 Power aware software pipelining for hardware accelerators 有权
公开(公告)号：US07725745B2
公开(公告)日：2010-05-25
申请号：US11642128
申请日：2006-12-19
申请人： Ron Gabor , Hong Jiang , Alon Naveh , Doron Rajwan , James Varga , Gady Yearim , Yuval Yosef
发明人： Ron Gabor , Hong Jiang , Alon Naveh , Doron Rajwan , James Varga , Gady Yearim , Yuval Yosef
IPC分类号： G06F1/32 , G06F1/00 , G06F9/40
CPC分类号： G06F1/3203
摘要： Forming a plurality of pipeline orderings, each pipeline ordering comprising one of a sequential, a parallel, or a sequential and parallel combination of a plurality of stages of a pipeline, analyzing the plurality of pipeline orderings to determine a total power of each of the orderings, and selecting one of the plurality of pipeline orderings based on the determined total power of each of the plurality of pipeline orderings.

4. 发明申请

US20080148076A1 Power aware software pipelining for hardware accelerators 有权
标题翻译：功率感知软件流水线用于硬件加速器
公开(公告)号：US20080148076A1
公开(公告)日：2008-06-19
申请号：US11642128
申请日：2006-12-19
申请人： Ron Gabor , Hong Jiang , Alon Naveh , Doron Rajwan , James Varga , Gady Yearim , Yuval Yosef
发明人： Ron Gabor , Hong Jiang , Alon Naveh , Doron Rajwan , James Varga , Gady Yearim , Yuval Yosef
IPC分类号： G06F1/28
CPC分类号： G06F1/3203
摘要： Forming a plurality of pipeline orderings, each pipeline ordering comprising one of a sequential, a parallel, or a sequential and parallel combination of a plurality of stages of a pipeline, analyzing the plurality of pipeline orderings to determine a total power of each of the orderings, and selecting one of the plurality of pipeline orderings based on the determined total power of each of the plurality of pipeline orderings.
摘要翻译：形成多个流水线排序，每个流水线排序包括流水线的多个阶段的顺序，并行或顺序和并行组合中的一个，分析多个流水线排序以确定每个排序的总功率并且基于所确定的多个流水线排序中的每一个的总功率来选择多个流水线排序中的一个。

5. 发明申请

US20100146314A1 Power aware software pipelining for hardware accelerators 有权
标题翻译：功率感知软件流水线用于硬件加速器
公开(公告)号：US20100146314A1
公开(公告)日：2010-06-10
申请号：US12704015
申请日：2010-02-11
申请人： Ron Gabor , Hong Jiang , Alon Naveh , Doron Rajwan , James Varga , Gady Yearim , Yuval Yosef
发明人： Ron Gabor , Hong Jiang , Alon Naveh , Doron Rajwan , James Varga , Gady Yearim , Yuval Yosef
IPC分类号： G06F1/32 , G06F1/26 , G06F9/30 , G06F9/38
CPC分类号： G06F1/3203
摘要： Forming a plurality of pipeline orderings, each pipeline ordering comprising one of a sequential, a parallel, or a sequential and parallel combination of a plurality of stages of a pipeline, analyzing the plurality of pipeline orderings to determine a total power of each of the orderings, and selecting one of the plurality of pipeline orderings based on the determined total power of each of the plurality of pipeline orderings.
摘要翻译：形成多个流水线排序，每个流水线排序包括流水线的多个阶段的顺序，并行或顺序和并行组合中的一个，分析多个流水线排序以确定每个排序的总功率并且基于所确定的多个流水线排序中的每一个的总功率来选择多个流水线排序中的一个。

6. 发明授权

US09032223B2 Techniques to manage operational parameters for a processor 有权
标题翻译：管理处理器的操作参数的技术
公开(公告)号：US09032223B2
公开(公告)日：2015-05-12
申请号：US12205317
申请日：2008-09-05
申请人： Efraim Rotem , Eric Distefano , Jim Hermerding , Ronny Korner , Yuval Yosef
发明人： Efraim Rotem , Eric Distefano , Jim Hermerding , Ronny Korner , Yuval Yosef
IPC分类号： G06F1/26 , G06F1/20 , G06F11/30
CPC分类号： G06F1/206 , G06F11/3006 , G06F11/3058 , G06F11/3089 , Y02D10/16
摘要： Techniques to manage operational parameters for a processor are described. For instance, a method includes monitoring performance values representing physical characteristics for multiple components of a computing platform, and managing a performance level for a processor based on the performance values and one or more operational parameters for the processor. The operational parameters may include one or more transitory operational parameters that cause the processor to temporarily exceed operational parameters set by a thermal design power limit. Other embodiments are described and claimed.
摘要翻译：描述了管理处理器的操作参数的技术。例如，一种方法包括监视表示计算平台的多个组件的物理特性的性能值，以及基于处理器的性能值和一个或多个操作参数来管理处理器的性能水平。操作参数可以包括使得处理器临时超过由热设计功率限制设定的操作参数的一个或多个暂时操作参数。描述和要求保护其他实施例。

7. 发明申请

US20140129808A1 MIGRATING TASKS BETWEEN ASYMMETRIC COMPUTING ELEMENTS OF A MULTI-CORE PROCESSOR 审中-公开
标题翻译：多核处理器的不对称计算元素之间的迁移任务
公开(公告)号：US20140129808A1
公开(公告)日：2014-05-08
申请号：US13994142
申请日：2012-04-27
申请人： Alon Naveh , Yuval Yosef , Eliezer Weissmann , Anil Aggarwal , Efraim Rotem , Avi Mendelson , Ronny Ronen , Boris Ginzburg , Michael Mishaeli , Scott D. Hahn , David A. Koufaty , Ganapati Srinivasa , Guy Therien
发明人： Alon Naveh , Yuval Yosef , Eliezer Weissmann , Anil Aggarwal , Efraim Rotem , Avi Mendelson , Ronny Ronen , Boris Ginzburg , Michael Mishaeli , Scott D. Hahn , David A. Koufaty , Ganapati Srinivasa , Guy Therien
IPC分类号： G06F9/30
CPC分类号： G06F9/30145 , G06F9/4856 , G06F9/5094 , G06F2209/5018 , Y02D10/22 , Y02D10/24 , Y02D10/32
摘要： In one embodiment, the present invention includes a multicore processor having first and second cores to independently execute instructions, the first core visible to an operating system (OS) and the second core transparent to the OS and heterogeneous from the first core. A task controller, which may be included in or coupled to the multicore processor, can cause dynamic migration of a first process scheduled by the OS to the first core to the second core transparently to the OS. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括具有第一和第二核心以独立执行指令的多核处理器，操作系统（OS）可见的第一核心和对OS可透明的第二核心，并且与第一核心不同。可以包括在多核处理器中或耦合到多核处理器的任务控制器可以使由OS所安排的第一进程到OS的第一核心到第二核心的动态迁移到第二核心。描述和要求保护其他实施例。

8. 发明申请

US20160246597A1 APPARATUS AND METHOD FOR LOW-LATENCY INVOCATION OF ACCELERATORS 审中-公开
标题翻译：低速延迟加速器的装置和方法
公开(公告)号：US20160246597A1
公开(公告)日：2016-08-25
申请号：US15145748
申请日：2016-05-03
申请人： Oren Ben-Kiki , llan Pardo , Robert Valentine , Eliezer Weissmann , Dror Markovich , Yuval Yosef
发明人： Oren Ben-Kiki , llan Pardo , Robert Valentine , Eliezer Weissmann , Dror Markovich , Yuval Yosef
IPC分类号： G06F9/30
CPC分类号： G06F9/3802 , G06F9/3004 , G06F9/30043 , G06F9/30076 , G06F9/30101 , G06F9/30145 , G06F9/3016 , G06F9/384 , G06F9/3877 , G06F9/3879 , G06F9/3881 , G06F9/54 , G06F11/0721 , G06F11/0724 , G06F11/0772 , G06F12/0875 , G06F2212/452
摘要： An apparatus and method are described for providing low-latency invocation of accelerators. For example, a processor according to one embodiment comprises: a command register for storing command data identifying a command to be executed; a result register to store a result of the command or data indicating a reason why the commend could not be executed; execution logic to execute a plurality of instructions including an accelerator invocation instruction to invoke one or more accelerator commands, the accelerator invocation instruction to store command data specifying the command within the command register; one or more accelerators to read the command data from the command register and responsively attempt to execute the command identified by the command data, wherein if the one or more accelerators successfully execute the command, the one or more accelerators are to store result data comprising the results of the command in the result register; and if the one or more accelerators cannot successfully execute the command, the one or more accelerators are to store result data indicating a reason why the command cannot be executed, wherein the execution logic is to temporarily halt execution until the accelerator completes execution or is interrupted, wherein the accelerator includes logic to store its state if interrupted so that it can continue execution at a later time.
摘要翻译：描述了一种用于提供加速器的低延迟调用的装置和方法。例如，根据一个实施例的处理器包括：命令寄存器，用于存储标识要执行的命令的命令数据; 用于存储命令结果的结果寄存器或指示不能执行推荐的原因的数据; 执行逻辑以执行包括用于调用一个或多个加速器命令的加速器调用指令的多个指令，所述加速器调用指令将指定所述命令的命令数据存储在所述命令寄存器内; 一个或多个加速器，用于从命令寄存器读取命令数据并响应于尝试执行由命令数据识别的命令，其中如果一个或多个加速器成功地执行命令，则一个或多个加速器将存储包括结果寄存器中的命令结果; 并且如果一个或多个加速器不能成功地执行命令，则一个或多个加速器将存储指示不能执行该命令的原因的结果数据，其中执行逻辑将暂停执行，直到加速器完成执行或被中断其中所述加速器包括用于存储其状态的逻辑，如果被中断，使得其可以在稍后的时间继续执行。

9. 发明申请

US20070157211A1 Instruction set architecture-based inter-sequencer communications with a heterogeneous resource 有权
标题翻译：与异构资源的指令集基于架构的间隔器通信
公开(公告)号：US20070157211A1
公开(公告)日：2007-07-05
申请号：US11321779
申请日：2005-12-29
申请人： Hong Wang , John Shen , Hong Jiang , Richard Hankins , Per Hammarlund , Dion Rodgers , Gautham Chinya , Baiju Patel , Shiv Kaushik , Bryant Bigbee , Gad Sheaffer , Yoav Talgam , Yuval Yosef , James Held
发明人： Hong Wang , John Shen , Hong Jiang , Richard Hankins , Per Hammarlund , Dion Rodgers , Gautham Chinya , Baiju Patel , Shiv Kaushik , Bryant Bigbee , Gad Sheaffer , Yoav Talgam , Yuval Yosef , James Held
IPC分类号： G06F9/46
CPC分类号： G06F9/30145 , G06F9/30 , G06F9/30181 , G06F9/3877 , G06F9/3879 , G06T1/20
摘要： In one embodiment, the present invention includes a method for directly communicating between an accelerator and an instruction sequencer coupled thereto, where the accelerator is a heterogeneous resource with respect to the instruction sequencer. An interface may be used to provide the communication between these resources. Via such a communication mechanism a user-level application may directly communicate with the accelerator without operating system support. Further, the instruction sequencer and the accelerator may perform operations in parallel. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括一种用于在加速器和与其耦合的指令定序器之间直接通信的方法，其中加速器相对于指令定序器是异质资源。可以使用接口来提供这些资源之间的通信。通过这种通信机制，用户级应用可以直接与加速器进行通信，而无需操作系统支持。此外，指令定序器和加速器可以并行地执行操作。描述和要求保护其他实施例。

10. 发明授权

US08914618B2 Instruction set architecture-based inter-sequencer communications with a heterogeneous resource 有权
标题翻译：与异构资源的指令集基于架构的间隔器通信
公开(公告)号：US08914618B2
公开(公告)日：2014-12-16
申请号：US11321779
申请日：2005-12-29
申请人： Hong Wang , John Shen , Hong Jiang , Richard Hankins , Per Hammarlund , Dion Rodgers , Gautham Chinya , Baiju Patel , Shiv Kaushik , Bryant Bigbee , Gad Sheaffer , Yoav Talgam , Yuval Yosef , James P. Held
发明人： Hong Wang , John Shen , Hong Jiang , Richard Hankins , Per Hammarlund , Dion Rodgers , Gautham Chinya , Baiju Patel , Shiv Kaushik , Bryant Bigbee , Gad Sheaffer , Yoav Talgam , Yuval Yosef , James P. Held
IPC分类号： G06F9/30 , G06F15/76 , G06F9/38
CPC分类号： G06F9/30145 , G06F9/30 , G06F9/30181 , G06F9/3877 , G06F9/3879 , G06T1/20
摘要： In one embodiment, the present invention includes a method for directly communicating between an accelerator and an instruction sequencer coupled thereto, where the accelerator is a heterogeneous resource with respect to the instruction sequencer. An interface may be used to provide the communication between these resources. Via such a communication mechanism a user-level application may directly communicate with the accelerator without operating system support. Further, the instruction sequencer and the accelerator may perform operations in parallel. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括一种用于在加速器和与其耦合的指令定序器之间直接通信的方法，其中加速器相对于指令定序器是异质资源。可以使用接口来提供这些资源之间的通信。通过这种通信机制，用户级应用可以直接与加速器进行通信，而无需操作系统支持。此外，指令定序器和加速器可以并行地执行操作。描述和要求保护其他实施例。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式