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1. 发明申请

US20140129808A1 MIGRATING TASKS BETWEEN ASYMMETRIC COMPUTING ELEMENTS OF A MULTI-CORE PROCESSOR 审中-公开
标题翻译：多核处理器的不对称计算元素之间的迁移任务
公开(公告)号：US20140129808A1
公开(公告)日：2014-05-08
申请号：US13994142
申请日：2012-04-27
申请人： Alon Naveh , Yuval Yosef , Eliezer Weissmann , Anil Aggarwal , Efraim Rotem , Avi Mendelson , Ronny Ronen , Boris Ginzburg , Michael Mishaeli , Scott D. Hahn , David A. Koufaty , Ganapati Srinivasa , Guy Therien
发明人： Alon Naveh , Yuval Yosef , Eliezer Weissmann , Anil Aggarwal , Efraim Rotem , Avi Mendelson , Ronny Ronen , Boris Ginzburg , Michael Mishaeli , Scott D. Hahn , David A. Koufaty , Ganapati Srinivasa , Guy Therien
IPC分类号： G06F9/30
CPC分类号： G06F9/30145 , G06F9/4856 , G06F9/5094 , G06F2209/5018 , Y02D10/22 , Y02D10/24 , Y02D10/32
摘要： In one embodiment, the present invention includes a multicore processor having first and second cores to independently execute instructions, the first core visible to an operating system (OS) and the second core transparent to the OS and heterogeneous from the first core. A task controller, which may be included in or coupled to the multicore processor, can cause dynamic migration of a first process scheduled by the OS to the first core to the second core transparently to the OS. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括具有第一和第二核心以独立执行指令的多核处理器，操作系统（OS）可见的第一核心和对OS可透明的第二核心，并且与第一核心不同。可以包括在多核处理器中或耦合到多核处理器的任务控制器可以使由OS所安排的第一进程到OS的第一核心到第二核心的动态迁移到第二核心。描述和要求保护其他实施例。

2. 发明授权

US10185566B2 Migrating tasks between asymmetric computing elements of a multi-core processor 有权
公开(公告)号：US10185566B2
公开(公告)日：2019-01-22
申请号：US13994142
申请日：2012-04-27
申请人： Alon Naveh , Yuval Yosef , Eliezer Weissmann , Anil Aggarwal , Efraim Rotem , Avi Mendelson , Ronny Ronen , Boris Ginzburg , Michael Mishaeli , Scott D. Hahn , David A. Koufaty , Ganapati Srinivasa , Guy Therien
发明人： Alon Naveh , Yuval Yosef , Eliezer Weissmann , Anil Aggarwal , Efraim Rotem , Avi Mendelson , Ronny Ronen , Boris Ginzburg , Michael Mishaeli , Scott D. Hahn , David A. Koufaty , Ganapati Srinivasa , Guy Therien
IPC分类号： G06F9/30 , G06F9/48 , G06F9/50
摘要： In one embodiment, the present invention includes a multicore processor having first and second cores to independently execute instructions, the first core visible to an operating system (OS) and the second core transparent to the OS and heterogeneous from the first core. A task controller, which may be included in or coupled to the multicore processor, can cause dynamic migration of a first process scheduled by the OS to the first core to the second core transparently to the OS. Other embodiments are described and claimed.

3. 发明申请

US20140281399A1 INSTRUCTION EMULATION PROCESSORS, METHODS, AND SYSTEMS 有权
标题翻译：指令仿真处理器，方法和系统
公开(公告)号：US20140281399A1
公开(公告)日：2014-09-18
申请号：US13844881
申请日：2013-03-16
申请人： WILLIAM C. RASH , BRET L. TOLL , SCOTT D. HAHN , GLENN J. HINTON
发明人： WILLIAM C. RASH , BRET L. TOLL , SCOTT D. HAHN , GLENN J. HINTON
IPC分类号： G06F9/30
CPC分类号： G06F9/30145 , G06F9/3017 , G06F9/30189
摘要： A processor of an aspect includes decode logic to receive a first instruction and to determine that the first instruction is to be emulated. The processor also includes emulation mode aware post-decode instruction processor logic coupled with the decode logic. The emulation mode aware post-decode instruction processor logic is to process one or more control signals decoded from an instruction. The instruction is one of a set of one or more instructions used to emulate the first instruction. The one or more control signals are to be processed differently by the emulation mode aware post-decode instruction processor logic when in an emulation mode than when not in the emulation mode. Other apparatus are also disclosed as well as methods and systems.
摘要翻译：一方面的处理器包括用于接收第一指令并确定要仿真第一指令的解码逻辑。处理器还包括与解码逻辑耦合的仿真模式感知后解码指令处理器逻辑。仿真模式感知后解码指令处理器逻辑是处理从指令解码的一个或多个控制信号。该指令是用于模拟第一条指令的一组或多条指令之一。当仿真模式下的仿真模式识别后解码指令处理器逻辑比未处于仿真模式时，一个或多个控制信号被不同地处理。还公开了其他装置以及方法和系统。

4. 发明申请

US20140189299A1 HETERGENEOUS PROCESSOR APPARATUS AND METHOD 有权
标题翻译：空气处理器装置和方法
公开(公告)号：US20140189299A1
公开(公告)日：2014-07-03
申请号：US13730565
申请日：2012-12-28
申请人： Paolo Narvaez , Ganapati N. Srinivasa , Eugene Gorbatov , Dheeraj R. Subbareddy , Mishali Naik , Alon Naveh , Abirami Prabhakaran , Eliezer Weissmann , David A. Koufaty , Paul Brett , Scott D. Hahn , Andrew J. Herdrich , Ravishankar Iyer , Nagabhushan Chitlur , Inder M. Sodhi , Gaurav Khanna , Russell J. Fenger
发明人： Paolo Narvaez , Ganapati N. Srinivasa , Eugene Gorbatov , Dheeraj R. Subbareddy , Mishali Naik , Alon Naveh , Abirami Prabhakaran , Eliezer Weissmann , David A. Koufaty , Paul Brett , Scott D. Hahn , Andrew J. Herdrich , Ravishankar Iyer , Nagabhushan Chitlur , Inder M. Sodhi , Gaurav Khanna , Russell J. Fenger
IPC分类号： G06F9/38
CPC分类号： G06F9/3891
摘要： A heterogeneous processor architecture is described. For example, a processor according to one embodiment of the invention comprises: a set of large physical processor cores; a set of small physical processor cores having relatively lower performance processing capabilities and relatively lower power usage relative to the large physical processor cores; virtual-to-physical (V-P) mapping logic to expose the set of large physical processor cores to software through a corresponding set of virtual cores and to hide the set of small physical processor core from the software.
摘要翻译：描述异构处理器架构。例如，根据本发明的一个实施例的处理器包括：一组大的物理处理器核心; 一组具有相对较低性能处理能力的小物理处理器核和相对于大型物理处理器核的相对较低的功率使用; 虚拟到物理（V-P）映射逻辑，以通过相应的一组虚拟核心将大型物理处理器核心集合暴露给软件，并从该软件中隐藏一组小型物理处理器核心。

5. 发明授权

US07330118B2 Apparatus and method capable of secure wireless configuration and provisioning 有权
标题翻译：能够确保无线配置和配置的装置和方法
公开(公告)号：US07330118B2
公开(公告)日：2008-02-12
申请号：US10977831
申请日：2004-10-28
申请人： Lenitra M. Durham , Scott D. Hahn , David M. Durham
发明人： Lenitra M. Durham , Scott D. Hahn , David M. Durham
IPC分类号： G08B13/14
CPC分类号： H04L63/0823 , G06F21/575
摘要： An embodiment of the present invention provides an apparatus, comprising an RFID tag interfaced with the apparatus, the RFID tag enables wireless provisioning and configuration of the apparatus and may be a passive read/write RFID tag. The apparatus may be, in one embodiment, a platform such as a client or server and the passive RFID tag may be interfaced with the platform such that the tag's EEPROM can also be read from or written to by the platform using a wired serial connection. The apparatus may further comprise a host processor with an operating system (OS) and an embedded microcontroller, the embedded microcontroller may have access to dynamic and non-volatile memory capable of operating independently of the host processor and OS and with direct access to a network interface, wherein the RFID tag may be read from or written to by either a RFID reader or the platform via a direct connection to the embedded processor.
摘要翻译：本发明的一个实施例提供了一种装置，其包括与该装置接口的RFID标签，该RFID标签能够进行设备的无线供应和配置，并且可以是无源的读/写RFID标签。在一个实施例中，该装置可以是诸如客户端或服务器的平台，并且无源RFID标签可以与平台接口，使得标签的EEPROM也可以使用有线串行连接从平台读取或写入。该装置还可以包括具有操作系统（OS）和嵌入式微控制器的主处理器，嵌入式微控制器可以访问能够独立于主处理器和OS并且直接访问网络的动态和非易失性存储器接口，其中RFID标签可以通过RFID读取器或平台通过与嵌入式处理器的直接连接来读取或写入RFID标签。

6. 发明授权

US06880005B1 Managing policy rules in a network 失效
标题翻译：管理网络中的策略规则
公开(公告)号：US06880005B1
公开(公告)日：2005-04-12
申请号：US09539927
申请日：2000-03-31
申请人： Carol A. Bell , Michael D. Shipley , Scott D. Hahn
发明人： Carol A. Bell , Michael D. Shipley , Scott D. Hahn
IPC分类号： G06F15/16 , H04L12/56
CPC分类号： H04L47/10
摘要： Policy rules are disseminated on a network and are received by one or more devices on the network. Each device is configured with a proxy agent that translates the policy data into a format that is meaningful to the device. The agent translates the policy rules into an access list that generates permit and deny filters that determine the access that the device is allowed on the network.
摘要翻译：策略规则在网络上传播，并由网络上的一个或多个设备接收。每个设备配置有代理代理，将代理策略数据转换为对设备有意义的格式。代理将策略规则转换为生成允许和拒绝过滤器的访问列表，以确定设备在网络上被允许的访问。

7. 发明申请

US20150095614A1 APPARATUS AND METHOD FOR EFFICIENT MIGRATION OF ARCHITECTURAL STATE BETWEEN PROCESSOR CORES 审中-公开
标题翻译：处理器之间建筑状态有效迁移的装置和方法
公开(公告)号：US20150095614A1
公开(公告)日：2015-04-02
申请号：US14040230
申请日：2013-09-27
申请人： Bret L. Toll , Scott D. Hahn , Jason W. Brandt , Thomas F. Toll
发明人： Bret L. Toll , Scott D. Hahn , Jason W. Brandt , Thomas F. Toll
IPC分类号： G06F9/38
CPC分类号： G06F9/3824 , G06F9/3851 , G06F9/4856
摘要： An apparatus and method are described for the efficient migration of architectural state between processor cores. For example, a processor according to one embodiment comprises: a first processing core having a first instruction execution pipeline including first register set for storing a first architectural state of a first thread being executed thereon; a second processing core having a second instruction execution pipeline including a second register set for storing a second architectural state of a second thread being executed thereon; and architectural state migration logic to perform a direct, simultaneous swap of the first architectural state from the first register set with the second architectural state from the second register set responsive to detecting that the execution of the first thread is to be migrated from the first core to the second core.
摘要翻译：描述了用于处理器核心之间架构状态的有效迁移的装置和方法。例如，根据一个实施例的处理器包括：具有第一指令执行流水线的第一处理核心，第一指令执行流水线包括用于存储在其上执行的第一线程的第一架构状态的第一寄存器集; 第二处理核心，具有第二指令执行流水线，该第二指令执行流水线包括第二寄存器组，用于存储在其上执行的第二线程的第二架构状态; 以及体系结构状态迁移逻辑，用于响应于检测到要从第一核心迁移第一线程的执行，执行来自第二架构状态的第一寄存器与第二寄存器集的第一架构状态的直接同时交换到第二个核心。

8. 发明申请

US20140281457A1 METHOD FOR BOOTING A HETEROGENEOUS SYSTEM AND PRESENTING A SYMMETRIC CORE VIEW 有权
标题翻译：用于打造异质系统并提供对称核心视图的方法
公开(公告)号：US20140281457A1
公开(公告)日：2014-09-18
申请号：US13854001
申请日：2013-03-29
申请人： Elierzer Weissmann , Rinat Rappoport , Michael Mishaeli , Hisham Shafi , Oron Lenz , Jason W. Brandt , Stephen A. Fischer , Bret L. Toll , Inder M. Sodhi , Alon Naveh , Ganapati N. Srinivasa , Ashish V. Choubal , Scott D. Hahn , David A. Koufaty , Russel J. Fenger , Gaurav Khanna , Eugene Gorbatov , Mishali Naik , Andrew J. Herdrich , Abirami Prabhakaran , Sanjeev S. Sahagirdar , Paul Brett , Paolo Narvaez , Andrew D. Henroid , Dheeraj R. Subbareddy
发明人： Elierzer Weissmann , Rinat Rappoport , Michael Mishaeli , Hisham Shafi , Oron Lenz , Jason W. Brandt , Stephen A. Fischer , Bret L. Toll , Inder M. Sodhi , Alon Naveh , Ganapati N. Srinivasa , Ashish V. Choubal , Scott D. Hahn , David A. Koufaty , Russel J. Fenger , Gaurav Khanna , Eugene Gorbatov , Mishali Naik , Andrew J. Herdrich , Abirami Prabhakaran , Sanjeev S. Sahagirdar , Paul Brett , Paolo Narvaez , Andrew D. Henroid , Dheeraj R. Subbareddy
IPC分类号： G06F9/44
CPC分类号： G06F9/4401 , G06F9/45558 , G06F9/5077 , G06F9/5094 , Y02D10/22 , Y02D10/36
摘要： A heterogeneous processor architecture and a method of booting a heterogeneous processor is described. A processor according to one embodiment comprises: a set of large physical processor cores; a set of small physical processor cores having relatively lower performance processing capabilities and relatively lower power usage relative to the large physical processor cores; and a package unit, to enable a bootstrap processor. The bootstrap processor initializes the homogeneous physical processor cores, while the heterogeneous processor presents the appearance of a homogeneous processor to a system firmware interface.
摘要翻译：描述异构处理器架构和启动异构处理器的方法。根据一个实施例的处理器包括：一组大的物理处理器核心; 一组具有相对较低性能处理能力的小物理处理器核和相对于大型物理处理器核的相对较低的功率使用; 以及一个包装单元，用于启用自举处理器。引导处理器初始化同构物理处理器内核，而异构处理器将均匀处理器的外观呈现给系统固件界面。

9. 发明申请

US20140189704A1 HETERGENEOUS PROCESSOR APPARATUS AND METHOD 有权
标题翻译：空气处理器装置和方法
公开(公告)号：US20140189704A1
公开(公告)日：2014-07-03
申请号：US13730539
申请日：2012-12-28
申请人： Paolo Narvaez , Ganapati N. Srinivasa , Eugene Gorbatov , Dheeraj R. Subbareddy , Mishali Naik , Alon Naveh , Abirami Prabhakaran , Eliezer Weissmann , David A. Koufaty , Paul Brett , Scott D. Hahn , Andrew J. Herdrich , Ravishankar Iyer , Nagabhushan Chitlur , Inder M. Sodhi , Gaurav Khanna , Russell J. Fenger
发明人： Paolo Narvaez , Ganapati N. Srinivasa , Eugene Gorbatov , Dheeraj R. Subbareddy , Mishali Naik , Alon Naveh , Abirami Prabhakaran , Eliezer Weissmann , David A. Koufaty , Paul Brett , Scott D. Hahn , Andrew J. Herdrich , Ravishankar Iyer , Nagabhushan Chitlur , Inder M. Sodhi , Gaurav Khanna , Russell J. Fenger
IPC分类号： G06F9/50
CPC分类号： G06F9/5044 , G06F9/45533 , G06F9/5077 , G06F9/5094 , G06F15/80 , Y02D10/22
摘要： A heterogeneous processor architecture is described. For example, a processor according to one embodiment of the invention comprises: a first set of one or more physical processor cores having first processing characteristics; a second set of one or more physical processor cores having second processing characteristics different from the first processing characteristics; virtual-to-physical (V-P) mapping logic to expose a plurality of virtual processors to software, the plurality of virtual processors to appear to the software as a plurality of homogeneous processor cores, the software to allocate threads to the virtual processors as if the virtual processors were homogeneous processor cores; wherein the V-P mapping logic is to map each virtual processor to a physical processor within the first set of physical processor cores or the second set of physical processor cores such that a thread allocated to a first virtual processor by software is executed by a physical processor mapped to the first virtual processor from the first set or the second set of physical processors.
摘要翻译：描述异构处理器架构。例如，根据本发明的一个实施例的处理器包括：具有第一处理特性的一个或多个物理处理器核心的第一组; 具有不同于所述第一处理特性的第二处理特性的第二组一个或多个物理处理器核; 虚拟到物理（VP）映射逻辑，以将多个虚拟处理器暴露给软件，所述多个虚拟处理器将软件呈现为多个同构的处理器核，所述软件将线程分配给虚拟处理器，如同虚拟处理器是同类处理器核心; 其中所述VP映射逻辑将每个虚拟处理器映射到所述第一物理处理器核心集合或所述第二物理处理器核心组内的物理处理器，使得通过软件分配给第一虚拟处理器的线程由物理处理器映射执行从第一组或第二组物理处理器到第一虚拟处理器。

10. 发明申请

US20140189377A1 APPARATUS AND METHOD FOR INTELLIGENTLY POWERING HETERGENEOU PROCESSOR COMPONENTS 有权
标题翻译：智能加热器加热器组件的装置和方法
公开(公告)号：US20140189377A1
公开(公告)日：2014-07-03
申请号：US13730493
申请日：2012-12-28
申请人： Dheeraj R. Subbareddy , Ganapati N. Srinivasa , Eugene Gorbatov , Scott D. Hahn , David A. Koufaty , Paul Brett , Abirami Prabhakaran
发明人： Dheeraj R. Subbareddy , Ganapati N. Srinivasa , Eugene Gorbatov , Scott D. Hahn , David A. Koufaty , Paul Brett , Abirami Prabhakaran
IPC分类号： G06F1/26
CPC分类号： G06F9/44 , G06F1/324 , G06F1/329 , G06F1/3296 , G06F9/5094 , G09G5/363 , G09G2330/021 , Y02D10/126 , Y02D10/172 , Y02D10/22 , Y02D10/24
摘要： An intelligent power allocation architecture for a processor. For example, one embodiment of a processor comprises: a plurality of processor components for performing a corresponding plurality of processor functions; a plurality of power planes, each power plane associated with one of the processor components; and a power control unit (PCU) to dynamically adjust power to each of the power planes based on user experience metrics, workload characteristics, and power constraints for a current use of the processor.
摘要翻译：用于处理器的智能功率分配架构。例如，处理器的一个实施例包括：用于执行相应的多个处理器功能的多个处理器组件; 多个电力平面，与所述处理器组件中的一个相关联的每个电力平面; 以及功率控制单元（PCU），用于基于用于当前使用处理器的用户体验度量，工作负载特性和功率约束来动态地调整每个功率平面的功率。

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