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1. 发明申请

US20100146314A1 Power aware software pipelining for hardware accelerators 有权
标题翻译：功率感知软件流水线用于硬件加速器
公开(公告)号：US20100146314A1
公开(公告)日：2010-06-10
申请号：US12704015
申请日：2010-02-11
申请人： Ron Gabor , Hong Jiang , Alon Naveh , Doron Rajwan , James Varga , Gady Yearim , Yuval Yosef
发明人： Ron Gabor , Hong Jiang , Alon Naveh , Doron Rajwan , James Varga , Gady Yearim , Yuval Yosef
IPC分类号： G06F1/32 , G06F1/26 , G06F9/30 , G06F9/38
CPC分类号： G06F1/3203
摘要： Forming a plurality of pipeline orderings, each pipeline ordering comprising one of a sequential, a parallel, or a sequential and parallel combination of a plurality of stages of a pipeline, analyzing the plurality of pipeline orderings to determine a total power of each of the orderings, and selecting one of the plurality of pipeline orderings based on the determined total power of each of the plurality of pipeline orderings.
摘要翻译：形成多个流水线排序，每个流水线排序包括流水线的多个阶段的顺序，并行或顺序和并行组合中的一个，分析多个流水线排序以确定每个排序的总功率并且基于所确定的多个流水线排序中的每一个的总功率来选择多个流水线排序中的一个。

2. 发明授权

US07391416B2 Fine tuning a sampling clock of analog signals having digital information for optimal digital display 有权
标题翻译：微调具有数字信息的模拟信号采样时钟，实现最佳数字显示
公开(公告)号：US07391416B2
公开(公告)日：2008-06-24
申请号：US10498979
申请日：2002-12-26
申请人： Gady Yearim
发明人： Gady Yearim
IPC分类号： G09G5/00
CPC分类号： G09G5/008
摘要： Method and system for fine tuning frequency and phase of a sampling clock of analog signals (R, G, B) having digital information, for sampling the analog signals within an optimal sampling period, enabling optimal display by a digital display device (92). Small amount of information from input signals is required for rapidly and accurately determining values of frequency and phase of the sampling clock. After measuring using a measurement system (96) and obtaining pixel values while sweeping phase values of signals using a phase locked loop (PLL) mechanism (48), there is determining values of two parameters, (i) error of an initial frequency value of the sampling clock (Rx clock), proportional to error of an initial phase locked loop (PLL) division factor value, and (ii) phase of the sampling clock, without need for making additional measurements based on these values, using a control unit (94).
摘要翻译：具有数字信息的模拟信号（R，G，B）的采样时钟的微调频率和相位的方法和系统，用于在最佳采样周期内对模拟信号进行采样，从而实现数字显示设备（92）的最佳显示。需要从输入信号得到的少量信息用于快速准确地确定采样时钟的频率和相位值。在使用测量系统（96）测量并且使用锁相环（PLL）机构（48）扫描信号的相位值时获得像素值，确定两个参数的值，（i）初始频率值的误差与初始锁相环（PLL）分频因子值的误差成比例的采样时钟（Rx时钟）和（ii）采样时钟的相位，而不需要使用控制单元（基于这些值）进行基于这些值的附加测量 94）。

3. 发明授权

US06191827B1 Electronic keystone correction for electronic devices with a visual display 失效
标题翻译：具有视觉显示功能的电子设备的电子梯形失真校正
公开(公告)号：US06191827B1
公开(公告)日：2001-02-20
申请号：US09201849
申请日：1998-12-01
申请人： Yosef Segman , Gady Yearim , Avy Strominger
发明人： Yosef Segman , Gady Yearim , Avy Strominger
IPC分类号： H04N323
CPC分类号： H04N3/2335
摘要： A method of electronic Keystone correction for electronic devices having visual displays which exhibit optical distortion on the display screen. The corrective method is based on computation and electronic (physical) manipulation of the pixels of a visual display screen grid, and features the principle steps of: 1) characterization of the size of an input image, 2) determination of the number of generated pixels in the output image, 3) determination of the real position of each pixel in the output image by performing an electronic distortion to the input image opposite to the optical distortion of the input image, 4) interpolation of the output value of all color components of each pixel of the input image, 5) correction of (non-uniform) edge effects at both ends of each line of pixels, 6) transmission of the output corrected image to the electronic display device, individually, pixel by pixel, or as complete set of corrected pixels of the image, and 7) display of the perfected corrected optical image. The method of this invention solves at least two universally known optical distortion problems involving trapezoidal distortion and computerized diagonal line drawing. Moreover, the method of this invention is applicable to real time domain of operation of electronic devices with visual displays.
摘要翻译：一种具有在显示屏幕上呈现光学失真的视觉显示器的电子设备的电子梯形校正方法。校正方法基于视觉显示屏网格像素的计算和电子（物理）操纵，其特征在于：1）表征输入图像的大小，2）确定所生成的像素数在输出图像中，3）通过对与输入图像的光学失真相反的输入图像执行电子失真来确定输出图像中的每个像素的实际位置，4）所有颜色分量的输出值的内插输入图像的每个像素，5）校正每行像素两端的（非均匀）边缘效果，6）逐个像素地将输出校正图像传输到电子显示装置，或者作为完整的图像的校正像素组，以及7）完美校正的光学图像的显示。本发明的方法解决了至少两个普遍已知的涉及梯形失真和计算机对角线绘图的光学失真问题。此外，本发明的方法适用于具有视觉显示器的电子设备的实时操作领域。

4. 发明授权

US08166320B2 Power aware software pipelining for hardware accelerators 有权
标题翻译：功率感知软件流水线用于硬件加速器
公开(公告)号：US08166320B2
公开(公告)日：2012-04-24
申请号：US12704015
申请日：2010-02-11
申请人： Ron Gabor , Hong Jiang , Alon Naveh , Doron Rajwan , James Varga , Gady Yearim , Yuval Yosef
发明人： Ron Gabor , Hong Jiang , Alon Naveh , Doron Rajwan , James Varga , Gady Yearim , Yuval Yosef
IPC分类号： G06F1/32 , G06F1/00 , G06F9/30
CPC分类号： G06F1/3203
摘要： Forming a plurality of pipeline orderings, each pipeline ordering comprising one of a sequential, a parallel, or a sequential and parallel combination of a plurality of stages of a pipeline, analyzing the plurality of pipeline orderings to determine a total power of each of the orderings, and selecting one of the plurality of pipeline orderings based on the determined total power of each of the plurality of pipeline orderings.
摘要翻译：形成多个流水线排序，每个流水线排序包括流水线的多个阶段的顺序，并行或顺序和并行组合中的一个，分析多个流水线排序以确定每个排序的总功率并且基于所确定的多个流水线排序中的每一个的总功率来选择多个流水线排序中的一个。

5. 发明申请

US20050020228A1 Fine tuning a sampling clock of analog signals having digital information for optimal digital display 有权
标题翻译：微调具有数字信息的模拟信号采样时钟，实现最佳数字显示
公开(公告)号：US20050020228A1
公开(公告)日：2005-01-27
申请号：US10498979
申请日：2002-12-26
申请人： Gady Yearim
发明人： Gady Yearim
IPC分类号： G09G3/20 , G09G5/00 , H04B1/06
CPC分类号： G09G5/008
摘要： Method and system for fine tuning frequency and phase of a sampling clock of analog signals (R, G, B) having digital information, for sampling the analog signals within an optimal sampling period, enabling optimal display by a digital display device (92). Small amount of information from input signals is required for rapidly and accurately determining values of frequency and phase of the sampling clock. After measuring using a measurement system (96) and obtaining pixel values while sweeping phase values of signals using a phase locked loop (PLL) mechanism (48), there is determining values of two parameters, (i) error of an initial frequency value of the sampling clock (Rx clock), proportional to error of an initial phase locked loop (PLL) division factor value, and (ii) phase of the sampling clock, without need for making additional measurements based on these values, using a control unit (94).
摘要翻译：具有数字信息的模拟信号（R，G，B）的采样时钟的微调频率和相位的方法和系统，用于在最佳采样周期内对模拟信号进行采样，从而实现数字显示设备（92）的最佳显示。需要从输入信号得到的少量信息用于快速准确地确定采样时钟的频率和相位值。在使用测量系统（96）测量并且使用锁相环（PLL）机构（48）扫描信号的相位值时获得像素值，确定两个参数的值，（i）初始频率值的误差与初始锁相环（PLL）分频因子值的误差成比例的采样时钟（Rx时钟）和（ii）采样时钟的相位，而不需要使用控制单元（基于这些值）进行基于这些值的附加测量 94）。

6. 发明申请

US20110013095A1 Portable Projector 审中-公开
标题翻译：便携式投影仪
公开(公告)号：US20110013095A1
公开(公告)日：2011-01-20
申请号：US12817500
申请日：2010-06-17
申请人： Meir Aloni , Gady Yearim , Elisha-Avraham Tal , Jacob Rand , Eyal Cremer
发明人： Meir Aloni , Gady Yearim , Elisha-Avraham Tal , Jacob Rand , Eyal Cremer
IPC分类号： H04N9/31 , H04N7/12
CPC分类号： G03B21/145
摘要： A projector and a system comprising a projector and a handheld device are described. In a preferred embodiment, a projector for projecting an image includes a back section and a front section. The back section has a bottom surface for resting on a supporting surface, and the front section has an optical window for projecting light indicative of the image. The front section is tilted with respect to the bottom surface of the back section to define a tilt angle. The system includes a video-output generating handheld device, and a display device controlled by control signals generated by the handheld device. The handheld device and the display device are interconnected with no more than one physical video signal connection.
摘要翻译：描述了投影仪和包括投影仪和手持装置的系统。在优选实施例中，用于投影图像的投影仪包括后部和前部。后部具有用于搁置在支撑表面上的底表面，并且前部具有用于投射指示图像的光的光学窗口。前部相对于后部的底面倾斜以限定倾斜角。该系统包括视频输出产生手持设备和由手持设备产生的控制信号控制的显示设备。手持设备和显示设备与不超过一个物理视频信号连接互连。

7. 发明授权

US07725745B2 Power aware software pipelining for hardware accelerators 有权
公开(公告)号：US07725745B2
公开(公告)日：2010-05-25
申请号：US11642128
申请日：2006-12-19
申请人： Ron Gabor , Hong Jiang , Alon Naveh , Doron Rajwan , James Varga , Gady Yearim , Yuval Yosef
发明人： Ron Gabor , Hong Jiang , Alon Naveh , Doron Rajwan , James Varga , Gady Yearim , Yuval Yosef
IPC分类号： G06F1/32 , G06F1/00 , G06F9/40
CPC分类号： G06F1/3203
摘要： Forming a plurality of pipeline orderings, each pipeline ordering comprising one of a sequential, a parallel, or a sequential and parallel combination of a plurality of stages of a pipeline, analyzing the plurality of pipeline orderings to determine a total power of each of the orderings, and selecting one of the plurality of pipeline orderings based on the determined total power of each of the plurality of pipeline orderings.

8. 发明申请

US20080148076A1 Power aware software pipelining for hardware accelerators 有权
标题翻译：功率感知软件流水线用于硬件加速器
公开(公告)号：US20080148076A1
公开(公告)日：2008-06-19
申请号：US11642128
申请日：2006-12-19
申请人： Ron Gabor , Hong Jiang , Alon Naveh , Doron Rajwan , James Varga , Gady Yearim , Yuval Yosef
发明人： Ron Gabor , Hong Jiang , Alon Naveh , Doron Rajwan , James Varga , Gady Yearim , Yuval Yosef
IPC分类号： G06F1/28
CPC分类号： G06F1/3203
摘要： Forming a plurality of pipeline orderings, each pipeline ordering comprising one of a sequential, a parallel, or a sequential and parallel combination of a plurality of stages of a pipeline, analyzing the plurality of pipeline orderings to determine a total power of each of the orderings, and selecting one of the plurality of pipeline orderings based on the determined total power of each of the plurality of pipeline orderings.
摘要翻译：形成多个流水线排序，每个流水线排序包括流水线的多个阶段的顺序，并行或顺序和并行组合中的一个，分析多个流水线排序以确定每个排序的总功率并且基于所确定的多个流水线排序中的每一个的总功率来选择多个流水线排序中的一个。

9. 发明申请

US20060107294A1 Integrated video processing circuit and method for providing a displayed visual user interface for the display, selection and setup of video input sources 审中-公开
标题翻译：用于提供用于显示，选择和设置视频输入源的显示的可视用户界面的集成视频处理电路和方法
公开(公告)号：US20060107294A1
公开(公告)日：2006-05-18
申请号：US11274688
申请日：2005-11-14
申请人： Ze'ev Rivlin , Yair Alpern , Gady Yearim
发明人： Ze'ev Rivlin , Yair Alpern , Gady Yearim
IPC分类号： H04N7/18 , H04N5/445 , G06F3/00
CPC分类号： G11B27/031 , H04N5/45 , H04N5/50 , H04N5/775 , H04N21/42204 , H04N21/4316 , H04N21/43615 , H04N21/440263 , H04N21/485
摘要： An integrated video processing circuit (VPC) and method for providing a displayed visual user interface for the display, selection and setup of video input sources on a shared display. A VPC processes video from two or more video input sources, where some subset of the two or more video input sources receive video from a respective device. The VPC creates on the display a visual user interface consisting of live or interval-updated video providing simultaneously (e.g., in a mosaic of windows) a visual indication of the status of some or all of the video input sources. The VPC allows for the easy selection and setup of the respective devices via the user interface on the display and an input device (e.g., a remote control device).
摘要翻译：一种用于在共享显示器上显示，选择和设置视频输入源的显示视觉用户界面的集成视频处理电路（VPC）和方法。 VPC处理来自两个或更多个视频输入源的视频，其中两个或更多个视频输入源的某些子集从相应的设备接收视频。 VPC在显示器上创建一个视觉用户界面，其包括实时或间隔更新的视频，同时（例如，以马赛克窗口）提供一些或所有视频输入源的状态的视觉指示。 VPC允许通过显示器上的用户界面和输入设备（例如，遥控设备）容易地选择和设置各个设备。

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