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1. 发明申请

US20160246597A1 APPARATUS AND METHOD FOR LOW-LATENCY INVOCATION OF ACCELERATORS 审中-公开
标题翻译：低速延迟加速器的装置和方法
公开(公告)号：US20160246597A1
公开(公告)日：2016-08-25
申请号：US15145748
申请日：2016-05-03
申请人： Oren Ben-Kiki , llan Pardo , Robert Valentine , Eliezer Weissmann , Dror Markovich , Yuval Yosef
发明人： Oren Ben-Kiki , llan Pardo , Robert Valentine , Eliezer Weissmann , Dror Markovich , Yuval Yosef
IPC分类号： G06F9/30
CPC分类号： G06F9/3802 , G06F9/3004 , G06F9/30043 , G06F9/30076 , G06F9/30101 , G06F9/30145 , G06F9/3016 , G06F9/384 , G06F9/3877 , G06F9/3879 , G06F9/3881 , G06F9/54 , G06F11/0721 , G06F11/0724 , G06F11/0772 , G06F12/0875 , G06F2212/452
摘要： An apparatus and method are described for providing low-latency invocation of accelerators. For example, a processor according to one embodiment comprises: a command register for storing command data identifying a command to be executed; a result register to store a result of the command or data indicating a reason why the commend could not be executed; execution logic to execute a plurality of instructions including an accelerator invocation instruction to invoke one or more accelerator commands, the accelerator invocation instruction to store command data specifying the command within the command register; one or more accelerators to read the command data from the command register and responsively attempt to execute the command identified by the command data, wherein if the one or more accelerators successfully execute the command, the one or more accelerators are to store result data comprising the results of the command in the result register; and if the one or more accelerators cannot successfully execute the command, the one or more accelerators are to store result data indicating a reason why the command cannot be executed, wherein the execution logic is to temporarily halt execution until the accelerator completes execution or is interrupted, wherein the accelerator includes logic to store its state if interrupted so that it can continue execution at a later time.
摘要翻译：描述了一种用于提供加速器的低延迟调用的装置和方法。例如，根据一个实施例的处理器包括：命令寄存器，用于存储标识要执行的命令的命令数据; 用于存储命令结果的结果寄存器或指示不能执行推荐的原因的数据; 执行逻辑以执行包括用于调用一个或多个加速器命令的加速器调用指令的多个指令，所述加速器调用指令将指定所述命令的命令数据存储在所述命令寄存器内; 一个或多个加速器，用于从命令寄存器读取命令数据并响应于尝试执行由命令数据识别的命令，其中如果一个或多个加速器成功地执行命令，则一个或多个加速器将存储包括结果寄存器中的命令结果; 并且如果一个或多个加速器不能成功地执行命令，则一个或多个加速器将存储指示不能执行该命令的原因的结果数据，其中执行逻辑将暂停执行，直到加速器完成执行或被中断其中所述加速器包括用于存储其状态的逻辑，如果被中断，使得其可以在稍后的时间继续执行。

2. 发明申请

US20140189712A1 Memory Address Collision Detection Of Ordered Parallel Threads With Bloom Filters 有权
标题翻译：存储器地址与布隆过滤器的有序并行线程的碰撞检测
公开(公告)号：US20140189712A1
公开(公告)日：2014-07-03
申请号：US13730704
申请日：2012-12-28
申请人： Enrique DE LUCAS , Pedro MARCUELLO , Oren BEN-KIKI , Ilan PARDO , Yuval YOSEF
发明人： Enrique DE LUCAS , Pedro MARCUELLO , Oren BEN-KIKI , Ilan PARDO , Yuval YOSEF
IPC分类号： G06F9/46
CPC分类号： G06F9/30043 , G06F9/3009 , G06F9/3834 , G06F9/3851 , G06F9/3857 , G06F9/3867
摘要： A semiconductor chip is described having a load collision detection circuit comprising a first bloom filter circuit. The semiconductor chip has a store collision detection circuit comprising a second bloom filter circuit. The semiconductor chip has one or more processing units capable of executing ordered parallel threads coupled to the load collision detection circuit and the store collision detection circuit. The load collision detection circuit and the store collision detection circuit is to detect younger stores for load operations of said threads and younger loads for store operations of said threads.
摘要翻译：描述了一种具有负载碰撞检测电路的半导体芯片，该电路包括第一起爆滤波器电路。半导体芯片具有存储冲突检测电路，该电路包括第二盛盛滤波器电路。该半导体芯片具有能够执行与负载碰撞检测电路和存储冲突检测电路耦合的有序并行线程的一个或多个处理单元。负载碰撞检测电路和存储碰撞检测电路是检测较年轻的存储器用于所述线程和较小负载的负载操作，用于所述线程的存储操作。

3. 发明申请

US20070157211A1 Instruction set architecture-based inter-sequencer communications with a heterogeneous resource 有权
标题翻译：与异构资源的指令集基于架构的间隔器通信
公开(公告)号：US20070157211A1
公开(公告)日：2007-07-05
申请号：US11321779
申请日：2005-12-29
申请人： Hong Wang , John Shen , Hong Jiang , Richard Hankins , Per Hammarlund , Dion Rodgers , Gautham Chinya , Baiju Patel , Shiv Kaushik , Bryant Bigbee , Gad Sheaffer , Yoav Talgam , Yuval Yosef , James Held
发明人： Hong Wang , John Shen , Hong Jiang , Richard Hankins , Per Hammarlund , Dion Rodgers , Gautham Chinya , Baiju Patel , Shiv Kaushik , Bryant Bigbee , Gad Sheaffer , Yoav Talgam , Yuval Yosef , James Held
IPC分类号： G06F9/46
CPC分类号： G06F9/30145 , G06F9/30 , G06F9/30181 , G06F9/3877 , G06F9/3879 , G06T1/20
摘要： In one embodiment, the present invention includes a method for directly communicating between an accelerator and an instruction sequencer coupled thereto, where the accelerator is a heterogeneous resource with respect to the instruction sequencer. An interface may be used to provide the communication between these resources. Via such a communication mechanism a user-level application may directly communicate with the accelerator without operating system support. Further, the instruction sequencer and the accelerator may perform operations in parallel. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括一种用于在加速器和与其耦合的指令定序器之间直接通信的方法，其中加速器相对于指令定序器是异质资源。可以使用接口来提供这些资源之间的通信。通过这种通信机制，用户级应用可以直接与加速器进行通信，而无需操作系统支持。此外，指令定序器和加速器可以并行地执行操作。描述和要求保护其他实施例。

4. 发明申请

US20050259682A1 Broadcast system 审中-公开
标题翻译：广播系统
公开(公告)号：US20050259682A1
公开(公告)日：2005-11-24
申请号：US10182753
申请日：2001-02-02
申请人： Yuval Yosef , Haim Neerman , Doron Rajwan , Edan Ayal
发明人： Yuval Yosef , Haim Neerman , Doron Rajwan , Edan Ayal
IPC分类号： H04J3/16 , H04L12/18 , H04L29/08
CPC分类号： H04L12/1859 , H04L12/18 , H04L67/2823 , H04L67/2828 , H04L67/2842
摘要： A method of emulating an interactive connection, comprising: generating a request for interactive data from an interactive server, at a client; intercepting said request by an agent; responsive to said request, retrieving at least some of said data from a continuous retransmission of said data, by said agent; and displaying said data including said retrieved data at said client.
摘要翻译：一种模拟交互式连接的方法，包括：在客户端处产生来自交互式服务器的交互式数据的请求; 由代理人截取该请求; 响应于所述请求，由所述代理从所述数据的连续重传中检索所述数据中的至少一些; 以及在所述客户端显示包括所述检索的数据的所述数据。

5. 发明授权

US10185566B2 Migrating tasks between asymmetric computing elements of a multi-core processor 有权
公开(公告)号：US10185566B2
公开(公告)日：2019-01-22
申请号：US13994142
申请日：2012-04-27
申请人： Alon Naveh , Yuval Yosef , Eliezer Weissmann , Anil Aggarwal , Efraim Rotem , Avi Mendelson , Ronny Ronen , Boris Ginzburg , Michael Mishaeli , Scott D. Hahn , David A. Koufaty , Ganapati Srinivasa , Guy Therien
发明人： Alon Naveh , Yuval Yosef , Eliezer Weissmann , Anil Aggarwal , Efraim Rotem , Avi Mendelson , Ronny Ronen , Boris Ginzburg , Michael Mishaeli , Scott D. Hahn , David A. Koufaty , Ganapati Srinivasa , Guy Therien
IPC分类号： G06F9/30 , G06F9/48 , G06F9/50
摘要： In one embodiment, the present invention includes a multicore processor having first and second cores to independently execute instructions, the first core visible to an operating system (OS) and the second core transparent to the OS and heterogeneous from the first core. A task controller, which may be included in or coupled to the multicore processor, can cause dynamic migration of a first process scheduled by the OS to the first core to the second core transparently to the OS. Other embodiments are described and claimed.

6. 发明申请

US20140189332A1 APPARATUS AND METHOD FOR LOW-LATENCY INVOCATION OF ACCELERATORS 有权
标题翻译：低速延迟加速器的装置和方法
公开(公告)号：US20140189332A1
公开(公告)日：2014-07-03
申请号：US13729915
申请日：2012-12-28
申请人： Oren Ben-Kiki , Ilan Pardo , Robert Valentine , Eliezer Weissmann , Dror Markovich , Yuval Yosef
发明人： Oren Ben-Kiki , Ilan Pardo , Robert Valentine , Eliezer Weissmann , Dror Markovich , Yuval Yosef
IPC分类号： G06F9/30
CPC分类号： G06F9/3802 , G06F9/3004 , G06F9/30043 , G06F9/30076 , G06F9/30101 , G06F9/30145 , G06F9/3016 , G06F9/384 , G06F9/3877 , G06F9/3879 , G06F9/3881 , G06F9/54 , G06F11/0721 , G06F11/0724 , G06F11/0772 , G06F12/0875 , G06F2212/452
摘要： An apparatus and method are described for providing low-latency invocation of accelerators. For example, a processor according to one embodiment comprises: a command register for storing command data identifying a command to be executed; a result register to store a result of the command or data indicating a reason why the command could not be executed; execution logic to execute a plurality of instructions including an accelerator invocation instruction to invoke one or more accelerator commands; and one or more accelerators to read the command data from the command register and responsively attempt to execute the command identified by the command data.
摘要翻译：描述了一种用于提供加速器的低延迟调用的装置和方法。例如，根据一个实施例的处理器包括：命令寄存器，用于存储标识要执行的命令的命令数据; 用于存储命令结果的结果寄存器或表示无法执行命令的原因的数据; 执行逻辑以执行包括调用一个或多个加速器命令的加速器调用指令的多个指令; 以及一个或多个加速器，用于从命令寄存器读取命令数据，并且响应地尝试执行由命令数据识别的命令。

7. 发明申请

US20120056988A1 3-D CAMERA 审中-公开
标题翻译： 3-D相机
公开(公告)号：US20120056988A1
公开(公告)日：2012-03-08
申请号：US12876818
申请日：2010-09-07
申请人： David Stanhill , Omri Govrin , Yuval Yosef , Eli Turiel
发明人： David Stanhill , Omri Govrin , Yuval Yosef , Eli Turiel
IPC分类号： H04N13/02 , H04N9/04
CPC分类号： H04N13/271 , H04N13/254
摘要： A 3-D camera is disclosed. The 3-D camera includes an optical system, a front-end block, and a processor. The front-end block further includes a combined image sensor to generate an image, which includes color information and near infra-red information of a captured object and a near infra-red projector to generate one or more patterns. The processor is to generate a color image and a near infra-red image from the image and then generate a depth map using the near infra-red image and the one or more patterns from a near infra-red projector. The processor is to further generate a full three dimensional color model based on the color image and the depth map, which may be aligned with each other.
摘要翻译：公开了一种3-D照相机。 3-D摄像机包括光学系统，前端块和处理器。前端块还包括组合图像传感器以产生图像，其包括被捕获对象的颜色信息和近红外信息以及近红外线投影仪以生成一个或多个图案。处理器将从图像生成彩色图像和近红外图像，然后使用近红外图像和近红外投影仪的一个或多个图案生成深度图。处理器是基于可以彼此对准的彩色图像和深度图进一步产生完整的三维颜色模型。

8. 发明授权

US08914618B2 Instruction set architecture-based inter-sequencer communications with a heterogeneous resource 有权
标题翻译：与异构资源的指令集基于架构的间隔器通信
公开(公告)号：US08914618B2
公开(公告)日：2014-12-16
申请号：US11321779
申请日：2005-12-29
申请人： Hong Wang , John Shen , Hong Jiang , Richard Hankins , Per Hammarlund , Dion Rodgers , Gautham Chinya , Baiju Patel , Shiv Kaushik , Bryant Bigbee , Gad Sheaffer , Yoav Talgam , Yuval Yosef , James P. Held
发明人： Hong Wang , John Shen , Hong Jiang , Richard Hankins , Per Hammarlund , Dion Rodgers , Gautham Chinya , Baiju Patel , Shiv Kaushik , Bryant Bigbee , Gad Sheaffer , Yoav Talgam , Yuval Yosef , James P. Held
IPC分类号： G06F9/30 , G06F15/76 , G06F9/38
CPC分类号： G06F9/30145 , G06F9/30 , G06F9/30181 , G06F9/3877 , G06F9/3879 , G06T1/20
摘要： In one embodiment, the present invention includes a method for directly communicating between an accelerator and an instruction sequencer coupled thereto, where the accelerator is a heterogeneous resource with respect to the instruction sequencer. An interface may be used to provide the communication between these resources. Via such a communication mechanism a user-level application may directly communicate with the accelerator without operating system support. Further, the instruction sequencer and the accelerator may perform operations in parallel. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括一种用于在加速器和与其耦合的指令定序器之间直接通信的方法，其中加速器相对于指令定序器是异质资源。可以使用接口来提供这些资源之间的通信。通过这种通信机制，用户级应用可以直接与加速器进行通信，而无需操作系统支持。此外，指令定序器和加速器可以并行地执行操作。描述和要求保护其他实施例。

9. 发明申请

US20140189317A1 APPARATUS AND METHOD FOR A HYBRID LATENCY-THROUGHPUT PROCESSOR 有权
标题翻译：混合式延迟加工器的装置和方法
公开(公告)号：US20140189317A1
公开(公告)日：2014-07-03
申请号：US13730055
申请日：2012-12-28
申请人： Oren Ben-Kiki , Yuval Yosef , Ilan Pardo , Dror Markovich
发明人： Oren Ben-Kiki , Yuval Yosef , Ilan Pardo , Dror Markovich
IPC分类号： G06F9/30
CPC分类号： G06F9/3851 , G06F9/30079 , G06F9/3836 , G06F9/3855 , G06F9/3861 , G06F9/3877 , G06F9/46 , G06F15/7867 , G06F15/7892 , G06F15/80
摘要： An apparatus and method are described for executing both latency-optimized execution logic and throughput-optimized execution logic on a processing device. For example, a processor according to one embodiment comprises: latency-optimized execution logic to execute a first type of program code; throughput-optimized execution logic to execute a second type of program code, wherein the first type of program code and the second type of program code are designed for the same instruction set architecture; logic to identify the first type of program code and the second type of program code within a process and to distribute the first type of program code for execution on the latency-optimized execution logic and the second type of program code for execution on the throughput-optimized execution logic.
摘要翻译：描述了用于在处理设备上执行延迟优化的执行逻辑和吞吐量优化的执行逻辑的装置和方法。例如，根据一个实施例的处理器包括：执行第一类型的程序代码的等待时间优化的执行逻辑; 吞吐量优化执行逻辑以执行第二类型的程序代码，其中所述第一类型的程序代码和所述第二类型的程序代码被设计用于相同的指令集架构; 识别过程中的第一类型的程序代码和第二类型的程序代码的逻辑，并且将用于执行的第一类型的程序代码分配在延迟优化的执行逻辑和第二类型的程序代码上以便在吞吐量 - 优化的执行逻辑。

10. 发明申请

US20140189300A1 Processing Core Having Shared Front End Unit 审中-公开
标题翻译：具有共享前端单元的处理核心
公开(公告)号：US20140189300A1
公开(公告)日：2014-07-03
申请号：US13730719
申请日：2012-12-28
申请人： Name ILAN PARDO , DROR MARKOVICH , OREN BEN-KIKI , YUVAL YOSEF
发明人： Name ILAN PARDO , DROR MARKOVICH , OREN BEN-KIKI , YUVAL YOSEF
IPC分类号： G06F15/76
CPC分类号： G06F9/3891 , G06F9/30123 , G06F9/3802 , G06F9/3818 , G06F9/3851
摘要： A processor having one or more processing cores is described. Each of the one or more processing cores has front end logic circuitry and a plurality of processing units. The front end logic circuitry is to fetch respective instructions of threads and decode the instructions into respective micro-code and input operand and resultant addresses of the instructions. Each of the plurality of processing units is to be assigned at least one of the threads, is coupled to said front end unit, and has a respective buffer to receive and store microcode of its assigned at least one of the threads. Each of the plurality of processing units also comprises: i) at least one set of functional units corresponding to a complete instruction set offered by the processor, the at least one set of functional units to execute its respective processing unit's received microcode; ii) registers coupled to the at least one set of functional units to store operands and resultants of the received microcode; iii) data fetch circuitry to fetch input operands for the at least one functional units' execution of the received microcode.
摘要翻译：描述具有一个或多个处理核的处理器。一个或多个处理核心中的每一个具有前端逻辑电路和多个处理单元。前端逻辑电路是提取线程的相应指令，并将指令解码为相应的微码和指令的输入操作数和结果地址。多个处理单元中的每一个将被分配至少一个线程，耦合到所述前端单元，并且具有相应的缓冲器以接收和存储其分配的至少一个线程的微代码。所述多个处理单元中的每一个还包括：i）至少一组对应于由所述处理器提供的完整指令集的功能单元，所述至少一组功能单元执行其各自处理单元的接收到的微代码; ii）耦合到所述至少一组功能单元的寄存器，以存储所接收的微代码的操作数和结果; iii）数据获取电路，用于获取至少一个功能单元执行所接收的微代码的输入操作数。

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