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1. 发明授权

US6118699A Semiconductor memory device using MONOS type nonvolatile memory cell 失效
标题翻译：半导体存储器件采用MONOS型非易失性存储单元
公开(公告)号：US6118699A
公开(公告)日：2000-09-12
申请号：US352838
申请日：1999-07-13
申请人： Yuuichi Tatsumi , Noriaki Suzuki , Hidenobu Minagawa , Kazuhiko Satou , Hitoshi Ohta
发明人： Yuuichi Tatsumi , Noriaki Suzuki , Hidenobu Minagawa , Kazuhiko Satou , Hitoshi Ohta
IPC分类号： H01L27/115 , G11C16/04
CPC分类号： G11C16/0416 , H01L27/115
摘要： That surface portion of a semiconductor substrate which is adjacent to a buried source region formed in the substrate is covered with an offset side wall to suppress expansion of a channel beneath the offset side wall. In addition, buried source regions in the form of offset side walls are formed on the two sides of a drain region having one non-offset side wall to prevent a write or read error in unselected memory cell transistors on both sides of a selected memory transistor either in a data write or in a data read.
摘要翻译：与形成在基板中的埋入源极区域相邻的半导体基板的表面部分被偏移侧壁覆盖，以抑制偏移侧壁下方的通道的膨胀。此外，在具有一个非偏移侧壁的漏极区域的两侧上形成有偏移侧壁形式的掩埋源极区域，以防止选定存储晶体管两侧的未选择的存储单元晶体管中的写入或读取错误在数据写入或数据读取中。

2. 发明授权

US5175704A Nonvolatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US5175704A
公开(公告)日：1992-12-29
申请号：US607468
申请日：1990-10-31
申请人： Hidenobu Minagawa , Yuuichi Tatsumi , Hiroshi Iwahashi , Masamichi Asano , Hiroto Nakai , Mizuho Imai
发明人： Hidenobu Minagawa , Yuuichi Tatsumi , Hiroshi Iwahashi , Masamichi Asano , Hiroto Nakai , Mizuho Imai
IPC分类号： G11C16/10 , G11C16/24 , G11C16/30 , G11C16/34
CPC分类号： G11C16/10 , G11C16/24 , G11C16/30 , G11C16/34
摘要： In a nonvolatile semiconductor memory device, a wiring layer is connected between a power source and a memory cell. Resistance of the wiring layer is larger than the on-resistance of a load transistor, so that the load transistor substantially determines the load characteristic. Therefore, the load characteristic curve is more gentle in inclination and more rectilinear in shape. This makes the data writing operation stable against a variance in the channel lengths of manufactured transistors forming the memory cells.
摘要翻译：在非易失性半导体存储器件中，布线层连接在电源和存储单元之间。布线层的电阻大于负载晶体管的导通电阻，负载晶体管基本上决定负载特性。因此，载荷特性曲线在倾斜度上更为平缓，形状更为直线。这使得数据写入操作对于形成存储单元的制造的晶体管的沟道长度的变化是稳定的。

3. 发明授权

US4967394A Semiconductor memory device having a test cell array 失效
标题翻译：具有测试单元阵列的半导体存储器件
公开(公告)号：US4967394A
公开(公告)日：1990-10-30
申请号：US241748
申请日：1988-09-08
申请人： Hidenobu Minagawa , Yuuichi Tatsumi , Hiroshi Iwahashi , Masamichi Asano , Mizuho Imai
发明人： Hidenobu Minagawa , Yuuichi Tatsumi , Hiroshi Iwahashi , Masamichi Asano , Mizuho Imai
IPC分类号： G11C16/08 , G11C16/28 , G11C16/32 , G11C16/34 , G11C29/24 , G11C29/50 , G11C29/52
CPC分类号： G11C29/50012 , G11C16/08 , G11C16/28 , G11C16/32 , G11C16/34 , G11C29/24 , G11C29/50 , G11C29/52 , G11C16/04
摘要： A semiconductor memory device in which data can be read out in response to an address signal comprises power source lines, a plurality of row and column conductive lines, a memory cell array including nonvolatile memory cells arranged in a matrix form of rows and columns and respectively connected to the plurality of row and column lines and the power source lines, a first selector circuit for generating a signal for selecting the row conductive lines in response to an address signal, a dummy row line, and a dummy memory cells each having a source, a drain and a control gate connected to the dummy row line. In the semiconductor memory device, one of paths between the source and the power source line and between the drain and the corresponding row line is closed and the other path is opened, and it further includes a second selector circuit for selectively generating a line selection signal for selecting one of the row conductive lines in response to an address signal and a dummy selection signal for selecting the dummy row line in response to the same address signal.

4. 发明授权

US4882507A Output circuit of semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件的输出电路
公开(公告)号：US4882507A
公开(公告)日：1989-11-21
申请号：US226307
申请日：1988-07-29
申请人： Yuuichi Tatsumi , Hidenobu Minagawa , Hiroshi Iwahashi , Masamichi Asano , Mizuho Imai
发明人： Yuuichi Tatsumi , Hidenobu Minagawa , Hiroshi Iwahashi , Masamichi Asano , Mizuho Imai
IPC分类号： G11C11/417 , G11C7/10 , G11C7/22 , G11C11/409 , G11C17/18 , H03K17/16 , H03K17/687 , H03K19/003 , H03K19/0175 , H03K19/0185
CPC分类号： G11C7/1057 , G11C7/1051 , G11C7/22 , H03K19/00361
摘要： A semiconductor integrated circuit includes an output circuit and a control circuit for controlling the output circuit. The control circuit controls the output circuit so as to charge or discharge a preset node in the output circuit at a rate different from an ordinary charging or discharging rate for a preset period of time after a control signal has been changed in level.

5. 发明授权

US4858192A Semiconductor memory device with redundancy circuit 失效
标题翻译：具有冗余电路的半导体存储器件
公开(公告)号：US4858192A
公开(公告)日：1989-08-15
申请号：US225510
申请日：1988-07-28
申请人： Yuuichi Tatsumi , Hidenobu Minagawa , Hiroshi Iwahashi , Masamichi Asano , Mizuho Imai
发明人： Yuuichi Tatsumi , Hidenobu Minagawa , Hiroshi Iwahashi , Masamichi Asano , Mizuho Imai
IPC分类号： G11C17/00 , G11C16/06 , G11C29/00 , G11C29/04
CPC分类号： G11C29/781
摘要： A semiconductor memory device has a redundancy circuit for compensating a defective bit when it occurs in the main memory cells. The redundancy circuit includes spare memory cells, a spare row decoder for selecting the spare memory cells, a first circuit section for inhibiting the use of the main row decoder when the spare row decoder is used, and a second circuit section for selecting the spare row decoder when an address specifying the main row line connected to the defective memory cell is denoted.
摘要翻译：半导体存储器件具有用于在发生在主存储器单元中时补偿有缺陷的位的冗余电路。冗余电路包括备用存储单元，用于选择备用存储单元的备用排解码器，当使用备用行解码器时禁止使用主行解码器的第一电路部分和用于选择备用行的第二电路部分解码器，当指定连接到有缺陷的存储单元的主行线的地址被表示时。

6. 发明授权

US5010520A Nonvolatile semiconductor memory device with stabilized data write characteristic 失效
标题翻译：具有稳定数据写特性的非易失性半导体存储器件
公开(公告)号：US5010520A
公开(公告)日：1991-04-23
申请号：US224953
申请日：1988-07-27
申请人： Hidenobu Minagawa , Yuuichi Tatsumi , Hiroshi Iwahashi , Masamichi Asano , Hiroto Nakai , Mizuho Imai
发明人： Hidenobu Minagawa , Yuuichi Tatsumi , Hiroshi Iwahashi , Masamichi Asano , Hiroto Nakai , Mizuho Imai
IPC分类号： G11C16/10 , G11C16/24 , G11C16/30 , G11C16/34
CPC分类号： G11C16/34 , G11C16/10 , G11C16/24 , G11C16/30
摘要： In a nonvolatile semiconductor memory device, a wiring layer is connected between a power source and a memory cell. Resistance of the wiring layer is larger than the on-resistance of a load transistor, so that the load transistor substantially determines the load characteristic. Therefore, the load characteristic curve is more gentle in inclination and more rectilinear in shape. This makes the data writing operation stable against a variance in the channel lengths of manufactured transistors forming the memory cells.

7. 发明授权

US4916334A High voltage booster circuit for use in EEPROMs 失效
标题翻译：用于EEPROM的高压升压电路
公开(公告)号：US4916334A
公开(公告)日：1990-04-10
申请号：US226312
申请日：1988-07-29
申请人： Hidenobu Minagawa , Yuuichi Tatsumi , Hiroshi Iwahashi , Masamichi Asano , Mizuho Imai
发明人： Hidenobu Minagawa , Yuuichi Tatsumi , Hiroshi Iwahashi , Masamichi Asano , Mizuho Imai
IPC分类号： G11C16/30 , H02M3/07 , H03K5/02
CPC分类号： G11C16/30 , H02M3/07 , H03K5/023
摘要： A semiconductor integrated circuit includes a CMOS circuit operated on a voltage of a first voltage level to set an output node thereof to a voltage of the first voltage level or a reference voltage; an output circuit for controlling supply of a voltage of a second voltage level which is higher than the first voltage level to a signal output node; and an isolation MOS transistor having a current path connected between the output node of the CMOS circuit and the signal output node and a gate connected to receive a control signal. The output node of the CMOS circuit is set to the reference voltage with the conduction resistance of the isolation MOS transistor kept high after the lapse of period in which the voltage of the second voltage level is kept supplied to the signal output node. After this, the conduction resistance of the isolation MOS transistor is reduced in response to the control signal.
摘要翻译：半导体集成电路包括以第一电压电平工作的CMOS电路，以将其输出节点设置为第一电压电平或参考电压的电压; 输出电路，用于控制向信号输出节点提供高于第一电压电平的第二电压电平的电压; 以及隔离MOS晶体管，其具有连接在CMOS电路的输出节点和信号输出节点之间的电流路径以及连接以接收控制信号的栅极。 CMOS电路的输出节点被设定为参考电压，其中隔离MOS晶体管的导通电阻保持高电平，其中第二电压电平的电压被保持提供给信号输出节点。此后，隔离MOS晶体管的导通电阻响应于控制信号而减小。

8. 发明授权

US5138579A Semiconductor memory device having transfer gates which prevent high voltages from being applied to memory and dummy cells in the reading operation 失效
标题翻译：具有在读取操作中防止高电压施加到存储器和虚设单元的传输门的半导体存储器件
公开(公告)号：US5138579A
公开(公告)日：1992-08-11
申请号：US632613
申请日：1990-12-26
申请人： Yuuichi Tatsumi , Hidenobu Minagawa , Hiroshi Iwahashi , Masamichi Asano , Mizuho Imai
发明人： Yuuichi Tatsumi , Hidenobu Minagawa , Hiroshi Iwahashi , Masamichi Asano , Mizuho Imai
IPC分类号： G11C7/00 , G11C16/06 , G11C16/28 , G11C17/00
CPC分类号： G11C16/28
摘要： A semiconductor memory device includes word lines selectively driven by a signal from a row decoder, memory cells connected to word lines, first and second data lines, a bit line connected to receive data from the memory cell and to supply received data to the first data lines, dummy cells connected to word lines, first and second dummy data lines, a dummy bit lines connected to receive data from the dummy memory cell and to supply received data to the first dummy data line, a data sensing circuit for generating an output signal corresponding to a potential difference between the second data line and second dummy data line, a first MOS transistor connected between the first and second data lines, a first load circuit for charging the second data line, a second MOS transistor connected between the first and second dummy data lines, and a second load circuit for charging the second dummy data lines. The memory device further includes a first equalizer circuit connected between the second data line and dummy data line and equalizing potentials at both ends during a predetermined period of time after the semiconductor memory device is set in the active mode, and a second equalizer circuit connected between the data line and dummy data line and equalizing potential as at both ends during a predetermined period of time after the memory device is set in the active mode.
摘要翻译：半导体存储器件包括由来自行解码器的信号选择性地驱动的字线，连接到字线的存储器单元，第一和第二数据线，连接到从存储器单元接收数据并将接收到的数据提供给第一数据的位线连接到字线的虚拟单元，第一和第二虚拟数据线，连接成从虚拟存储单元接收数据并将接收到的数据提供给第一虚拟数据线的虚拟位线;数据感测电路，用于产生输出信号对应于第二数据线和第二虚拟数据线之间的电位差，连接在第一和第二数据线之间的第一MOS晶体管，用于对第二数据线充电的第一负载电路，连接在第一和第二数据线之间的第二MOS晶体管虚拟数据线，以及用于对第二虚拟数据线进行充电的第二负载电路。存储装置还包括连接在第二数据线和虚拟数据线之间的第一均衡器电路，并且在半导体存储器件被设置为激活模式之后的预定时间段期间使两端的电位相等，以及第二均衡器电路数据线和虚拟数据线，并且在存储器件被设置为活动模式之后的预定时间段期间两端的均衡电位。

9. 发明授权

US06376295B1 Method for manufacturing a semiconductor memory device with a fine structure 失效
标题翻译：具有精细结构的半导体存储器件的制造方法
公开(公告)号：US06376295B1
公开(公告)日：2002-04-23
申请号：US09631977
申请日：2000-08-03
申请人： Kiyomi Naruke , Minoru Kurata , Yuuichi Tatsumi , Yasumasa Sawada
发明人： Kiyomi Naruke , Minoru Kurata , Yuuichi Tatsumi , Yasumasa Sawada
IPC分类号： H01L218238
CPC分类号： H01L27/11568 , G11C16/0491 , H01L27/115 , H01L27/11521 , H01L27/11526 , H01L27/11546
摘要： There is disclosed a memory cell which has a diffusion layers constituting source/drain areas formed on a p-type silicon substrate surface, and a channel area formed between the diffusion layers. Above the channel area, an insulating film of a laminated structure is formed of a silicon oxide film, a silicon nitride film and a silicon oxide film. A gate electrode is formed on the upper surface of the insulating film of the laminated structure. The gate electrode is used as a word line. Moreover, an interlayer insulating film is formed between the diffusion layer and the gate electrode. By injecting hot electrons from the substrate to the silicon nitride film in the insulating film of the laminated structure, data is written. The silicon nitride film and the diffusion layer are partially overlapped in a vertical direction, and an offset portion is disposed between the silicon nitride film and the diffusion layer.
摘要翻译：公开了一种存储单元，其具有构成在p型硅衬底表面上形成的源/漏区的扩散层和形成在扩散层之间的沟道区。在通道区域之上，层叠结构的绝缘膜由氧化硅膜，氮化硅膜和氧化硅膜形成。在层叠结构体的绝缘膜的上表面上形成栅电极。栅电极用作字线。此外，在扩散层和栅电极之间形成层间绝缘膜。通过将层叠结构的绝缘膜中的热电子从基板注入氮化硅膜，写入数据。氮化硅膜和扩散层在垂直方向上部分重叠，偏移部分设置在氮化硅膜和扩散层之间。

10. 发明授权

US5056064A Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：US5056064A
公开(公告)日：1991-10-08
申请号：US568734
申请日：1990-08-17
申请人： Hiroshi Iwahashi , Hideo Kato , Yuuichi Tatsumi
发明人： Hiroshi Iwahashi , Hideo Kato , Yuuichi Tatsumi
IPC分类号： G11C7/10 , G11C7/22 , G11C8/18 , H03K5/1534
CPC分类号： G11C7/1051 , G11C7/1006 , G11C7/22 , G11C8/18 , H03K5/1534
摘要： A data transfer control circuit is connected between a sense amplifier and output buffer circuit. The data transfer control circuit is controlled by a pulse signal supplied from a pulse signal generator so as to have longer delay time which pulse signal is not generated by the pulse signal generator, and operate as noise canceller and prevents from outputting erroneous signal therefrom to the output buffer circuit.

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