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1. 发明授权

US08664062B2 Method of manufacturing flash memory cell 有权
标题翻译：制造闪存单元的方法
公开(公告)号：US08664062B2
公开(公告)日：2014-03-04
申请号：US13047758
申请日：2011-03-14
申请人： Yung-Chang Lin , Nan-Ray Wu , Le-Tien Jung
发明人： Yung-Chang Lin , Nan-Ray Wu , Le-Tien Jung
IPC分类号： H01L21/336 , H01L21/3205 , H01L21/76
CPC分类号： H01L27/11524 , H01L21/28273 , H01L27/11526 , H01L27/11536 , H01L27/1157 , H01L29/4983 , H01L29/512 , H01L29/6659 , H01L29/7833 , H01L29/7881
摘要： A method of manufacturing a flash memory cell includes providing a substrate having a first dielectric layer formed thereon, forming a control gate on the first dielectric layer, forming an oxide-nitride-oxide (ONO) spacer on sidewalls of the control gate, forming a second dielectric layer on the substrate at two sides of the ONO spacer, and forming a floating gate at outer sides of the ONO spacer on the second dielectric layer, respectively.
摘要翻译：制造闪速存储单元的方法包括提供其上形成有第一介电层的基板，在第一介电层上形成控制栅极，在控制栅极的侧壁上形成氧化物 - 氧化物（ONO）间隔物，形成在ONO间隔物两侧的衬底上的第二电介质层，并分别在第二电介质层上的ONO间隔物的外侧形成浮栅。

2. 发明申请

US20110244640A1 METHOD OF MANUFACTURING FLASH MEMORY CELL 有权
标题翻译：制造闪存存储单元的方法
公开(公告)号：US20110244640A1
公开(公告)日：2011-10-06
申请号：US13047758
申请日：2011-03-14
申请人： Yung-Chang Lin , Nan-Ray Wu , Le-Tien Jung
发明人： Yung-Chang Lin , Nan-Ray Wu , Le-Tien Jung
IPC分类号： H01L21/336 , H01L21/3205 , H01L21/76
CPC分类号： H01L27/11524 , H01L21/28273 , H01L27/11526 , H01L27/11536 , H01L27/1157 , H01L29/4983 , H01L29/512 , H01L29/6659 , H01L29/7833 , H01L29/7881
摘要： A method of manufacturing a flash memory cell includes providing a substrate having a first dielectric layer formed thereon, forming a control gate on the first dielectric layer, forming an oxide-nitride-oxide (ONO) spacer on sidewalls of the control gate, forming a second dielectric layer on the substrate at two sides of the ONO spacer, and forming a floating gate at outer sides of the ONO spacer on the second dielectric layer, respectively.
摘要翻译：制造闪速存储单元的方法包括提供其上形成有第一介电层的基板，在第一介电层上形成控制栅极，在控制栅极的侧壁上形成氧化物 - 氧化物（ONO）间隔物，形成在ONO间隔物两侧的衬底上的第二电介质层，并分别在第二电介质层上的ONO间隔物的外侧形成浮栅。

3. 发明申请

US20050156252A1 Method for forming a polycide gate and structure of the same 审中-公开
标题翻译：形成多晶硅栅极的方法及其结构
公开(公告)号：US20050156252A1
公开(公告)日：2005-07-21
申请号：US11011598
申请日：2004-12-15
申请人： Yung-Chang Lin , Le-Tien Jung , Wen-Jeng Lin
发明人： Yung-Chang Lin , Le-Tien Jung , Wen-Jeng Lin
IPC分类号： H01L21/28 , H01L21/3115 , H01L29/49 , H01L29/76 , H01L21/336
CPC分类号： H01L21/31155 , H01L21/28061 , H01L29/4916
摘要： The method of forming a polycide gate includes forming a pad oxide layer on a substrate. A first conductive layer is formed on the pad oxide layer. Subsequently, a first ion implantation into the first conductive layer is next performed to form deep implantation region of polysilicon. Successively, a second ion implantation into the first conductive layer is performed to form shallow implantation region of polysilicon, wherein the second ion type is the same as the first ion type. A second conductive layer formed on the first conductive layer. A further patterned photoresist layer is formed on the second conductive layer. Next, a dry etching process one time by way of using the patterned photoresist layer as an etching mask is performed to etch through in turn the second conductive layer, the first conductive layer and the pad oxide layer until forming a gate with double polysilicon implantation, thereby forming a polycide gate. Finally, the photoresist layer is then removed.
摘要翻译：形成多晶硅栅极的方法包括在衬底上形成衬垫氧化物层。在衬垫氧化物层上形成第一导电层。随后，进行第一离子注入到第一导电层中以形成多晶硅的深注入区。接着，进行到第一导电层的第二离子注入以形成多晶硅的浅注入区，其中第二离子类型与第一离子类型相同。形成在第一导电层上的第二导电层。在第二导电层上形成另外的图案化光致抗蚀剂层。接下来，进行通过使用图案化光致抗蚀剂层作为蚀刻掩模一次的干蚀刻处理，以依次蚀刻第二导电层，第一导电层和衬垫氧化物层，直到形成具有双多晶硅注入的栅极，从而形成多晶硅栅极。最后，去除光致抗蚀剂层。

4. 发明授权

US08748961B2 Buried bit line process and scheme 有权
标题翻译：埋位式流程和方案
公开(公告)号：US08748961B2
公开(公告)日：2014-06-10
申请号：US12940207
申请日：2010-11-05
申请人： Le-Tien Jung , Yung-Chang Lin
发明人： Le-Tien Jung , Yung-Chang Lin
IPC分类号： H01L29/94
CPC分类号： H01L27/10885 , H01L21/743 , H01L27/10876 , H01L27/10888
摘要： The embodiment provides a buried bit line process and scheme. The buried bit line is disposed in a trench formed in a substrate. The buried bit line includes a diffusion region formed in a portion of the substrate adjacent the trench. A blocking layer is formed on a portion sidewall of the trench. A conductive plug is formed in the trench, covering sidewalls of the diffusion region and the blocking layer.
摘要翻译：该实施例提供了一种掩埋位线处理和方案。掩埋位线设置在形成在衬底中的沟槽中。掩埋位线包括形成在与沟槽相邻的衬底的一部分中的扩散区域。阻挡层形成在沟槽的一部分侧壁上。导电插塞形成在沟槽中，覆盖扩散区域和阻挡层的侧壁。

5. 发明授权

US09022392B2 Chuck and semiconductor process using the same 有权
标题翻译：夹头和半导体工艺使用相同
公开(公告)号：US09022392B2
公开(公告)日：2015-05-05
申请号：US13600231
申请日：2012-08-31
申请人： Chung-Sung Jang , Ming-Tse Lin , Yung-Chang Lin
发明人： Chung-Sung Jang , Ming-Tse Lin , Yung-Chang Lin
IPC分类号： H01L21/683
CPC分类号： H01L22/20 , G03F7/20 , G03F7/707 , G03F7/70783 , H01L21/6836 , H01L21/6838 , H01L22/12 , Y10T29/49764 , Y10T279/11
摘要： An apparatus of semiconductor process including a chuck and a vacuum source is provided. The chuck has a plurality of holes for holding a semiconductor substrate, and the vacuum source is used for providing vacuum suction through the holes to make the semiconductor substrate be subjected to varied suction intensities according to a warpage level thereof.
摘要翻译：提供一种包括卡盘和真空源的半导体工艺装置。卡盘具有用于保持半导体衬底的多个孔，并且真空源用于通过孔提供真空吸力，以使半导体衬底根据其翘曲程度受到各种抽吸强度。

6. 发明授权

US08377829B2 Method of manufacturing a capacitor deep trench and of etching a deep trench opening 有权
标题翻译：制造电容器深沟槽并蚀刻深沟槽开口的方法
公开(公告)号：US08377829B2
公开(公告)日：2013-02-19
申请号：US11871166
申请日：2007-10-12
申请人： Ta-Chuan Yeh , Ni-Min Chung , Kao-Su Huang , Yung-Chang Lin , Ruey-Chyr Lee , Chien-Kuo Wang
发明人： Ta-Chuan Yeh , Ni-Min Chung , Kao-Su Huang , Yung-Chang Lin , Ruey-Chyr Lee , Chien-Kuo Wang
IPC分类号： H01L21/302 , H01L21/461 , B44C1/22 , C03C15/00 , C03C25/68 , C23F1/00
CPC分类号： H01L27/1087 , H01L21/76205
摘要： A substrate is provided having an oxide layer, a first nitride-silicon, a STI, and a second nitride-silicon. A pattern poly-silicon layer on the second nitride-silicon layer is etched to form a deep trench opening. Etching the pattern poly-silicon layer also deepens the deep trench opening. Then, a conductive layer is filled in the deep trench opening.
摘要翻译：提供了具有氧化物层，第一氮化硅 - 硅，STI和第二氮化硅 - 硅的衬底。蚀刻第二氮化硅 - 硅层上的图案多晶硅层以形成深沟槽开口。蚀刻图案多晶硅层也加深了深沟槽开口。然后，在深沟槽开口中填充导电层。

7. 发明授权

US08227890B2 Method of forming an electrical fuse and a metal gate transistor and the related electrical fuse 有权
标题翻译：形成电熔丝和金属栅晶体管及相关电熔丝的方法
公开(公告)号：US08227890B2
公开(公告)日：2012-07-24
申请号：US12641322
申请日：2009-12-18
申请人： Yung-Chang Lin , Kuei-Sheng Wu , Chang-Chien Wong
发明人： Yung-Chang Lin , Kuei-Sheng Wu , Chang-Chien Wong
IPC分类号： H01L29/00
CPC分类号： H01L23/5256 , H01L21/823807 , H01L21/823814 , H01L27/0629 , H01L27/112 , H01L27/11206 , H01L29/7843 , H01L29/7848 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a method of integrating an electrical fuse process into a high-k/metal gate process. The method simultaneously forms a dummy gate stack of a transistor and a dummy gate stack of an e-fuse; and simultaneously removes the polysilicon of the dummy gate stack in the transistor region and the polysilicon of the dummy gate stack in the e-fuse region. Thereafter, the work function metal layer disposed in the opening of the e-fuse region is removed; and the opening in the transistor region and the opening in the e-fuse region with metal conductive structures are filled to form an e-fuse and a metal gate of a transistor.
摘要翻译：本发明提供了一种将电熔丝工艺集成到高k /金属栅极工艺中的方法。该方法同时形成晶体管的虚拟栅极堆叠和电子熔丝的虚拟栅极堆叠; 并且同时去除晶体管区域中的虚拟栅极堆叠的多晶硅和电子熔丝区域中的伪栅极堆叠的多晶硅。此后，去除设置在电熔丝区域的开口中的功函数金属层; 并且晶体管区域中的开口和具有金属导电结构的e熔丝区域中的开口被填充以形成晶体管的电熔丝和金属栅极。

8. 发明申请

US20120075218A1 TOUCH PANEL AND TOUCH DISPLAY DEVICE USING THE SAME 审中-公开
标题翻译：触摸面板和触摸显示设备使用它
公开(公告)号：US20120075218A1
公开(公告)日：2012-03-29
申请号：US13238255
申请日：2011-09-21
申请人： MING-CHUAN LIN , Tien-Nan Wang , Ying-Chi Wang , Yung-Chang Lin , Lin Lin , Wen-Hung Wang , Pei-Fang Tsai , Shyh-Jeng Chen
发明人： MING-CHUAN LIN , Tien-Nan Wang , Ying-Chi Wang , Yung-Chang Lin , Lin Lin , Wen-Hung Wang , Pei-Fang Tsai , Shyh-Jeng Chen
IPC分类号： G06F3/041
CPC分类号： G06F3/044 , G06F3/0418 , G06F2203/04107
摘要： A touch panel comprising a substrate, a touch element, a first grounding electrode, an insulation layer and a second grounding electrode is disclosed. The touch element is disposed on a first surface of the substrate. The first grounding electrode is disposed on the first surface to surround the touch element. The insulation layer is disposed on the first surface to cover the touch element and the first grounding electrode. The second grounding electrode is disposed on the first insulation layer or on a second surface of the substrate opposite to the first surface. Therefore, the ESD can be conducted to the grounding end G of the circuit component through the enclosed first grounding electrode, and the signal interference between the touch panel and display can be shielded by the second grounding electrode to enhance anti-ESD and anti-noise abilities of the touch panel.
摘要翻译：公开了一种包括基板，触摸元件，第一接地电极，绝缘层和第二接地电极的触摸面板。触摸元件设置在基板的第一表面上。第一接地电极设置在第一表面上以围绕触摸元件。绝缘层设置在第一表面上以覆盖触摸元件和第一接地电极。第二接地电极设置在与第一表面相对的第一绝缘层或第二表面上。因此，ESD可以通过封闭的第一接地电极传导到电路部件的接地端G，并且可以通过第二接地电极屏蔽触摸面板和显示器之间的信号干扰，以增强抗ESD和抗噪声触摸屏的能力。

9. 发明申请

US20120001813A1 USB Antenna with a Bottle Opener 审中-公开
标题翻译： USB天线与开瓶器
公开(公告)号：US20120001813A1
公开(公告)日：2012-01-05
申请号：US12883403
申请日：2010-09-16
申请人： Yung-Chang Lin
发明人： Yung-Chang Lin
IPC分类号： H01Q1/00 , B67B7/44
CPC分类号： B67B7/16 , H01Q1/2275 , H01Q1/44
摘要： The present invention discloses an USB antenna device with a bottle opener, which comprises a main body being a casing; a connector being mounted on an end of the main body; a bottle opener being concavely disposed on a side of the main body; and a wireless antenna for transmitting and receiving wireless signals or microwaves. In the present invention, the available limited space in the USB antenna device can be used efficiently because the wireless antenna occupying a certain area in the traditional USB antenna device is disposed corresponding to a bottle opener structure. That is, the USB antenna device of the present invention not only is easy to carry, but can also provide a function of opening the bottle.
摘要翻译：本发明公开了一种具有开瓶器的USB天线装置，其包括：主体，其为壳体; 连接器，其安装在所述主体的端部上; 开瓶器凹入地设置在主体的一侧; 以及用于发送和接收无线信号或微波的无线天线。在本发明中，由于在传统的USB天线装置中占据一定区域的无线天线对应于开瓶器结构而设置在USB天线装置中的有限空间可以有效地使用。也就是说，本发明的USB天线装置不仅容易携带，而且还可以提供打开瓶子的功能。

10. 发明授权

US08071437B2 Method of fabricating efuse, resistor and transistor 有权
标题翻译：制造efuse，电阻和晶体管的方法
公开(公告)号：US08071437B2
公开(公告)日：2011-12-06
申请号：US12621518
申请日：2009-11-19
申请人： Yung-Chang Lin , Kuei-Sheng Wu , Chang-Chien Wong , Ching-Hsiang Tseng
发明人： Yung-Chang Lin , Kuei-Sheng Wu , Chang-Chien Wong , Ching-Hsiang Tseng
IPC分类号： H01L21/8234
CPC分类号： H01L21/823807 , H01L21/823842 , H01L27/0629 , H01L29/7848
摘要： A method of fabricating an efuse, a resistor and a transistor includes the following steps: A substrate is provided. Then, a gate, a resistor and an efuse are formed on the substrate, wherein the gate, the resistor and the efuse together include a first dielectric layer, a polysilicon layer and a hard mask. Later, a source/drain doping region is formed in the substrate besides the gate. After that, the hard mask in the resistor and the efuse is removed. Subsequently, a salicide process is performed to form a silicide layer on the source/drain doping region, the resistor, and the efuse. Then, a planarized second dielectric layer is formed on the substrate and the polysilicon in the gate is exposed. Later, the polysilicon in the gate is removed to form a recess. Finally a metal layer is formed to fill up the recess.
摘要翻译：一种制造efuse，电阻器和晶体管的方法包括以下步骤：提供衬底。然后，在衬底上形成栅极，电阻器和efuse，其中栅极，电阻器和efuse一起包括第一介电层，多晶硅层和硬掩模。之后，在栅极之外的基板中形成源极/漏极掺杂区域。之后，去除电阻和efuse中的硬掩模。随后，执行自对准硅化处理以在源/漏掺杂区域，电阻器和efuse上形成硅化物层。然后，在基板上形成平坦化的第二介质层，露出栅极中的多晶硅。之后，去除栅极中的多晶硅以形成凹陷。最后，形成一个金属层以填充凹槽。

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