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1. 发明申请

US20050156252A1 Method for forming a polycide gate and structure of the same 审中-公开
标题翻译：形成多晶硅栅极的方法及其结构
公开(公告)号：US20050156252A1
公开(公告)日：2005-07-21
申请号：US11011598
申请日：2004-12-15
申请人： Yung-Chang Lin , Le-Tien Jung , Wen-Jeng Lin
发明人： Yung-Chang Lin , Le-Tien Jung , Wen-Jeng Lin
IPC分类号： H01L21/28 , H01L21/3115 , H01L29/49 , H01L29/76 , H01L21/336
CPC分类号： H01L21/31155 , H01L21/28061 , H01L29/4916
摘要： The method of forming a polycide gate includes forming a pad oxide layer on a substrate. A first conductive layer is formed on the pad oxide layer. Subsequently, a first ion implantation into the first conductive layer is next performed to form deep implantation region of polysilicon. Successively, a second ion implantation into the first conductive layer is performed to form shallow implantation region of polysilicon, wherein the second ion type is the same as the first ion type. A second conductive layer formed on the first conductive layer. A further patterned photoresist layer is formed on the second conductive layer. Next, a dry etching process one time by way of using the patterned photoresist layer as an etching mask is performed to etch through in turn the second conductive layer, the first conductive layer and the pad oxide layer until forming a gate with double polysilicon implantation, thereby forming a polycide gate. Finally, the photoresist layer is then removed.
摘要翻译：形成多晶硅栅极的方法包括在衬底上形成衬垫氧化物层。在衬垫氧化物层上形成第一导电层。随后，进行第一离子注入到第一导电层中以形成多晶硅的深注入区。接着，进行到第一导电层的第二离子注入以形成多晶硅的浅注入区，其中第二离子类型与第一离子类型相同。形成在第一导电层上的第二导电层。在第二导电层上形成另外的图案化光致抗蚀剂层。接下来，进行通过使用图案化光致抗蚀剂层作为蚀刻掩模一次的干蚀刻处理，以依次蚀刻第二导电层，第一导电层和衬垫氧化物层，直到形成具有双多晶硅注入的栅极，从而形成多晶硅栅极。最后，去除光致抗蚀剂层。

2. 发明授权

US08664062B2 Method of manufacturing flash memory cell 有权
标题翻译：制造闪存单元的方法
公开(公告)号：US08664062B2
公开(公告)日：2014-03-04
申请号：US13047758
申请日：2011-03-14
申请人： Yung-Chang Lin , Nan-Ray Wu , Le-Tien Jung
发明人： Yung-Chang Lin , Nan-Ray Wu , Le-Tien Jung
IPC分类号： H01L21/336 , H01L21/3205 , H01L21/76
CPC分类号： H01L27/11524 , H01L21/28273 , H01L27/11526 , H01L27/11536 , H01L27/1157 , H01L29/4983 , H01L29/512 , H01L29/6659 , H01L29/7833 , H01L29/7881
摘要： A method of manufacturing a flash memory cell includes providing a substrate having a first dielectric layer formed thereon, forming a control gate on the first dielectric layer, forming an oxide-nitride-oxide (ONO) spacer on sidewalls of the control gate, forming a second dielectric layer on the substrate at two sides of the ONO spacer, and forming a floating gate at outer sides of the ONO spacer on the second dielectric layer, respectively.
摘要翻译：制造闪速存储单元的方法包括提供其上形成有第一介电层的基板，在第一介电层上形成控制栅极，在控制栅极的侧壁上形成氧化物 - 氧化物（ONO）间隔物，形成在ONO间隔物两侧的衬底上的第二电介质层，并分别在第二电介质层上的ONO间隔物的外侧形成浮栅。

3. 发明授权

US08748961B2 Buried bit line process and scheme 有权
标题翻译：埋位式流程和方案
公开(公告)号：US08748961B2
公开(公告)日：2014-06-10
申请号：US12940207
申请日：2010-11-05
申请人： Le-Tien Jung , Yung-Chang Lin
发明人： Le-Tien Jung , Yung-Chang Lin
IPC分类号： H01L29/94
CPC分类号： H01L27/10885 , H01L21/743 , H01L27/10876 , H01L27/10888
摘要： The embodiment provides a buried bit line process and scheme. The buried bit line is disposed in a trench formed in a substrate. The buried bit line includes a diffusion region formed in a portion of the substrate adjacent the trench. A blocking layer is formed on a portion sidewall of the trench. A conductive plug is formed in the trench, covering sidewalls of the diffusion region and the blocking layer.
摘要翻译：该实施例提供了一种掩埋位线处理和方案。掩埋位线设置在形成在衬底中的沟槽中。掩埋位线包括形成在与沟槽相邻的衬底的一部分中的扩散区域。阻挡层形成在沟槽的一部分侧壁上。导电插塞形成在沟槽中，覆盖扩散区域和阻挡层的侧壁。

4. 发明申请

US20110244640A1 METHOD OF MANUFACTURING FLASH MEMORY CELL 有权
标题翻译：制造闪存存储单元的方法
公开(公告)号：US20110244640A1
公开(公告)日：2011-10-06
申请号：US13047758
申请日：2011-03-14
申请人： Yung-Chang Lin , Nan-Ray Wu , Le-Tien Jung
发明人： Yung-Chang Lin , Nan-Ray Wu , Le-Tien Jung
IPC分类号： H01L21/336 , H01L21/3205 , H01L21/76
CPC分类号： H01L27/11524 , H01L21/28273 , H01L27/11526 , H01L27/11536 , H01L27/1157 , H01L29/4983 , H01L29/512 , H01L29/6659 , H01L29/7833 , H01L29/7881
摘要： A method of manufacturing a flash memory cell includes providing a substrate having a first dielectric layer formed thereon, forming a control gate on the first dielectric layer, forming an oxide-nitride-oxide (ONO) spacer on sidewalls of the control gate, forming a second dielectric layer on the substrate at two sides of the ONO spacer, and forming a floating gate at outer sides of the ONO spacer on the second dielectric layer, respectively.
摘要翻译：制造闪速存储单元的方法包括提供其上形成有第一介电层的基板，在第一介电层上形成控制栅极，在控制栅极的侧壁上形成氧化物 - 氧化物（ONO）间隔物，形成在ONO间隔物两侧的衬底上的第二电介质层，并分别在第二电介质层上的ONO间隔物的外侧形成浮栅。

5. 发明申请

US20120196436A1 MANUFACTURING METHOD FOR A BURIED CIRCUIT STRUCTURE 有权
标题翻译：一种布线电路结构的制造方法
公开(公告)号：US20120196436A1
公开(公告)日：2012-08-02
申请号：US13441927
申请日：2012-04-09
申请人： Le-Tien Jung , Tai-Sheng Feng
发明人： Le-Tien Jung , Tai-Sheng Feng
IPC分类号： H01L21/768
CPC分类号： H01L21/743 , H01L21/76879 , H01L27/10885 , H01L27/10891
摘要： A manufacturing method for a buried circuit structure includes providing a substrate having at least a trench formed therein, forming a firs conductive layer on the substrate blanketly, forming a patterned photoresist having a surface lower than an opening of the trench in the trench, removing the first conductive layer not covered by the patterned photoresist to form a second conductive layer having a top lower than an opening of the trench in the trench, removing the patterned photoresist, performing a dry etching process to remove the second conductive layer from the bottom of the trench to form a third conductive layer on the sidewalls of the trench, performing a selective metal chemical vapor deposition to form a metal layer having a surface lower than a surface of the substrate, and forming a protecting layer filling the trench on the metal layer.
摘要翻译：掩埋电路结构的制造方法包括提供至少形成有沟槽的衬底，在衬底上形成第一导电层，形成表面低于沟槽开口的图案化光致抗蚀剂，去除第一导电层未被图案化的光致抗蚀剂覆盖以形成具有比沟槽中的沟槽的开口低的顶部的第二导电层，去除图案化的光致抗蚀剂，执行干蚀刻工艺以从第二导电层的底部移除第二导电层沟槽，以在沟槽的侧壁上形成第三导电层，进行选择性金属化学气相沉积以形成具有低于衬底表面的表面的金属层，以及形成填充金属层上的沟槽的保护层。

6. 发明授权

US06627525B2 Method for preventing polycide gate spiking 有权
标题翻译：防止多孔栅极尖峰的方法
公开(公告)号：US06627525B2
公开(公告)日：2003-09-30
申请号：US09774816
申请日：2001-01-31
申请人： Ming-Tsung Chen , Kirk Hsu , Le-Tien Jung
发明人： Ming-Tsung Chen , Kirk Hsu , Le-Tien Jung
IPC分类号： H01L213205
CPC分类号： H01L21/324 , H01L21/28061 , H01L29/4941
摘要： A method for preventing polycide gate spiking, which essentially comprises the following steps: forms an oxide layer on a substrate; forming a polysilicon layer on the oxide layer; sputtering a barrier layer on the polysilicon layer; performing a first rapid thermal process; sputtering a silicide layer on the barrier layer; performing a photolithography process and an etching process to remove part of the silicide layer, part of the barrier layer and part of the polysilicon layer to form a polycide gate; and performing a second rapid thermal process. Further, as it is necessary to use both rapid thermal processes, the invention can be expanded such that only one rapid thermal process is applied. Both rapid thermal processes use almost no oxygen.
摘要翻译：防止多晶硅栅极尖峰化的方法，其基本上包括以下步骤：在基底上形成氧化物层; 在所述氧化物层上形成多晶硅层; 在多晶硅层上溅射阻挡层; 执行第一快速热处理; 在阻挡层上溅射硅化物层; 执行光刻工艺和蚀刻工艺以去除硅化物层的一部分，阻挡层的一部分和多晶硅层的一部分以形成多晶硅栅极; 并执行第二快速热处理。此外，由于需要同时使用快速热处理，本发明可以被扩展，使得只应用一个快速热处理。两种快速热处理几乎不使用氧气。

7. 发明授权

US06392930B1 Method of manufacturing mask read-only memory cell 有权
公开(公告)号：US06392930B1
公开(公告)日：2002-05-21
申请号：US09756587
申请日：2001-01-09
申请人： Le-Tien Jung , Ming-Jing Ho
发明人： Le-Tien Jung , Ming-Jing Ho
IPC分类号： G11C700
摘要： A method of manufacturing a ROM cell. A DRAM cell is provided. An ONO (oxide-nitride-oxide) stacked layer is used as a dielectric film of a capacitor of the DRAM cell. When a supply power is over 6 volts, the dielectric layer would be breakdown so that leakage is occurred between a lower electrode and an upper electrode of the capacitor. The DRAM cell, which can be used as a ROM cell, is thus readout as a stock at fault to stock a logic state of “1” or “0”. The stored data as “1” or “0” is depended on voltage of the upper electrode (VPL) and a voltage of the bit line (VBL). If VPL>VBL, the breakdown of the dielectric film would make the cell stock at “1”, and a normal DRAM cell is stocked at “0”, and vice versa.

8. 发明授权

US08183146B2 Manufacturing method for a buried circuit structure 有权
标题翻译：埋地电路结构的制造方法
公开(公告)号：US08183146B2
公开(公告)日：2012-05-22
申请号：US12980349
申请日：2010-12-29
申请人： Tai-Sheng Feng , Le-Tien Jung
发明人： Tai-Sheng Feng , Le-Tien Jung
IPC分类号： H01L21/4763 , H01L21/44 , H01L21/302
CPC分类号： H01L21/743 , H01L21/76879 , H01L27/10885 , H01L27/10891
摘要： A manufacturing method for a buried circuit structure includes providing a substrate having at least a trench therein, forming a conductive layer having a top lower than an opening of the trench in the trench, performing a selective metal chemical vapor deposition (CVD) to form a metal layer having a top lower than the substrate in the trench, and forming a protecting layer filling the trench on the metal layer.
摘要翻译：掩埋电路结构的制造方法包括提供其中至少具有沟槽的衬底，在沟槽中形成具有比沟槽开口低的顶部的导电层，执行选择性金属化学气相沉积（CVD）以形成金属层的顶部比沟槽中的衬底低，并且形成填充金属层上的沟槽的保护层。

9. 发明授权

US07749856B2 Method of fabricating storage node with supported structure of stacked capacitor 有权
标题翻译：制造堆叠电容器支撑结构的储能节点的方法
公开(公告)号：US07749856B2
公开(公告)日：2010-07-06
申请号：US12237382
申请日：2008-09-24
申请人： Shih-Fan Kuan , Le-Tien Jung
发明人： Shih-Fan Kuan , Le-Tien Jung
IPC分类号： H01L21/20
CPC分类号： H01L28/90 , H01L27/10817 , H01L27/10852
摘要： A method of fabricating a storage node with a supported structure is provided. A dielectric stacked comprising an etch stop layer, a first dielectric layer, a support layer and a second dielectric layer is formed on a substrate. An opening is etched into the dielectric stacked. A conductive layer is formed on the second dielectric layer and inside the opening. The conductive layer directly above the second dielectric layer is removed to form columnar node structure. The second dielectric layer is then removed. A spacer layer is deposited on the support layer and the columnar node structure. A tilt-angle implant is performed to implant dopants into the spacer layer. The undoped spacer layer is removed to form a hard mask. The support layer not covered by the hard mask is etched away to expose the first dielectric layer. The first dielectric layer and the hard mask are removed.
摘要翻译：提供一种制造具有支撑结构的存储节点的方法。在衬底上形成包括蚀刻停止层，第一介电层，支撑层和第二介电层的电介质。一个开口蚀刻到堆叠的电介质中。导电层形成在第二介质层上和开口内部。直接在第二介质层上方的导电层被去除以形成柱状节点结构。然后去除第二介电层。间隔层沉积在支撑层和柱状节点结构上。执行倾斜角度注入以将掺杂剂注入到间隔层中。去除未掺杂的间隔层以形成硬掩模。不被硬掩模覆盖的支撑层被蚀刻掉以露出第一介电层。去除第一电介质层和硬掩模。

10. 发明授权

US07279707B2 Test key structure 有权
标题翻译：测试键结构
公开(公告)号：US07279707B2
公开(公告)日：2007-10-09
申请号：US11066991
申请日：2005-02-25
申请人： Chuck Chen , Yo-Yi Gong , Le-Tien Jung
发明人： Chuck Chen , Yo-Yi Gong , Le-Tien Jung
IPC分类号： H01L23/58
CPC分类号： H01L22/34
摘要： A test key structure includes a substrate, a closed loop, a plurality of spacers, a plurality of first and second doping regions and a plurality of contacts. The closed loop having two conductive lines and two connection portions is located on the substrate. Each connection portion connects to one end of the conductive line and surrounds a contact region. The spacers are disposed at the edge of the closed loop to cover the substrate between the conductive lines. The first doping regions are located in the substrate outside the closed loop and the spacers. The second doping regions are located in the substrate under the spacers. The contacts are electrically connected to the first doping regions within the contact regions. Because the spacers and the conductive lines are incorporated into a test key structure, the influence of spacers upon the entire device can be more accurately determined.
摘要翻译：测试键结构包括基板，闭环，多个间隔物，多个第一和第二掺杂区域以及多个触点。具有两个导线和两个连接部分的闭环位于基板上。每个连接部分连接到导电线的一端并且包围接触区域。间隔件设置在闭环的边缘以覆盖导电线之间的基板。第一掺杂区位于封闭环外部的衬底和间隔物中。第二掺杂区域位于衬垫下的衬垫下。触点电连接到接触区域内的第一掺杂区域。由于间隔物和导线被结合到测试键结构中，因此可以更精确地确定间隔物对整个器件的影响。

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