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1. 发明授权

US08183146B2 Manufacturing method for a buried circuit structure 有权
标题翻译：埋地电路结构的制造方法
公开(公告)号：US08183146B2
公开(公告)日：2012-05-22
申请号：US12980349
申请日：2010-12-29
申请人： Tai-Sheng Feng , Le-Tien Jung
发明人： Tai-Sheng Feng , Le-Tien Jung
IPC分类号： H01L21/4763 , H01L21/44 , H01L21/302
CPC分类号： H01L21/743 , H01L21/76879 , H01L27/10885 , H01L27/10891
摘要： A manufacturing method for a buried circuit structure includes providing a substrate having at least a trench therein, forming a conductive layer having a top lower than an opening of the trench in the trench, performing a selective metal chemical vapor deposition (CVD) to form a metal layer having a top lower than the substrate in the trench, and forming a protecting layer filling the trench on the metal layer.
摘要翻译：掩埋电路结构的制造方法包括提供其中至少具有沟槽的衬底，在沟槽中形成具有比沟槽开口低的顶部的导电层，执行选择性金属化学气相沉积（CVD）以形成金属层的顶部比沟槽中的衬底低，并且形成填充金属层上的沟槽的保护层。

2. 发明申请

US20120214279A1 METHOD OF MANUFACTURING SEMICONDUCTOR CHIP STACK 审中-公开
标题翻译：制造半导体芯片堆叠的方法
公开(公告)号：US20120214279A1
公开(公告)日：2012-08-23
申请号：US13400558
申请日：2012-02-20
申请人： John Hsuan , Tai-Sheng Feng
发明人： John Hsuan , Tai-Sheng Feng
IPC分类号： H01L21/78
CPC分类号： H01L25/0657 , H01L25/18 , H01L25/50 , H01L2224/32145 , H01L2225/06541 , H01L2924/1461 , H01L2924/00
摘要： A method of manufacturing a semiconductor chip stack includes providing a circuit layout of a function device, the circuit layout further comprising a first device layout and a second device layout, and an integration density of the first device layout is larger than an integration density of the second device layout; defining a plurality of first chip regions on a first wafer and forming the first device layout in each first chip region; defining a plurality of second chip regions on a second wafer and forming the second device layout in each second chip region; forming a plurality of first TSVs in each first wafer for electrically connecting the first device layout and the second device layout; and respectively cutting the first wafer and the second wafer to form a plurality of first chips and a plurality of second chips.
摘要翻译：制造半导体芯片堆叠的方法包括提供功能器件的电路布局，电路布局还包括第一器件布局和第二器件布局，并且第一器件布局的集成密度大于第第二设备布局; 在第一晶片上限定多个第一芯片区域，并在每个第一芯片区域中形成第一器件布局; 在第二晶片上限定多个第二芯片区域，并在每个第二芯片区域中形成第二器件布局; 在每个第一晶片中形成多个第一TSV，用于电连接第一器件布局和第二器件布局; 并分别切割第一晶片和第二晶片以形成多个第一芯片和多个第二芯片。

3. 发明申请

US20120196436A1 MANUFACTURING METHOD FOR A BURIED CIRCUIT STRUCTURE 有权
标题翻译：一种布线电路结构的制造方法
公开(公告)号：US20120196436A1
公开(公告)日：2012-08-02
申请号：US13441927
申请日：2012-04-09
申请人： Le-Tien Jung , Tai-Sheng Feng
发明人： Le-Tien Jung , Tai-Sheng Feng
IPC分类号： H01L21/768
CPC分类号： H01L21/743 , H01L21/76879 , H01L27/10885 , H01L27/10891
摘要： A manufacturing method for a buried circuit structure includes providing a substrate having at least a trench formed therein, forming a firs conductive layer on the substrate blanketly, forming a patterned photoresist having a surface lower than an opening of the trench in the trench, removing the first conductive layer not covered by the patterned photoresist to form a second conductive layer having a top lower than an opening of the trench in the trench, removing the patterned photoresist, performing a dry etching process to remove the second conductive layer from the bottom of the trench to form a third conductive layer on the sidewalls of the trench, performing a selective metal chemical vapor deposition to form a metal layer having a surface lower than a surface of the substrate, and forming a protecting layer filling the trench on the metal layer.
摘要翻译：掩埋电路结构的制造方法包括提供至少形成有沟槽的衬底，在衬底上形成第一导电层，形成表面低于沟槽开口的图案化光致抗蚀剂，去除第一导电层未被图案化的光致抗蚀剂覆盖以形成具有比沟槽中的沟槽的开口低的顶部的第二导电层，去除图案化的光致抗蚀剂，执行干蚀刻工艺以从第二导电层的底部移除第二导电层沟槽，以在沟槽的侧壁上形成第三导电层，进行选择性金属化学气相沉积以形成具有低于衬底表面的表面的金属层，以及形成填充金属层上的沟槽的保护层。

4. 发明授权

US08159075B2 Semiconductor chip stack and manufacturing method thereof 失效
标题翻译：半导体芯片堆栈及其制造方法
公开(公告)号：US08159075B2
公开(公告)日：2012-04-17
申请号：US12641333
申请日：2009-12-18
申请人： John Hsuan , Tai-Sheng Feng
发明人： John Hsuan , Tai-Sheng Feng
IPC分类号： H01L23/60 , H01L21/98
CPC分类号： H01L25/0657 , H01L25/18 , H01L25/50 , H01L2224/32145 , H01L2225/06541 , H01L2924/1461 , H01L2924/00
摘要： A semiconductor chip stack includes a first chip and a second chip. The first chip includes a first circuit formed in the first chip with a first integration density, and the second chip includes a second circuit in the second chip with a second integration density smaller than the first integration density. The first chip further includes at least a through-silicon via formed therein for electrically connecting the first chip and the second chip.
摘要翻译：半导体芯片堆叠包括第一芯片和第二芯片。第一芯片包括形成在第一芯片中的第一电路具有第一集成密度，并且第二芯片包括具有小于第一集成密度的第二集成密度的第二芯片中的第二电路。第一芯片还包括至少形成在其中的用于电连接第一芯片和第二芯片的穿硅通孔。

5. 发明授权

US5059829A Logic level shifting circuit with minimal delay 失效
标题翻译：具有最小延迟的逻辑电平移位电路
公开(公告)号：US5059829A
公开(公告)日：1991-10-22
申请号：US577178
申请日：1990-09-04
申请人： Stephen T. Flannagan , Tai-Sheng Feng
发明人： Stephen T. Flannagan , Tai-Sheng Feng
IPC分类号： H03K19/00 , H03K19/013 , H03K19/0175
CPC分类号： H03K19/0016 , H03K19/0136 , H03K19/017527
摘要： A circuit enabling the conversion of a set of ECL and a set of CMOS logic levels has a differential amplifier, two emitter followers, a current switching circuit, and a level shifting circuit. The differential amplifier provides a common mode input to two emitter followers which switch very rapidly using ECL voltage levels. High operational speed is accomplished by providing a relaxation current during logic high-to-low voltage transients. The current switching circuit conserves power consumption by switching off the relaxation current during logic low-to-high transients, during which time the emitter followers switch sufficiently fast. The level shifting circuit converts the set of ECL logic voltage levels to a set of CMOS voltage levels and the CMOS output voltage is used to control the current switching circuit without introducing a switching delay time.
摘要翻译：能够转换一组ECL和一组CMOS逻辑电平的电路具有差分放大器，两个发射极跟随器，电流切换电路和电平移位电路。差分放大器为使用ECL电压电平非常快速地切换的两个发射极跟随器提供了一个共模输入。通过在逻辑高电压到低电压瞬变期间提供松弛电流来实现高运行速度。电流开关电路通过在逻辑低电平至高瞬态期间关断松弛电流来节省功耗，在此期间发射极跟随器足够快地切换。电平移位电路将ECL逻辑电压电平的集合转换为一组CMOS电压电平，并且CMOS输出电压用于控制电流开关电路而不引入开关延迟时间。

6. 发明申请

US20120015515A1 MANUFACTURING METHOD FOR A BURIED CIRCUIT STRUCTURE 有权
标题翻译：一种布线电路结构的制造方法
公开(公告)号：US20120015515A1
公开(公告)日：2012-01-19
申请号：US12980349
申请日：2010-12-29
申请人： Tai-Sheng Feng , Le-Tien Jung
发明人： Tai-Sheng Feng , Le-Tien Jung
IPC分类号： H01L21/768
CPC分类号： H01L21/743 , H01L21/76879 , H01L27/10885 , H01L27/10891
摘要： A manufacturing method for a buried circuit structure includes providing a substrate having at least a trench therein, forming a conductive layer having a top lower than an opening of the trench in the trench, performing a selective metal chemical vapor deposition (CVD) to form a metal layer having a top lower than the substrate in the trench, and forming a protecting layer filling the trench on the metal layer.
摘要翻译：掩埋电路结构的制造方法包括提供其中至少具有沟槽的衬底，在沟槽中形成具有比沟槽开口低的顶部的导电层，执行选择性金属化学气相沉积（CVD）以形成金属层的顶部比沟槽中的衬底低，并且形成填充金属层上的沟槽的保护层。

7. 发明授权

US08431485B2 Manufacturing method for a buried circuit structure 有权
标题翻译：埋地电路结构的制造方法
公开(公告)号：US08431485B2
公开(公告)日：2013-04-30
申请号：US13441927
申请日：2012-04-09
申请人： Le-Tien Jung , Tai-Sheng Feng
发明人： Le-Tien Jung , Tai-Sheng Feng
IPC分类号： H01L21/4763 , H01L21/44 , H01L21/302
CPC分类号： H01L21/743 , H01L21/76879 , H01L27/10885 , H01L27/10891
摘要： A manufacturing method for a buried circuit structure includes providing a substrate having at least a trench formed therein, forming a firs conductive layer on the substrate blanketly, forming a patterned photoresist having a surface lower than an opening of the trench in the trench, removing the first conductive layer not covered by the patterned photoresist to form a second conductive layer having a top lower than an opening of the trench in the trench, removing the patterned photoresist, performing a dry etching process to remove the second conductive layer from the bottom of the trench to form a third conductive layer on the sidewalls of the trench, performing a selective metal chemical vapor deposition to form a metal layer having a surface lower than a surface of the substrate, and forming a protecting layer filling the trench on the metal layer.
摘要翻译：掩埋电路结构的制造方法包括提供至少形成有沟槽的衬底，在衬底上形成第一导电层，形成表面低于沟槽开口的图案化光致抗蚀剂，去除第一导电层未被图案化的光致抗蚀剂覆盖以形成具有比沟槽中的沟槽的开口低的顶部的第二导电层，去除图案化的光致抗蚀剂，执行干蚀刻工艺以从第二导电层的底部移除第二导电层沟槽，以在沟槽的侧壁上形成第三导电层，进行选择性金属化学气相沉积以形成具有低于衬底表面的表面的金属层，以及形成填充金属层上的沟槽的保护层。

8. 发明申请

US20110147909A1 SEMICONDCUTOR CHIP STACK AND MANUFACTURING METHOD THEREOF 失效
标题翻译：半导体芯片堆栈及其制造方法
公开(公告)号：US20110147909A1
公开(公告)日：2011-06-23
申请号：US12641333
申请日：2009-12-18
申请人： John Hsuan , Tai-Sheng Feng
发明人： John Hsuan , Tai-Sheng Feng
IPC分类号： H01L23/60 , H01L21/98
CPC分类号： H01L25/0657 , H01L25/18 , H01L25/50 , H01L2224/32145 , H01L2225/06541 , H01L2924/1461 , H01L2924/00
摘要： A semiconductor chip stack includes a first chip and a second chip. The first chip includes a first circuit formed in the first chip with a first integration density, and the second chip includes a second circuit in the second chip with a second integration density smaller than the first integration density. The first chip further includes at least a through-silicon via formed therein for electrically connecting the first chip and the second chip.
摘要翻译：半导体芯片堆叠包括第一芯片和第二芯片。第一芯片包括形成在第一芯片中的第一电路具有第一集成密度，并且第二芯片包括具有小于第一集成密度的第二集成密度的第二芯片中的第二电路。第一芯片还包括至少形成在其中的用于电连接第一芯片和第二芯片的穿硅通孔。

9. 发明授权

US5173877A BICMOS combined bit line load and write gate for a memory 失效
标题翻译： BICMOS组合位线负载和写入门用于存储器
公开(公告)号：US5173877A
公开(公告)日：1992-12-22
申请号：US625173
申请日：1990-12-10
申请人： Stephen T. Flannagan , Tai-Sheng Feng
发明人： Stephen T. Flannagan , Tai-Sheng Feng
IPC分类号： G11C7/10 , G11C7/12
CPC分类号： G11C7/1078 , G11C7/12
摘要： A BICMOS combined bit line load and write gate for a memory comprises first and second portions coupled to first and second bit lines of a bit line pair, the first and second portions each comprising first through sixth transistors. The first and second transistors are serially coupled from a power supply voltage terminal to form a CMOS inverter whose input terminal receives a local write signal and whose output terminal is coupled to the base of the fifth transistor. The third transistor has a drain coupled to the source of the second transistor, a gate for receiving the local write signal, and a source for receiving a data signal. The fourth transistor is serially coupled between the base of the fifth transistor and the source of the third transistor, with the local write signal coupled to the gate thereof. The fifth transistor has a collector coupled to the power supply voltage terminal, and an emitter coupled to a corresponding bit line. The sixth transistor receives the local write signal and is serially coupled between the power supply voltage terminal and the corresponding bit line. The BICMOS combined bit line load and write gate prevents failure due to the body effect, avoids failure due to manufacturing variations which occur due to ratioing of transistors, provides the ability to adapt the memory to different data organizations, and prevents of self boosting of the base of the fifth transistor.
摘要翻译：用于存储器的BICMOS组合位线负载和写入门包括耦合到位线对的第一和第二位线的第一和第二部分，第一和第二部分每个包括第一至第六晶体管。第一和第二晶体管从电源电压端子串联耦合，以形成CMOS反相器，其输入端子接收本地写信号，其输出端耦合到第五晶体管的基极。第三晶体管具有耦合到第二晶体管的源极的漏极，用于接收本地写入信号的栅极和用于接收数据信号的源极。第四晶体管串联耦合在第五晶体管的基极和第三晶体管的源极之间，其局部写信号耦合到其栅极。第五晶体管具有耦合到电源电压端子的集电极和耦合到相应位线的发射极。第六晶体管接收本地写入信号，并且串联耦合在电源电压端子和对应的位线之间。 BICMOS组合位线负载和写入门防止由于身体效应而导致的故障，避免由于晶体管的比例而导致的制造变化导致的故障，提供了将存储器适应不同数据组织的能力，并且防止了自增强第五晶体管的基极。

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