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1. 发明授权

US06256237B1 Semiconductor device and method for repairing failed memory cell by directly programming fuse memory cell 有权
标题翻译：半导体器件和通过直接编程保险丝存储器单元来修复故障存储器单元的方法
公开(公告)号：US06256237B1
公开(公告)日：2001-07-03
申请号：US09473083
申请日：1999-12-28
申请人： Ming-Jing Ho , Le-Tien Jung
发明人： Ming-Jing Ho , Le-Tien Jung
IPC分类号： G11C700
CPC分类号： G11C29/78 , G11C29/44 , G11C29/4401
摘要： A semiconductor memory device and a method for mending a failed memory cell by directly programming a fuse memory cell. Using a tester to program the fuse memory cell directly, a laser machine is not required. In addition, to move the wafer for fuse allocation is not required either, so that the consumption in time and cost can be greatly reduced. Even after the package is complete, the repairing work can still be performed. In addition, whether the voltage source is connected or disconnected, the failed address information is kept and stored without being lost. A self-repair for self-test can thus be applied.
摘要翻译：半导体存储器件和通过直接编程熔丝存储器单元来修复故障存储器单元的方法。使用测试仪直接对保险丝存储单元进行编程，不需要激光机。另外，也不需要移动用于熔丝分配的晶片，从而可以大大减少时间和成本的消耗。即使包装完成后，修理工作仍然可以进行。另外，无论电源是连接还是断开，故障地址信息都不会丢失而被保存和存储。因此可以应用自我修复。

2. 发明授权

US06392930B1 Method of manufacturing mask read-only memory cell 有权
公开(公告)号：US06392930B1
公开(公告)日：2002-05-21
申请号：US09756587
申请日：2001-01-09
申请人： Le-Tien Jung , Ming-Jing Ho
发明人： Le-Tien Jung , Ming-Jing Ho
IPC分类号： G11C700
摘要： A method of manufacturing a ROM cell. A DRAM cell is provided. An ONO (oxide-nitride-oxide) stacked layer is used as a dielectric film of a capacitor of the DRAM cell. When a supply power is over 6 volts, the dielectric layer would be breakdown so that leakage is occurred between a lower electrode and an upper electrode of the capacitor. The DRAM cell, which can be used as a ROM cell, is thus readout as a stock at fault to stock a logic state of “1” or “0”. The stored data as “1” or “0” is depended on voltage of the upper electrode (VPL) and a voltage of the bit line (VBL). If VPL>VBL, the breakdown of the dielectric film would make the cell stock at “1”, and a normal DRAM cell is stocked at “0”, and vice versa.

3. 发明授权

US06327174B1 Method of manufacturing mask read-only memory cell 有权
标题翻译：制造掩模只读存储单元的方法
公开(公告)号：US06327174B1
公开(公告)日：2001-12-04
申请号：US09513266
申请日：2000-02-24
申请人： Le-Tien Jung , Ming-Jing Ho
发明人： Le-Tien Jung , Ming-Jing Ho
IPC分类号： G11C1122
CPC分类号： H01L27/11206
摘要： A method of manufacturing a ROM cell. A DRAM cell is provided. An ONO (oxide-nitride-oxide) stacked layer is used as a dielectric film of a capacitor of the DRAM cell. When a supply power is over 6 volts, the dielectric layer would be breakdown so that leakage is occurred between a lower electrode and an upper electrode of the capacitor. The DRAM cell, which can be used as a ROM cell, is thus readout as a stock at fault to stock a logic state of “1” or “0”. The stored data as “1” or “0” is depended on voltage of the upper electrode (VPL) and a voltage of the bit line (VBL). If VPL>VBL, the breakdown of the dielectric film would make the cell stock at “1”, and a normal DRAM cell is stocked at “0”, and vice versa.
摘要翻译：一种制造ROM单元的方法。提供了DRAM单元。使用ONO（氧化物 - 氮化物 - 氧化物）层叠层作为DRAM单元的电容器的电介质膜。当电源功率超过6伏时，电介质层将被击穿，从而在电容器的下电极和上电极之间发生泄漏。因此，可以用作ROM单元的DRAM单元作为库存被故障地读出以存储“1”或“0”的逻辑状态。存储的数据为“1”或“0”取决于上电极（VPL）的电压和位线（VBL）的电压。如果VPL> VBL，电介质膜的击穿将使电池库存为“1”，并且正常DRAM单元被存储为“0”，反之亦然。

4. 发明授权

US06285620B1 Semiconductor device and method for repairing failed memory cell by directly programming fuse memory cell 有权
公开(公告)号：US06285620B1
公开(公告)日：2001-09-04
申请号：US09665788
申请日：2000-09-20
申请人： Ming-Jing Ho , Le-Tien Jung
发明人： Ming-Jing Ho , Le-Tien Jung
IPC分类号： G11C700
CPC分类号： G11C29/78 , G11C29/44 , G11C29/4401
摘要： A semiconductor memory device and a method for mending a failed memory cell by directly programming a fuse memory cell. Using a tester to program the fuse memory cell directly, a laser machine is not required. In addition, to move the wafer for fuse allocation is not required either, so that the consumption in time and cost can be greatly reduced. Even after the package is complete, the repairing work can still be performed. In addition, whether the voltage source is connected or disconnected, the failed address information is kept and stored without being lost. A self-repair for self-test can thus be applied.

5. 发明申请

US20120162831A1 ESD PROTECTION CIRCUIT FOR NEGATIVE-POWERED INTEGRATED CIRCUIT 有权
标题翻译：用于负极集成电路的ESD保护电路
公开(公告)号：US20120162831A1
公开(公告)日：2012-06-28
申请号：US12978622
申请日：2010-12-26
申请人： Wen-Tai Wang , Ming-Jing Ho
发明人： Wen-Tai Wang , Ming-Jing Ho
IPC分类号： H02H9/04
CPC分类号： H01L27/0251
摘要： For a negative-powered IC, an ESD protection circuit includes a negative voltage clamping circuit configured to provide a path for discharging ESD transient currents associated with different negative power supplies of the IC.
摘要翻译：对于负电源IC，ESD保护电路包括负电压钳位电路，其被配置为提供用于放电与IC的不同负电源相关联的ESD瞬态电流的路径。

6. 发明授权

US07463466B2 Integrated circuit with ESD protection circuit 有权
标题翻译：集成电路采用ESD保护电路
公开(公告)号：US07463466B2
公开(公告)日：2008-12-09
申请号：US11163571
申请日：2005-10-24
申请人： Kuey-Lung Kelvin Hsueh , Ming-Jing Ho
发明人： Kuey-Lung Kelvin Hsueh , Ming-Jing Ho
IPC分类号： H02H9/00
CPC分类号： H02H9/046
摘要： An integrated circuit (IC) having an electrostatic discharge (ESD) protection circuit therein is provided. The IC comprises a plurality of bonding pads, a plurality of ESD units, a first ESD bus and a second ESD bus. The first ESD bus has no direct connection with any power pad of the IC. Each ESD unit comprises a first diode, a second diode and an ESD clamping device. Due to the one-to-one correspondent of each bonding pad with an ESD unit, the present invention ensures ESD continuity through a continuous charge dissipation path no matter what kind of pin-to-pin ESD test the IC is undergoing or how many power sources the IC has. In addition, a bonding pad over active circuitry (BOAC) structure can also be deployed in the present invention to provide a better ESD protection for the whole IC chip.
摘要翻译：提供其中具有静电放电（ESD）保护电路的集成电路（IC）。 IC包括多个接合焊盘，多个ESD单元，第一ESD总线和第二ESD总线。第一个ESD总线与IC的任何电源板都没有直接连接。每个ESD单元包括第一二极管，第二二极管和ESD钳位装置。由于具有ESD单元的每个接合焊盘的一对一对应物，本发明通过连续的电荷耗散路径确保ESD连续性，而不管IC正在进行什么类型的针对针脚ESD测试或多少功率 IC的来源。此外，在本发明中还可以部署有源电路（BOAC）结构上的焊盘以为整个IC芯片提供更好的ESD保护。

7. 发明授权

US06573524B2 Method of analyzing DRAM redundancy repair 失效
标题翻译：分析DRAM冗余修复的方法
公开(公告)号：US06573524B2
公开(公告)日：2003-06-03
申请号：US09948073
申请日：2001-09-06
申请人： Ming-Jing Ho
发明人： Ming-Jing Ho
IPC分类号： G01N2188
CPC分类号： G11C29/006 , G11C11/401 , G11C29/24
摘要： A method of determining the correctness of a DRAM redundancy repair. The method is capable of detecting whether a redundancy repair has been properly conducted. The method includes illuminating a die on a wafer with a convergent light beam and observing the physical bit map produced after illumination on a screen. When the convergent light beam aims at a defective array, two semicircular shaped images appear on the screen. When the convergent light beam aims at a redundancy element used in a redundancy repair, a bright line appears on the screen. Through gauging the relative positions between the bright line and the pair of semicircular images, proper replacement by a redundancy element can be ascertained.
摘要翻译：确定DRAM冗余修复的正确性的方法。该方法能够检测冗余修复是否已正确进行。该方法包括用会聚光束在晶片上照射晶片，并观察在屏幕上照明之后产生的物理位图。当收敛光束瞄准有缺陷的阵列时，屏幕上出现两个半圆形图像。当收敛光束瞄准冗余修复中使用的冗余元素时，屏幕上会出现亮线。通过测量亮线和一对半圆形图像之间的相对位置，可以确定冗余元件的适当替换。

8. 发明授权

US07478355B2 Input/output circuits with programmable option and related method 有权
标题翻译：具有可编程选项和相关方法的输入/输出电路
公开(公告)号：US07478355B2
公开(公告)日：2009-01-13
申请号：US10709665
申请日：2004-05-21
申请人： Hsin-Wo Fang , Ming-Jing Ho
发明人： Hsin-Wo Fang , Ming-Jing Ho
IPC分类号： G06F17/50 , G06F7/38 , H03K19/00 , H03K19/173
CPC分类号： G06F17/5068 , H01L27/0207 , H01L27/0248 , H01L27/11898
摘要： A chip with programmable input/output (I/O) circuits has a plurality of layout layers including a plurality of same layouts in a plurality of positions of the layout layers so as to implement a plurality of sub-circuit cells with the same layout, and at least a connection layer having different layouts corresponding to the different positions of the layout layers so that the sub-circuit cells in different positions implement different circuit functions.
摘要翻译：具有可编程输入/输出（I / O）电路的芯片具有在布局层的多个位置中包括多个相同布局的多个布局层，以便实现具有相同布局的多个子电路单元，以及至少具有对应于布局层的不同位置的不同布局的连接层，使得不同位置中的子电路单元实现不同的电路功能。

9. 发明申请

US20130127508A1 SIGNAL DELAY CIRCUIT AND SIGNAL DELAY METHOD 有权
标题翻译：信号延迟电路和信号延迟方法
公开(公告)号：US20130127508A1
公开(公告)日：2013-05-23
申请号：US13480492
申请日：2012-05-25
申请人： Shih-Lun Chen , Ming-Jing Ho
发明人： Shih-Lun Chen , Ming-Jing Ho
IPC分类号： H03H11/26
CPC分类号： H03K5/133 , H03K5/135 , H03K5/14
摘要： A signal delay circuit comprising: a first delay stage, for delaying a first input signal to generate a first delay signal; and a second delay stage, for cooperating with part of delay units of the first delay stage to delay the first delay signal to generate a second delay signal. The signal delay circuit selectively enables the delay stages of the first delay stage or the second delay stage, wherein the signal delay circuit mixes the first delay signal and the second delay signal to generate a first mixed signal when the first delay stage and the second delay stage are both enabled.
摘要翻译：一种信号延迟电路，包括：第一延迟级，用于延迟第一输入信号以产生第一延迟信号; 以及第二延迟级，用于与第一延迟级的延迟单元的一部分协作以延迟第一延迟信号以产生第二延迟信号。所述信号延迟电路选择性地启动所述第一延迟级或所述第二延迟级的延迟级，其中所述信号延迟电路混合所述第一延迟信号和所述第二延迟信号以在所述第一延迟级和所述第二延迟阶段产生第一混合信号舞台都启用了。

10. 发明申请

US20070091521A1 INTEGRATED CIRCUIT WITH ESD PROTECTION CIRCUIT 有权
标题翻译：集成电路与ESD保护电路
公开(公告)号：US20070091521A1
公开(公告)日：2007-04-26
申请号：US11163571
申请日：2005-10-24
申请人： Kuey-Lung Hsueh , Ming-Jing Ho
发明人： Kuey-Lung Hsueh , Ming-Jing Ho
IPC分类号： H02H9/00
CPC分类号： H02H9/046
摘要： An integrated circuit (IC) having an electrostatic discharge (ESD) protection circuit therein is provided. The IC comprises a plurality of bonding pads, a plurality of ESD units, a first ESD bus and a second ESD bus. The first ESD bus has no direct connection with any power pad of the IC. Each ESD unit comprises a first diode, a second diode and an ESD clamping device. Due to the one-to-one correspondent of each bonding pad with an ESD unit, the present invention ensures ESD continuity through a continuous charge dissipation path no matter what kind of pin-to-pin ESD test the IC is undergoing or how many power sources the IC has. In addition, a bonding pad over active circuitry (BOAC) structure can also be deployed in the present invention to provide a better ESD protection for the whole IC chip.
摘要翻译：提供其中具有静电放电（ESD）保护电路的集成电路（IC）。 IC包括多个接合焊盘，多个ESD单元，第一ESD总线和第二ESD总线。第一个ESD总线与IC的任何电源板都没有直接连接。每个ESD单元包括第一二极管，第二二极管和ESD钳位装置。由于具有ESD单元的每个接合焊盘的一对一对应物，本发明通过连续的电荷耗散路径确保ESD连续性，而不管IC正在进行什么类型的针对针脚ESD测试或多少功率 IC的来源。此外，在本发明中还可以部署有源电路（BOAC）结构上的焊盘以为整个IC芯片提供更好的ESD保护。

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