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1. 发明授权

US07956417B2 Method of reducing stacking faults through annealing 失效
标题翻译：通过退火减少堆垛层错的方法
公开(公告)号：US07956417B2
公开(公告)日：2011-06-07
申请号：US12839588
申请日：2010-07-20
申请人： Yun-Yu Wang , Christopher D. Sheraw , Anthony G. Domenicucci , Linda Black , Judson R. Holt , David M. Fried
发明人： Yun-Yu Wang , Christopher D. Sheraw , Anthony G. Domenicucci , Linda Black , Judson R. Holt , David M. Fried
IPC分类号： H01L27/12
CPC分类号： H01L21/84 , H01L21/823807 , H01L21/823878 , H01L27/1203
摘要： Accordingly, in one embodiment of the invention, a method is provided for reducing stacking faults in an epitaxial semiconductor layer. In accordance with such method, a substrate is provided which includes a first single-crystal semiconductor region including a first semiconductor material, the first semiconductor region having a crystal orientation. An epitaxial layer including the first semiconductor material is grown on the first semiconductor region, the epitaxial layer having the crystal orientation. The substrate is then annealed with the epitaxial layer at a temperature greater than 1100 degrees Celsius in an ambient including hydrogen, whereby the step of annealing reduces stacking faults in the epitaxial layer.
摘要翻译：因此，在本发明的一个实施例中，提供了一种用于减少外延半导体层中的堆垛层错的方法。根据这种方法，提供了一种衬底，其包括包括第一半导体材料的第一单晶半导体区域，第一半导体区域具有<110>晶体取向。在第一半导体区域上生长包括第一半导体材料的外延层，具有<110>晶体取向的外延层。然后在包括氢气的环境中，在大于1100摄氏度的温度下将衬底与外延层退火，由此退火步骤减少外延层中的堆垛层错。

2. 发明授权

US07820501B2 Decoder for a stationary switch machine 有权
标题翻译：固定式开关机的解码器
公开(公告)号：US07820501B2
公开(公告)日：2010-10-26
申请号：US11548428
申请日：2006-10-11
申请人： Yun-Yu Wang , Christopher D. Sheraw , Anthony G. Domenicucci , Linda Black , Judson R. Holt , David M. Fried
发明人： Yun-Yu Wang , Christopher D. Sheraw , Anthony G. Domenicucci , Linda Black , Judson R. Holt , David M. Fried
IPC分类号： H01L21/336
CPC分类号： H01L21/84 , H01L21/823807 , H01L21/823878 , H01L27/1203
摘要： Accordingly, in one embodiment of the invention, a method is provided for reducing stacking faults in an epitaxial semiconductor layer. In accordance with such method, a substrate is provided which includes a first single-crystal semiconductor region including a first semiconductor material, the first semiconductor region having a crystal orientation. An epitaxial layer including the first semiconductor material is grown on the first semiconductor region, the epitaxial layer having the crystal orientation. The substrate is then annealed with the epitaxial layer at a temperature greater than 1100 degrees Celsius in an ambient including hydrogen, whereby the step of annealing reduces stacking faults in the epitaxial layer.
摘要翻译：因此，在本发明的一个实施例中，提供了一种用于减少外延半导体层中的堆垛层错的方法。根据这种方法，提供了一种衬底，其包括包括第一半导体材料的第一单晶半导体区域，第一半导体区域具有<110>晶体取向。在第一半导体区域上生长包括第一半导体材料的外延层，具有<110>晶体取向的外延层。然后在包括氢气的环境中，在大于1100摄氏度的温度下将衬底与外延层退火，由此退火步骤减少外延层中的堆垛层错。

3. 发明申请

US20100283089A1 METHOD OF REDUCING STACKING FAULTS THROUGH ANNEALING 失效
标题翻译：通过退火减少堆叠不良的方法
公开(公告)号：US20100283089A1
公开(公告)日：2010-11-11
申请号：US12839588
申请日：2010-07-20
申请人： Yun-Yu Wang , Christopher D. Sheraw , Anthony G. Domenicucci , Linda Black , Judson R. Holt , David M. Fried
发明人： Yun-Yu Wang , Christopher D. Sheraw , Anthony G. Domenicucci , Linda Black , Judson R. Holt , David M. Fried
IPC分类号： H01L29/04
CPC分类号： H01L21/84 , H01L21/823807 , H01L21/823878 , H01L27/1203
摘要： Accordingly, in one embodiment of the invention, a method is provided for reducing stacking faults in an epitaxial semiconductor layer. In accordance with such method, a substrate is provided which includes a first single-crystal semiconductor region including a first semiconductor material, the first semiconductor region having a crystal orientation. An epitaxial layer including the first semiconductor material is grown on the first semiconductor region, the epitaxial layer having the crystal orientation. The substrate is then annealed with the epitaxial layer at a temperature greater than 1100 degrees Celsius in an ambient including hydrogen, whereby the step of annealing reduces stacking faults in the epitaxial layer.
摘要翻译：因此，在本发明的一个实施例中，提供了一种用于减少外延半导体层中的堆垛层错的方法。根据这种方法，提供了一种衬底，其包括包括第一半导体材料的第一单晶半导体区域，第一半导体区域具有<110>晶体取向。在第一半导体区域上生长包括第一半导体材料的外延层，具有<110>晶体取向的外延层。然后在包括氢气的环境中，在大于1100摄氏度的温度下将衬底与外延层退火，由此退火步骤减少外延层中的堆垛层错。

4. 发明申请

US20080087961A1 METHOD OF REDUCING STACKING FAULTS THROUGH ANNEALING 有权
标题翻译：通过退火减少堆叠不良的方法
公开(公告)号：US20080087961A1
公开(公告)日：2008-04-17
申请号：US11548428
申请日：2006-10-11
申请人： Yun-Yu Wang , Christopher D. Sheraw , Anthony G. Domenicucci , Linda Black , Judson R. Holt , David M. Fried
发明人： Yun-Yu Wang , Christopher D. Sheraw , Anthony G. Domenicucci , Linda Black , Judson R. Holt , David M. Fried
IPC分类号： H01L27/092 , H01L21/8232
CPC分类号： H01L21/84 , H01L21/823807 , H01L21/823878 , H01L27/1203
摘要： Accordingly, in one embodiment of the invention, a method is provided for reducing stacking faults in an epitaxial semiconductor layer. In accordance with such method, a substrate is provided which includes a first single-crystal semiconductor region including a first semiconductor material, the first semiconductor region having a crystal orientation. An epitaxial layer including the first semiconductor material is grown on the first semiconductor region, the epitaxial layer having the crystal orientation. The substrate is then annealed with the epitaxial layer at a temperature greater than 1100 degrees Celsius in an ambient including hydrogen, whereby the step of annealing reduces stacking faults in the epitaxial layer.
摘要翻译：因此，在本发明的一个实施例中，提供了一种用于减少外延半导体层中的堆垛层错的方法。根据这种方法，提供了一种衬底，其包括包括第一半导体材料的第一单晶半导体区域，第一半导体区域具有<110>晶体取向。在第一半导体区域上生长包括第一半导体材料的外延层，具有<110>晶体取向的外延层。然后在包括氢气的环境中，在大于1100摄氏度的温度下将衬底与外延层退火，由此退火步骤减少外延层中的堆垛层错。

5. 发明申请

US20090090974A1 DUAL STRESS LINER STRUCTURE HAVING SUBSTANTIALLY PLANAR INTERFACE BETWEEN LINERS AND RELATED METHOD 审中-公开
标题翻译：具有线性和相关方法之间的主要平面界面的双应力衬里结构
公开(公告)号：US20090090974A1
公开(公告)日：2009-04-09
申请号：US11868567
申请日：2007-10-08
申请人： Gregory Costrini , David M. Fried , Werner A. Rausch , Christopher D. Sheraw
发明人： Gregory Costrini , David M. Fried , Werner A. Rausch , Christopher D. Sheraw
IPC分类号： H01L27/092 , H01L21/311
CPC分类号： H01L21/823807 , H01L21/31111 , H01L29/7843
摘要： A dual stress liner structure having a substantially planar interface between liners and a related method are disclosed. In one embodiment, a dual stress liner structure may include a tensile stress liner over an NFET, the NFET including a PFET adjacent thereto; and a compressive stress liner over the PFET, wherein an upper surface of the compressive stress liner is substantially planar with an upper surface of the tensile stress liner at an interface therebetween.
摘要翻译：公开了一种在衬垫之间具有基本平坦的界面的双重应力衬垫结构和相关方法。在一个实施例中，双应力衬垫结构可以包括在NFET上的拉伸应力衬垫，NFET包括与其相邻的PFET; 以及PFET上的压应力衬垫，其中所述压应力衬垫的上表面在其间的界面处与所述拉伸应力衬垫的上表面基本上是平面的。

6. 发明授权

US07884396B2 Method and structure for self-aligned device contacts 有权
标题翻译：自对准设备触点的方法和结构
公开(公告)号：US07884396B2
公开(公告)日：2011-02-08
申请号：US12194563
申请日：2008-08-20
申请人： Gregory Costrini , David M. Fried
发明人： Gregory Costrini , David M. Fried
IPC分类号： H01L23/532
CPC分类号： H01L29/458 , H01L21/76829 , H01L21/76897 , H01L21/84 , H01L27/12 , H01L29/41733 , H01L29/665 , H01L29/6656 , H01L29/7843 , H01L2924/0002 , H01L2924/00
摘要： Disclosed are embodiments of a semiconductor structure with a partially self-aligned contact in lower portion of the contact is enlarged to reduce resistance without impacting device yield. Additionally, the structure optionally incorporates a thick middle-of-the-line (MOL) nitride stress film to enhance carrier mobility. Embodiments of the method of forming the structure comprise forming a sacrificial section in the intended location of the contact. This section is patterned so that it is self-aligned to the gate electrodes and only occupies space that is intended for the future contact. Dielectric layer(s) (e.g., an optional stress layer followed by an interlayer dielectric) may be deposited once the sacrificial section is in place. Conventional contact lithography is used to etch a contact hole through the dielectric layer(s) to the sacrificial section. The sacrificial section is then selectively removed to form a cavity and the contact is formed in the cavity and contact hole.
摘要翻译：公开了在触点下部具有部分自对准接触的半导体结构的实施例被扩大以降低电阻而不会影响器件的产量。另外，该结构可选地包含厚中间线（MOL）氮化物应力膜以增强载流子迁移率。形成结构的方法的实施例包括在接触的预期位置形成牺牲部分。该部分被图案化，使得其与栅电极自对准，并且仅占用用于将来接触的空间。一旦牺牲部分就位就可以沉积介质层（例如，可选的应力层，然后是层间电介质）。常规的接触光刻用于蚀刻通过介电层到牺牲部分的接触孔。然后选择性地去除牺牲部分以形成空腔，并且在空腔和接触孔中形成接触。

7. 发明授权

US07645650B2 Double gated transistor and method of fabrication 有权
标题翻译：双门控晶体管和制造方法
公开(公告)号：US07645650B2
公开(公告)日：2010-01-12
申请号：US11774663
申请日：2007-07-09
申请人： Andres Bryant , Meikei Ieong , K. Paul Muller , Edward J. Nowak , David M. Fried , Jed Rankin
发明人： Andres Bryant , Meikei Ieong , K. Paul Muller , Edward J. Nowak , David M. Fried , Jed Rankin
IPC分类号： H01L21/84
CPC分类号： H01L29/4908 , H01L21/823842 , H01L27/092 , H01L29/66795 , H01L29/785
摘要： A method for forming a transistor. A semiconductor substrate is provided. The semiconductor substrate is patterned to provide a first body edge. A first gate structure of a first fermi level is provided adjacent the first body edge. The semiconductor substrate is patterned to provide a second body edge. The first and second body edges of the semiconductor substrate define a transistor body. A second gate structure of a second fermi level is provided adjacent the second body edge. A substantially uniform dopant concentration density is formed throughout the transistor body.
摘要翻译：一种形成晶体管的方法。提供半导体衬底。图案化半导体衬底以提供第一本体边缘。在第一身体边缘附近提供第一费米能级的第一门结构。图案化半导体衬底以提供第二本体边缘。半导体衬底的第一和第二主体边缘限定晶体管体。在第二身体边缘附近设置第二费米能级的第二门结构。在整个晶体管本体中形成基本均匀的掺杂剂浓度密度。

8. 发明申请

US20090134463A1 SEMICONDUCTOR STRUCTURE AND SYSTEM FOR FABRICATING AN INTEGRATED CIRCUIT CHIP 有权
标题翻译：用于制造集成电路芯片的半导体结构和系统
公开(公告)号：US20090134463A1
公开(公告)日：2009-05-28
申请号：US12348344
申请日：2009-01-05
申请人： Wagdi W. Abadeer , Jeffrey S. Brown , David M. Fried , Robert J. Gauthier, JR. , Edward J. Nowak , Jed H. Rankin , William R. Tonti
发明人： Wagdi W. Abadeer , Jeffrey S. Brown , David M. Fried , Robert J. Gauthier, JR. , Edward J. Nowak , Jed H. Rankin , William R. Tonti
IPC分类号： H01L29/78
CPC分类号： H01L29/786 , H01L21/845 , H01L27/1211 , H01L29/4908 , H01L29/78615
摘要： A semiconductor structure and a system for fabricating an integrated circuit chip. The semiconductor structure includes: a buried oxide layer on a semiconductor wafer; a thin fin structure on the buried oxide layer, wherein the thin fin structure includes a first hard mask on a semiconductor fin, wherein the semiconductor fin is disposed between the first hard mask and a surface of the buried oxide layer; and a thick mesa structure on the buried oxide layer, and wherein the thick mesa structure includes a semiconductor mesa. The system for fabricating an integrated circuit chip enables: providing a buried oxide layer on and in direct mechanical contact with a semiconductor wafer; and concurrently forming at least one fin-type field effect transistor and at least one thick-body device on the buried oxide layer.
摘要翻译：一种半导体结构和用于制造集成电路芯片的系统。半导体结构包括：半导体晶片上的掩埋氧化物层; 在所述掩埋氧化物层上的薄翅片结构，其中所述薄翅片结构包括半导体鳍片上的第一硬掩模，其中所述半导体鳍片设置在所述第一硬掩模和所述掩埋氧化物层的表面之间; 以及在所述掩埋氧化物层上的厚的台面结构，并且其中所述厚的台面结构包括半导体台面。用于制造集成电路芯片的系统能够：提供与半导体晶片直接机械接触的掩埋氧化物层; 并且在掩埋氧化物层上同时形成至少一个鳍式场效应晶体管和至少一个厚体器件。

9. 发明授权

US07517806B2 Integrated circuit having pairs of parallel complementary FinFETs 失效
标题翻译：具有成对的并联互补FinFET的集成电路
公开(公告)号：US07517806B2
公开(公告)日：2009-04-14
申请号：US11186748
申请日：2005-07-21
申请人： Andres Bryant , William F. Clark, Jr. , David M. Fried , Mark D. Jaffe , Edward J. Nowak , John J. Pekarik , Christopher S. Putnam
发明人： Andres Bryant , William F. Clark, Jr. , David M. Fried , Mark D. Jaffe , Edward J. Nowak , John J. Pekarik , Christopher S. Putnam
IPC分类号： H01L21/302
CPC分类号： H01L21/84 , H01L21/3086 , H01L21/3088 , H01L21/823821 , H01L27/1203 , H01L29/66795 , H01L29/785 , Y10S438/947
摘要： A method and structure for an integrated circuit structure that utilizes complementary fin-type field effect transistors (FinFETs) is disclosed. The invention has a first-type of FinFET which includes a first fin, and a second-type of FinFET which includes a second fin running parallel to the first fin. The invention also has an insulator fin positioned between the source/drain regions of the first first-type of FinFET and the second-type of FinFET. The insulator fin has approximately the same width dimensions as the first fin and the second fin, such that the spacing between the first-type of FinFET and the second-type of FinFET is approximately equal to the width of one fin. The invention also has a common gate formed over channel regions of the first-type of FinFET and the second-type of FinFET. The gate includes a first impurity doping region adjacent the first-type of FinFET and a second impurity doping region adjacent the second-type of FinFET. The differences between the first impurity doping region and the second impurity doping region provide the gate with different work functions related to differences between the first-type of FinFET and the second-type of FinFET. The first fin and the second fin have approximately the same width.
摘要翻译：公开了利用互补翅片型场效应晶体管（FinFET）的集成电路结构的方法和结构。本发明具有包括第一鳍片的第一类型的FinFET和包括与第一鳍片平行的第二鳍片的第二类型的FinFET。本发明还具有位于第一第一类型FinFET的源极/漏极区域和第二类型FinFET之间的绝缘体鳍片。绝缘体鳍片具有与第一鳍片和第二鳍片大致相同的宽度尺寸，使得第一类型的FinFET和第二类型的FinFET之间的间隔大致等于一个鳍片的宽度。本发明还具有形成在第一类型FinFET和第二类型FinFET的沟道区上的公共栅极。栅极包括与第一类型的FinFET相邻的第一杂质掺杂区域和与第二类型的FinFET相邻的第二杂质掺杂区域。第一杂质掺杂区域和第二杂质掺杂区域之间的差异为栅极提供与第一类型FinFET和第二类型FinFET之间的差异有关的不同功函数。第一鳍片和第二鳍片具有大致相同的宽度。

10. 发明授权

US07288445B2 Double gated transistor and method of fabrication 有权
标题翻译：双门控晶体管及其制造方法
公开(公告)号：US07288445B2
公开(公告)日：2007-10-30
申请号：US11125063
申请日：2005-05-09
申请人： Andres Bryant , Meikei Ieong , K. Paul Muller , Edward J. Nowak , David M. Fried , Jed Rankin
发明人： Andres Bryant , Meikei Ieong , K. Paul Muller , Edward J. Nowak , David M. Fried , Jed Rankin
IPC分类号： H01L21/84
CPC分类号： H01L29/4908 , H01L21/823842 , H01L27/092 , H01L29/66795 , H01L29/785
摘要： Accordingly, the present invention provides a double gated transistor and a method for forming the same that results in improved device performance and density. The preferred embodiment of the present invention uses provides a double gated transistor with asymmetric gate doping, where one of the double gates is doped degenerately n-type and the other degenerately p-type. By doping on of the gates n-type, and the other p-type, the threshold voltage of the resulting device is improved. In particular, by asymmetrically doping the two gates, the resulting transistor can, with adequate doping of the body, have a threshold voltage in a range that enables low-voltage CMOS operation. For example, a transistor can be created that has a threshold voltage between 0V and 0.5V for nFETs and between 0 and −0.5V for pFETs.
摘要翻译：因此，本发明提供一种双门控晶体管及其形成方法，其导致改进的器件性能和密度。本发明的优选实施例提供了具有不对称栅极掺杂的双门控晶体管，其中双栅极中的一个被简并掺杂为n型，另一个为简并p型。通过掺杂栅极n型和另一种p型，所得器件的阈值电压得到改善。特别地，通过不对称地掺杂两个栅极，所得到的晶体管可以通过适当掺杂的体，在允许低电压CMOS操作的范围内具有阈值电压。例如，可以产生对于nFET具有在0V和0.5V之间的阈值电压并且对于pFET而言在0和-0.5V之间的晶体管。

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