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1. 发明授权

US08916426B2 Passive devices for FinFET integrated circuit technologies 有权
标题翻译： FinFET集成电路技术的无源器件
公开(公告)号：US08916426B2
公开(公告)日：2014-12-23
申请号：US13431414
申请日：2012-03-27
申请人： William F. Clark, Jr. , Robert J. Gauthier, Jr. , Terence B. Hook , Junjun Li , Theodorus E. Standaert , Thomas A. Wallner
发明人： William F. Clark, Jr. , Robert J. Gauthier, Jr. , Terence B. Hook , Junjun Li , Theodorus E. Standaert , Thomas A. Wallner
IPC分类号： H01L21/338 , H01L29/66 , H01L21/8238 , H01L21/84
CPC分类号： H01L27/1211 , H01L21/7624 , H01L21/823821 , H01L21/845 , H01L27/0207 , H01L27/0262 , H01L27/0924 , H01L27/1203 , H01L29/66795 , H01L29/785
摘要： Device structures, design structures, and fabrication methods for passive devices that may be used as electrostatic discharge protection devices in fin-type field-effect transistor integrated circuit technologies. A device region is formed in a trench and is coupled with a handle wafer of a semiconductor-on-insulator substrate. The device region extends through a buried insulator layer of the semiconductor-on-insulator substrate toward a top surface of a device layer of the semiconductor-on-insulator substrate. The device region is comprised of lightly-doped semiconductor material. The device structure further includes a doped region formed in the device region and that defines a junction. A portion of the device region is laterally positioned between the doped region and the buried insulator layer of the semiconductor-on-insulator substrate. Another region of the device layer may be patterned to form fins for fin-type field-effect transistors.
摘要翻译：无源器件的器件结构，设计结构和制造方法可用作鳍式场效应晶体管集成电路技术中的静电放电保护器件。器件区域形成在沟槽中并且与绝缘体上半导体衬底的处理晶片耦合。器件区域延伸穿过绝缘体上半导体衬底的掩埋绝缘体层朝向绝缘体上半导体衬底的器件层的顶表面。器件区域由轻掺杂的半导体材料组成。器件结构还包括形成在器件区域中并限定结的掺杂区域。器件区域的一部分横向地位于绝缘体上半导体衬底的掺杂区域和掩埋绝缘体层之间。可以对器件层的另一区域进行构图以形成翅片型场效应晶体管的鳍片。

2. 发明授权

US08891212B2 RC-triggered semiconductor controlled rectifier for ESD protection of signal pads 有权
标题翻译： RC触发半导体可控整流器用于信号焊盘的ESD保护
公开(公告)号：US08891212B2
公开(公告)日：2014-11-18
申请号：US13079946
申请日：2011-04-05
申请人： Michel J. Abou-Khalil , Robert J. Gauthier, Jr. , Tom C. Lee , Junjun Li , Souvick Mitra , Christopher S. Putnam
发明人： Michel J. Abou-Khalil , Robert J. Gauthier, Jr. , Tom C. Lee , Junjun Li , Souvick Mitra , Christopher S. Putnam
IPC分类号： H02H9/04 , H03K19/003 , H01L27/02
CPC分类号： H02H9/046 , H01L27/0262 , H03K19/00361 , Y10T29/49002
摘要： RC-trigger circuits for a semiconductor controlled rectifier (SCR), methods of providing electrostatic discharge (ESD) protection, and design structures for a RC-trigger circuit. The RC-trigger circuit is coupled to an input/output (I/O) signal pad by an isolation diode and is coupled to a power supply voltage by a power supply diode. Under normal operating conditions, the isolation diode is reverse biased, isolating the RC-trigger circuit from the input/output (I/O) pad, and the power supply diode is forward biased so that the RC-trigger circuit is supplied with power. The isolation diode may become forward biased during ESD events while the chip is unpowered, causing the RC-trigger circuit to trigger an SCR configured protect the signal pad from ESD into a conductive state. The power supply diode may become reverse biased during the ESD event, which isolates the power supply rail from the ESD voltage pulse.
摘要翻译：用于半导体可控整流器（SCR）的RC触发电路，提供静电放电（ESD）保护的方法以及用于RC触发电路的设计结构。 RC触发电路通过隔离二极管耦合到输入/输出（I / O）信号焊盘，并通过电源二极管耦合到电源电压。在正常工作条件下，隔离二极管反向偏置，将RC触发电路与输入/输出（I / O）焊盘隔离，电源二极管正向偏置，使RC触发电路供电。在ESD事件期间，隔离二极管可能会在芯片未上电时产生正向偏置，导致RC触发电路触发SCR配置，从而将信号焊盘从ESD保护到导通状态。在ESD事件期间，电源二极管可能会反向偏置，从而将电源轨与ESD电压脉冲隔离。

3. 发明授权

US08760827B2 Robust ESD protection circuit, method and design structure for tolerant and failsafe designs 有权
标题翻译：强大的ESD保护电路，容错和故障安全设计的方法和设计结构
公开(公告)号：US08760827B2
公开(公告)日：2014-06-24
申请号：US12424169
申请日：2009-04-15
申请人： John B. Campi, Jr. , Shunhua T. Chang , Kiran V. Chatty , Robert J. Gauthier, Jr. , Junjun Li , Mujahid Muhammad
发明人： John B. Campi, Jr. , Shunhua T. Chang , Kiran V. Chatty , Robert J. Gauthier, Jr. , Junjun Li , Mujahid Muhammad
IPC分类号： H02H3/22
CPC分类号： H01L27/0274 , H01L2924/0002 , H01L2924/00
摘要： A robust ESD protection circuit, method and design structure for tolerant and failsafe designs are disclosed. A circuit includes a middle junction control circuit that turns off a top NFET of a stacked NFET electrostatic discharge (ESD) protection circuit during an ESD event.
摘要翻译：公开了用于容错和故障安全设计的强大的ESD保护电路，方法和设计结构。电路包括在ESD事件期间关闭层叠的NFET静电放电（ESD）保护电路的顶部NFET的中间接点控制电路。

4. 发明授权

US08692290B2 Silicon controlled rectifier structure with improved junction breakdown and leakage control 有权
标题翻译：可控硅整流器结构，具有改进的结击穿和泄漏控制
公开(公告)号：US08692290B2
公开(公告)日：2014-04-08
申请号：US13226838
申请日：2011-09-07
申请人： Kiran V. Chatty , Robert J. Gauthier, Jr. , Junjun Li , Alain Loiseau
发明人： Kiran V. Chatty , Robert J. Gauthier, Jr. , Junjun Li , Alain Loiseau
IPC分类号： H01L29/73 , H01L21/331 , G06F17/50
CPC分类号： H01L29/66363 , G06F17/50 , H01L27/0262 , H01L29/74 , H01L29/7436 , H02H9/04
摘要： Device structures and design structures for a silicon controlled rectifier, as well as methods for fabricating a silicon controlled rectifier. The device structure includes first and second layers of different materials disposed on a top surface of a device region containing first and second p-n junctions of the silicon controlled rectifier. The first layer is laterally positioned on the top surface in vertical alignment with the first p-n junction. The second layer is laterally positioned on the top surface of the device region in vertical alignment with the second p-n junction. The material comprising the second layer has a higher electrical resistivity than the material comprising the first layer.
摘要翻译：可控硅整流器的器件结构和设计结构，以及制造可控硅整流器的方法。器件结构包括设置在包含可控硅整流器的第一和第二p-n结的器件区域的顶表面上的不同材料的第一和第二层。第一层横向定位在与第一p-n结垂直对准的顶表面上。第二层横向定位在与第二p-n结垂直对准的器件区域的顶表面上。包括第二层的材料具有比包含第一层的材料更高的电阻率。

5. 发明授权

US08634174B2 Gate dielectric breakdown protection during ESD events 有权
标题翻译： ESD事件期间的栅极绝缘击穿保护
公开(公告)号：US08634174B2
公开(公告)日：2014-01-21
申请号：US13115492
申请日：2011-05-25
申请人： Michel J. Abou-Khalil , James P. Di Sarro , Robert J. Gauthier, Jr. , Junjun Li , Souvick Mitra , Yang Yang
发明人： Michel J. Abou-Khalil , James P. Di Sarro , Robert J. Gauthier, Jr. , Junjun Li , Souvick Mitra , Yang Yang
IPC分类号： H02H9/00 , H02H3/22
CPC分类号： H02H9/046 , G06F17/5063 , H01L27/0285
摘要： Protection circuits, design structures, and methods for isolating the gate and gate dielectric of a field-effect transistor from electrostatic discharge (ESD). A protection field-effect transistor is located between a protected field-effect transistor and a voltage rail. Under normal operating conditions, the protection field-effect transistor is saturated so that the protected field-effect transistor is coupled to the voltage rail. The protection field-effect transistor may be driven into a cutoff condition in response to an ESD event while the chip is unpowered, which increases the series resistance of an ESD current path between the gate of the protected field-effect transistor and the voltage rail. The voltage drop across the protection field-effect transistor may reduce the ESD stress on the gate dielectric of the protected field-effect transistor. Alternatively, the gate and source of an existing field-effect transistor are selectively coupled provide ESD isolation to the protected field-effect transistor.
摘要翻译：用于将场效应晶体管的栅极和栅极电介质与静电放电（ESD）隔离的保护电路，设计结构和方法。保护场效应晶体管位于受保护的场效应晶体管和电压轨之间。在正常工作条件下，保护场效应晶体管饱和，使受保护的场效应晶体管耦合到电压轨。保护场效应晶体管可以在芯片无电源时响应于ESD事件而被驱动成截止状态，这增加了受保护的场效应晶体管的栅极与电压轨之间的ESD电流路径的串联电阻。保护场效应晶体管两端的电压降可以降低受保护的场效应晶体管的栅极电介质上的ESD应力。或者，现有的场效应晶体管的栅极和源极被选择性地耦合到提供ESD隔离到受保护的场效应晶体管。

6. 发明授权

US08610217B2 Self-protected electrostatic discharge field effect transistor (SPESDFET), an integrated circuit incorporating the SPESDFET as an input/output (I/O) pad driver and associated methods of forming the SPESDFET and the integrated circuit 有权
标题翻译：自保护静电放电场效应晶体管（SPESDFET），一种集成了SPESDFET作为输入/输出（I / O）焊盘驱动器的集成电路，以及形成SPESDFET和集成电路的相关方法
公开(公告)号：US08610217B2
公开(公告)日：2013-12-17
申请号：US12967114
申请日：2010-12-14
申请人： Robert J. Gauthier, Jr. , Mahender Kumar , Junjun Li , Dustin K. Slisher
发明人： Robert J. Gauthier, Jr. , Mahender Kumar , Junjun Li , Dustin K. Slisher
IPC分类号： H01L23/62
CPC分类号： H01L23/60 , H01L27/0266 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： Disclosed are embodiments of a self-protected electrostatic discharge field effect transistor (SPESDFET). In the SPESDFET embodiments, a resistance region is positioned laterally between two discrete sections of a deep source/drain region: a first section that is adjacent to the channel region and a second section that is contacted. The second section of the deep source/drain region is silicided, but the first section adjacent to the channel region and the resistance region are non-silicided. Additionally, the gate structure can be either silicided or non-silicided. With such a configuration, the disclosed SPESDFET provides robust ESD protection without consuming additional area and without altering the basic FET design (e.g., without increasing the distance between the deep source/drain regions and the channel region). Also disclosed are embodiments of integrated circuit that incorporates the SPESDFET as an input/output (I/O) pad driver and method embodiments for forming the SPESDFET and the integrated circuit.
摘要翻译：公开了自保护静电放电场效应晶体管（SPESDFET）的实施例。在SPESDFET实施例中，电阻区域横向定位在深源极/漏极区域的两个离散部分之间：与沟道区域相邻的第一部分和接触的第二部分。深源极/漏极区域的第二部分被硅化，但是与沟道区域和电阻区域相邻的第一部分是非硅化的。另外，栅极结构可以是硅化的或非硅化的。利用这种配置，所公开的SPESDFET提供强大的ESD保护，而不消耗额外的面积，而不改变基本FET设计（例如，不增加深源/漏区和沟道区之间的距离）。还公开了将SPESDFET作为输入/输出（I / O）焊盘驱动器和用于形成SPESDFET和集成电路的方法实施例的集成电路的实施例。

7. 发明申请

US20130258532A1 PASSIVE DEVICES FOR FINFET INTEGRATED CIRCUIT TECHNOLOGIES 有权
公开(公告)号：US20130258532A1
公开(公告)日：2013-10-03
申请号：US13431347
申请日：2012-03-27
申请人： William F. Clark, JR. , Robert J. Gauthier, JR. , Junjun Li
发明人： William F. Clark, JR. , Robert J. Gauthier, JR. , Junjun Li
IPC分类号： H01L27/06 , H01L21/20 , H01L21/33 , G06F17/50 , H01L21/8249 , H01L29/06 , H01L29/73 , H02H7/20 , H01L21/331
CPC分类号： H01L27/0262 , G06F17/5072 , H01L21/8249 , H01L21/845 , H01L27/0255 , H01L27/06 , H01L27/1211 , H01L29/06
摘要： Device structures, design structures, and fabrication methods for passive devices that may be used as electrostatic discharge protection devices in fin-type field-effect transistor integrated circuit technologies. A portion of a device layer of a semiconductor-on-insulator substrate is patterned to form a device region. A well of a first conductivity type is formed in the epitaxial layer and the device region. A doped region of a second conductivity type is formed in the well and defines a junction with a portion of the well. The epitaxial layer includes an exterior sidewall spaced from an exterior sidewall of the device region. Another portion of the device layer may be patterned to form fins for fin-type field-effect transistors.

8. 发明申请

US20130009207A1 VERTICAL NPNP STRUCTURE IN A TRIPLE WELL CMOS PROCESS 有权
标题翻译：三维CMOS工艺中的垂直NPNP结构
公开(公告)号：US20130009207A1
公开(公告)日：2013-01-10
申请号：US13614072
申请日：2012-09-13
申请人： John B. Campi, JR. , Shunhua T. Chang , Kiran V. Chatty , Robert J. Gauthier, JR. , Junjun Li , Rahul Mishra , Mujahid Muhammad
发明人： John B. Campi, JR. , Shunhua T. Chang , Kiran V. Chatty , Robert J. Gauthier, JR. , Junjun Li , Rahul Mishra , Mujahid Muhammad
IPC分类号： H01L29/74
CPC分类号： H01L29/74 , H01L21/823892 , H01L27/0262 , H01L27/0928 , H01L2924/0002 , H01L2924/00
摘要： A vertical NPNP structure fabricated using a triple well CMOS process, as well as methods of making the vertical NPNP structure, methods of providing electrostatic discharge (ESD) protection, and design structures for a BiCMOS integrated circuit. The vertical NPNP structure may be used to provide on-chip protection to an input/output (I/O) pad from negative-voltage ESD events. A vertical PNPN structure may be also used to protect the same I/O pad from positive-voltage ESD events.
摘要翻译：使用三阱CMOS工艺制造的垂直NPNP结构，以及制造垂直NPNP结构的方法，提供静电放电（ESD）保护的方法和BiCMOS集成电路的设计结构。垂直NPNP结构可用于从负电压ESD事件向输入/输出（I / O）焊盘提供片上保护。也可以使用垂直PNPN结构来保护相同的I / O焊盘免受正电压ESD事件的影响。

9. 发明申请

US20120300349A1 GATE DIELECTRIC BREAKDOWN PROTECTION DURING ESD EVENTS 有权
标题翻译：防静电事件期间门电绝缘保护
公开(公告)号：US20120300349A1
公开(公告)日：2012-11-29
申请号：US13115492
申请日：2011-05-25
申请人： Michel J. Abou-Khalil , James P. Di Sarro , Robert J. Gauthier, JR. , Junjun Li , Souvick Mitra , Yang Yang
发明人： Michel J. Abou-Khalil , James P. Di Sarro , Robert J. Gauthier, JR. , Junjun Li , Souvick Mitra , Yang Yang
IPC分类号： H02H9/00 , G06F17/50
CPC分类号： H02H9/046 , G06F17/5063 , H01L27/0285
摘要： Protection circuits, design structures, and methods for isolating the gate and gate dielectric of a field-effect transistor from electrostatic discharge (ESD). A protection field-effect transistor is located between a protected field-effect transistor and a voltage rail. Under normal operating conditions, the protection field-effect transistor is saturated so that the protected field-effect transistor is coupled to the voltage rail. The protection field-effect transistor may be driven into a cutoff condition in response to an ESD event while the chip is unpowered, which increases the series resistance of an ESD current path between the gate of the protected field-effect transistor and the voltage rail. The voltage drop across the protection field-effect transistor may reduce the ESD stress on the gate dielectric of the protected field-effect transistor. Alternatively, the gate and source of an existing field-effect transistor are selectively coupled provide ESD isolation to the protected field-effect transistor.
摘要翻译：用于将场效应晶体管的栅极和栅极电介质与静电放电（ESD）隔离的保护电路，设计结构和方法。保护场效应晶体管位于受保护的场效应晶体管和电压轨之间。在正常工作条件下，保护场效应晶体管饱和，使受保护的场效应晶体管耦合到电压轨。保护场效应晶体管可以在芯片无电源时响应于ESD事件而被驱动成截止状态，这增加了受保护的场效应晶体管的栅极与电压轨之间的ESD电流路径的串联电阻。保护场效应晶体管两端的电压降可以降低受保护的场效应晶体管的栅极电介质上的ESD应力。或者，现有的场效应晶体管的栅极和源极被选择性地耦合到提供ESD隔离到受保护的场效应晶体管。

10. 发明申请

US20120176721A1 ELECTROSTATIC DISCHARGE DEVICE CONTROL AND STRUCTURE 失效
标题翻译：静电放电装置的控制和结构
公开(公告)号：US20120176721A1
公开(公告)日：2012-07-12
申请号：US12987276
申请日：2011-01-10
申请人： Robert J. GAUTHIER, JR. , Junjun LI , Souvick MITRA
发明人： Robert J. GAUTHIER, JR. , Junjun LI , Souvick MITRA
IPC分类号： H05F3/02
CPC分类号： H01L27/0285
摘要： Structures and methods for electrostatic discharge (ESD) device control in an integrated circuit are provided. An ESD protection structure includes an input/output (I/O) pad, and an ESD field effect transistor (FET) including a drain connected to the I/O pad, a source connected to ground, and a gate. A first control FET includes a drain connected to the I/O pad, a source connected to the gate of the ESD FET, and a gate connected to ground. A second control FET includes a drain connected to the gate of the ESD FET and the source of the first control FET, a source connected to ground, and a gate connected to the I/O pad.
摘要翻译：提供集成电路中静电放电（ESD）器件控制的结构和方法。 ESD保护结构包括输入/输出（I / O）焊盘和包括连接到I / O焊盘的漏极，连接到地的源极和栅极的ESD场效应晶体管（FET）。第一控制FET包括连接到I / O焊盘的漏极，连接到ESD FET的栅极的源极和连接到地的栅极。第二控制FET包括连接到ESD FET的栅极和第一控制FET的源极的漏极，连接到地的源极和连接到I / O焊盘的栅极。

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