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    • 1. 发明授权
    • Semiconductor device and method of manufacturing the same
    • 半导体装置及其制造方法
    • US08946668B2
    • 2015-02-03
    • US13574405
    • 2011-01-21
    • Yukishige SaitoKimihiko ItoHiromitsu Hada
    • Yukishige SaitoKimihiko ItoHiromitsu Hada
    • H01L29/02H01L47/00H01L23/522H01L45/00
    • H01L23/5228H01L45/04H01L45/1233H01L45/145H01L45/1675H01L2924/0002H01L2924/00
    • Disclosed is a semiconductor device including a resistive change element between a first wiring and a second wiring, which are arranged in a vertical direction so as to be adjacent to each other, with an interlayer insulation film being interposed on a semiconductor substrate. The resistive change element includes a lower electrode, a resistive change element film made of a metal oxide and an upper electrode. Since the upper electrode on the resistive change element film is formed as part of a plug for the second wiring, a structure in which a side surface of the upper electrode is not in direct contact with the side surface of the metal oxide or the lower electrode is provided so that it is possible to realize excellent device characteristics, even when a byproduct is adhered to the side wall of the metal oxide or the lower electrode in the etching thereof.
    • 公开了一种半导体器件,其包括在第一布线和第二布线之间的电阻变化元件,它们在垂直方向上彼此相邻地布置,层间绝缘膜插入在半导体衬底上。 电阻变化元件包括下电极,由金属氧化物和上电极制成的电阻变化元件膜。 由于电阻变化元件膜上的上电极被形成为用于第二布线的插头的一部分,所以上电极的侧表面不与金属氧化物或下电极的侧表面直接接触的结构 即使在其蚀刻中副产物附着在金属氧化物或下电极的侧壁上时,也可以实现优异的器件特性。
    • 2. 发明申请
    • SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
    • 半导体器件及其制造方法
    • US20120286231A1
    • 2012-11-15
    • US13574405
    • 2011-01-21
    • Yukishige SaitoKimihiko ItoHiromitsu Hada
    • Yukishige SaitoKimihiko ItoHiromitsu Hada
    • H01L45/00H01L21/02
    • H01L23/5228H01L45/04H01L45/1233H01L45/145H01L45/1675H01L2924/0002H01L2924/00
    • Disclosed is a semiconductor device including a resistive change element between a first wiring and a second wiring, which are arranged in a vertical direction so as to be adjacent to each other, with an interlayer insulation film being interposed on a semiconductor substrate. The resistive change element includes a lower electrode, a resistive change element film made of a metal oxide and an upper electrode. Since the upper electrode on the resistive change element film is formed as part of a plug for the second wiring, a structure in which a side surface of the upper electrode is not in direct contact with the side surface of the metal oxide or the lower electrode is provided so that it is possible to realize excellent device characteristics, even when a byproduct is adhered to the side wall of the metal oxide or the lower electrode in the etching thereof.
    • 公开了一种半导体器件,其包括在第一布线和第二布线之间的电阻变化元件,它们在垂直方向上彼此相邻地布置,层间绝缘膜插入在半导体衬底上。 电阻变化元件包括下电极,由金属氧化物和上电极制成的电阻变化元件膜。 由于电阻变化元件膜上的上电极被形成为用于第二布线的插头的一部分,所以上电极的侧表面不与金属氧化物或下电极的侧表面直接接触的结构 即使在其蚀刻中副产物附着在金属氧化物或下电极的侧壁上时,也可以实现优异的器件特性。
    • 6. 发明授权
    • Semiconductor device and method that includes reverse tapering multiple layers
    • 半导体器件和方法,包括反向逐渐变细多层
    • US07211517B2
    • 2007-05-01
    • US10476978
    • 2002-09-05
    • Yukishige SaitoRisho KohJyonu RiHisashi Takemura
    • Yukishige SaitoRisho KohJyonu RiHisashi Takemura
    • H01L21/311
    • H01L29/66757H01L21/76264H01L21/76283H01L29/66742H01L29/66772H01L29/78609H01L29/78618H01L29/78636Y10S438/978
    • A method of manufacturing a semiconductor device of the present invention includes (a) sequentially forming a gate insulating film 14, a first conductive layer 15 and a first insulating film 16 on a semiconductor layer 13 provided on an insulating film 12; (b) selectively removing the semiconductor layer, the gate insulating film, the first conductive layer and the first insulating film to form a device isolation trench; (c) forming a second insulating film 17 in the device isolation [element separation] trench, wherein a height of an upper surface of the second insulating film is substantially coincident with that of an upper surface of the first insulating film; (d) removing a part of the second insulating film and the first insulating film such that a height of an upper surface of the exposed first conductive layer is substantially coincident with that of the top surface of the second insulating film; and (e) patterning the first conductive layer to form a gate electrode.
    • 本发明的半导体器件的制造方法包括:(a)在设置在绝缘膜12上的半导体层13上依次形成栅极绝缘膜14,第一导电层15和第一绝缘膜16; (b)选择性地去除半导体层,栅极绝缘膜,第一导电层和第一绝缘膜,以形成器件隔离沟槽; (c)在器件隔离[元件分离]沟槽中形成第二绝缘膜17,其中第二绝缘膜的上表面的高度与第一绝缘膜的上表面的高度基本一致; (d)去除第二绝缘膜和第一绝缘膜的一部分,使得暴露的第一导电层的上表面的高度与第二绝缘膜的顶表面的高度基本一致; 和(e)图案化第一导电层以形成栅电极。
    • 9. 发明授权
    • Semiconductor device and method of fabricating the same
    • 半导体装置及其制造方法
    • US06975001B2
    • 2005-12-13
    • US10163984
    • 2002-06-06
    • Risho KohYukishige SaitoJong-Wook LeeHisashi Takemura
    • Risho KohYukishige SaitoJong-Wook LeeHisashi Takemura
    • H01L21/28H01L21/8238H01L21/84H01L27/08H01L27/092H01L27/12H01L29/786H01L27/01
    • H01L27/1203H01L21/84
    • A semiconductor device includes (a) a semiconductor layer formed on an electrically insulating layer, (b) a gate insulating film formed on the semiconductor layer, (c) a gate electrode formed on the gate insulating film, and (d) a field insulating film formed on the semiconductor layer for defining a region in which a semiconductor device is to be fabricated. The semiconductor layer includes (a1) source and drain regions formed in the semiconductor layer around the gate electrode, the source and drain regions containing first electrically conductive type impurity, (a2) a body contact region formed in the semiconductor layer, the body contact region containing second electrically conductive type impurity, and (a3) a carrier path region formed in the semiconductor layer such that the carrier path region does not make contact with the source and drain regions, but makes contact with the body contact region, the carrier path region containing second electrically conductive type impurity.
    • 半导体器件包括(a)形成在电绝缘层上的半导体层,(b)形成在半导体层上的栅极绝缘膜,(c)形成在栅极绝缘膜上的栅电极,以及(d)场绝缘 在半导体层上形成用于限定要制造半导体器件的区域的膜。 半导体层包括(a1)形成在栅极周围的半导体层中的源极和漏极区,源极和漏极区包含第一导电型杂质,(a2)形成在半导体层中的体接触区域, 包含第二导电型杂质,以及(a3)形成在半导体层中的载流子路径区域,使得载流子路径区域不与源区域和漏极区域接触,但与体接触区域接触,载体路径区域 含有第二导电型杂质。