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1. 发明申请

US20050250317A1 Semiconductor device and method of fabricating the same 有权
公开(公告)号：US20050250317A1
公开(公告)日：2005-11-10
申请号：US11182150
申请日：2005-07-15
申请人： Risho Koh , Yukishige Saito , Jong-Wook Lee , Hisashi Takemura
发明人： Risho Koh , Yukishige Saito , Jong-Wook Lee , Hisashi Takemura
IPC分类号： H01L21/28 , H01L21/8238 , H01L21/84 , H01L27/08 , H01L27/092 , H01L27/12 , H01L29/786 , H01L21/44
CPC分类号： H01L27/1203 , H01L21/84
摘要： A semiconductor device includes (a) a semiconductor layer formed on an electrically insulating layer, (b) a gate insulating film formed on the semiconductor layer, (c) a gate electrode formed on the gate insulating film, and (d) a field insulating film formed on the semiconductor layer for defining a region in which a semiconductor device is to be fabricated. The semiconductor layer includes (a1) source and drain regions formed in the semiconductor layer around the gate electrode, the source and drain regions containing first electrically conductive type impurity, (a2) a body contact region formed in the semiconductor layer, the body contact region containing second electrically conductive type impurity, and (a3) a carrier path region formed in the semiconductor layer such that the carrier path region does not make contact with the source and drain regions, but makes contact with the body contact region, the carrier path region containing second electrically conductive type impurity.

2. 发明授权

US07611934B2 Semiconductor device and method of fabricating the same 有权
公开(公告)号：US07611934B2
公开(公告)日：2009-11-03
申请号：US11182150
申请日：2005-07-15
申请人： Risho Koh , Yukishige Saito , Jong-Wook Lee , Hisashi Takemura
发明人： Risho Koh , Yukishige Saito , Jong-Wook Lee , Hisashi Takemura
IPC分类号： H01L27/01 , H01L27/12 , H01L31/0392 , H01L21/336 , H01L21/8234
CPC分类号： H01L27/1203 , H01L21/84
摘要： A semiconductor device includes (a) a semiconductor layer formed on an electrically insulating layer, (b) a gate insulating film formed on the semiconductor layer, (c) a gate electrode formed on the gate insulating film, and (d) a field insulating film formed on the semiconductor layer for defining a region in which a semiconductor device is to be fabricated. The semiconductor layer includes (a1) source and drain regions formed in the semiconductor layer around the gate electrode, the source and drain regions containing first electrically conductive type impurity, (a2) a body contact region formed in the semiconductor layer, the body contact region containing second electrically conductive type impurity, and (a3) a carrier path region formed in the semiconductor layer such that the carrier path region does not make contact with the source and drain regions, but makes contact with the body contact region, the carrier path region containing second electrically conductive type impurity.

3. 发明授权

US06975001B2 Semiconductor device and method of fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US06975001B2
公开(公告)日：2005-12-13
申请号：US10163984
申请日：2002-06-06
申请人： Risho Koh , Yukishige Saito , Jong-Wook Lee , Hisashi Takemura
发明人： Risho Koh , Yukishige Saito , Jong-Wook Lee , Hisashi Takemura
IPC分类号： H01L21/28 , H01L21/8238 , H01L21/84 , H01L27/08 , H01L27/092 , H01L27/12 , H01L29/786 , H01L27/01
CPC分类号： H01L27/1203 , H01L21/84
摘要： A semiconductor device includes (a) a semiconductor layer formed on an electrically insulating layer, (b) a gate insulating film formed on the semiconductor layer, (c) a gate electrode formed on the gate insulating film, and (d) a field insulating film formed on the semiconductor layer for defining a region in which a semiconductor device is to be fabricated. The semiconductor layer includes (a1) source and drain regions formed in the semiconductor layer around the gate electrode, the source and drain regions containing first electrically conductive type impurity, (a2) a body contact region formed in the semiconductor layer, the body contact region containing second electrically conductive type impurity, and (a3) a carrier path region formed in the semiconductor layer such that the carrier path region does not make contact with the source and drain regions, but makes contact with the body contact region, the carrier path region containing second electrically conductive type impurity.
摘要翻译：半导体器件包括（a）形成在电绝缘层上的半导体层，（b）形成在半导体层上的栅极绝缘膜，（c）形成在栅极绝缘膜上的栅电极，以及（d）场绝缘在半导体层上形成用于限定要制造半导体器件的区域的膜。半导体层包括（a1）形成在栅极周围的半导体层中的源极和漏极区，源极和漏极区包含第一导电型杂质，（a2）形成在半导体层中的体接触区域，包含第二导电型杂质，以及（a3）形成在半导体层中的载流子路径区域，使得载流子路径区域不与源区域和漏极区域接触，但与体接触区域接触，载体路径区域含有第二导电型杂质。

4. 发明授权

US08236650B2 Vertical-type non-volatile memory devices and methods of manufacturing the same 有权
标题翻译：垂直型非易失性存储器件及其制造方法
公开(公告)号：US08236650B2
公开(公告)日：2012-08-07
申请号：US12686065
申请日：2010-01-12
申请人： Yong-Hoon Son , Jong-Wook Lee
发明人： Yong-Hoon Son , Jong-Wook Lee
IPC分类号： H01L21/336
CPC分类号： H01L27/11568 , H01L21/8221 , H01L27/0688 , H01L27/11556
摘要： In a semiconductor device, and a method of manufacturing thereof, the device includes a substrate of single-crystal semiconductor material extending in a horizontal direction and a plurality of interlayer dielectric layers on the substrate. A plurality of gate patterns are provided, each gate pattern being between a neighboring lower interlayer dielectric layer and a neighboring upper interlayer dielectric layer. A vertical channel of single-crystal semiconductor material extends in a vertical direction through the plurality of interlayer dielectric layers and the plurality to of gate patterns, a gate insulating layer being between each gate pattern and the vertical channel that insulates the gate pattern from the vertical channel.
摘要翻译：在半导体器件及其制造方法中，该器件包括在水平方向上延伸的单晶半导体材料的衬底和在衬底上的多个层间电介质层。提供多个栅极图案，每个栅极图案位于相邻的下层间介电层和相邻的上层间电介质层之间。单晶半导体材料的垂直沟道在垂直方向上延伸穿过多个层间电介质层和多个栅极图案，栅极绝缘层位于每个栅极图案和垂直沟道之间，其将栅极图案与垂直沟道绝缘渠道。

5. 发明申请

US20120070517A1 PHARMACEUTICAL COMPOSITION CONTAINING HERBAL EXTRACT FOR PREVENTION OR TREATMENT OF NEPHRITIS 有权
标题翻译：含有草药提取物的药物组合物用于预防或治疗非传染性疾病
公开(公告)号：US20120070517A1
公开(公告)日：2012-03-22
申请号：US13375255
申请日：2010-06-01
申请人： Jin Auh , Chang-Hwan Kim , Chang-Kyun Han , Sung-Hum Yeon , Seung-In Choe , Young-June Shin , Dong-Oh Han , Soo-Im Chang , Ji-Hye Lee , Jun-Seok Lee , Ho-Young Kwak , Hyo-Jin Moon , Jong-Wook Lee , Sung-Min Kim
发明人： Jin Auh , Chang-Hwan Kim , Chang-Kyun Han , Sung-Hum Yeon , Seung-In Choe , Young-June Shin , Dong-Oh Han , Soo-Im Chang , Ji-Hye Lee , Jun-Seok Lee , Ho-Young Kwak , Hyo-Jin Moon , Jong-Wook Lee , Sung-Min Kim
IPC分类号： A61K36/734 , A61P29/00 , A61P13/12
CPC分类号： A61K36/734 , A61K36/11 , A61K36/536 , A61K36/54 , A61K36/73 , A61K2300/00
摘要： The present invention relates to a novel use of herbal extracts in a pharmaceutical composition for prevention and treatment of nephritis and, more particularly, to a pharmaceutical composition and a health functional food for prevention and/or treatment of nephritis that contains at least one herbal extract selected from the group consisting of a Crataegi Fructus extract, a Cinnamomi Cortex extract, a Prunella Spica extract, and an Equiseti Herba extract, a method for prevention and/or treatment of nephritis using the herbal extract, and a use of the herbal extract in preparation of a composition for prevention and/or treatment of nephritis. The herbal extract has a good therapeutic effect for nephritis on a nephritis model of which the nephritis is induced by a drug such as gentamicin, cisplatin, etc., and a good inhibitory activity on the growth of mesangial cells in kidneys, thereby providing a very useful means for prevention and/or treatment of nephritis.
摘要翻译：本发明涉及草药提取物在用于预防和治疗肾炎的药物组合物中的新用途，更具体地，涉及含有至少一种草药提取物的用于预防和/或治疗肾炎的药物组合物和健康功能食品选自Crataegi Fructus提取物，Cinnamomi Cortex提取物，Prunella Spica提取物和Equiseti Herba提取物，使用草药提取物预防和/或治疗肾炎的方法，以及使用草药提取物制备用于预防和/或治疗肾炎的组合物。草药提取物对肾炎的治疗效果良好，肾炎是由庆大霉素，顺铂等药物引起的肾炎引起的，对肾脏肾小球膜细胞生长具有良好的抑制活性，预防和/或治疗肾炎的有用手段。

6. 发明授权

US08048784B2 Methods of manufacturing semiconductor devices including a doped silicon layer 有权
标题翻译：制造包括掺杂硅层的半导体器件的方法
公开(公告)号：US08048784B2
公开(公告)日：2011-11-01
申请号：US12284565
申请日：2008-09-23
申请人： Pil-Kyu Kang , Yong-Hoon Son , Jong-Wook Lee
发明人： Pil-Kyu Kang , Yong-Hoon Son , Jong-Wook Lee
IPC分类号： H01L21/36
CPC分类号： H01L21/02532 , H01L21/02636 , H01L21/02675
摘要： Methods for manufacturing a semiconductor device include forming a seed layer containing a silicon material on a substrate. An amorphous silicon layer containing amorphous silicon material is formed on the seed layer. The amorphous silicon layer is doped with an impurity. A laser beam is irradiated onto the amorphous silicon layer to produce a phase change of the amorphous silicon layer and change the amorphous silicon layer into a single-crystal silicon layer based on the seed layer.
摘要翻译：制造半导体器件的方法包括在衬底上形成含有硅材料的晶种层。在种子层上形成含有非晶硅材料的非晶硅层。非晶硅层掺杂有杂质。将激光束照射到非晶硅层上以产生非晶硅层的相变，并且基于种子层将非晶硅层改变为单晶硅层。

7. 发明申请

US20100112769A1 VERTICAL-TYPE NON-VOLATILE MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME 有权
标题翻译：垂直型非挥发性记忆体装置及其制造方法
公开(公告)号：US20100112769A1
公开(公告)日：2010-05-06
申请号：US12686065
申请日：2010-01-12
申请人： Yong-Hoon Son , Jong-Wook Lee
发明人： Yong-Hoon Son , Jong-Wook Lee
IPC分类号： H01L21/8234
CPC分类号： H01L27/11568 , H01L21/8221 , H01L27/0688 , H01L27/11556
摘要： In a semiconductor device, and a method of manufacturing thereof, the device includes a substrate of single-crystal semiconductor material extending in a horizontal direction and a plurality of interlayer dielectric layers on the substrate. A plurality of gate patterns are provided, each gate pattern being between a neighboring lower interlayer dielectric layer and a neighboring upper interlayer dielectric layer. A vertical channel of single-crystal semiconductor material extends in a vertical direction through the plurality of interlayer dielectric layers and the plurality to of gate patterns, a gate insulating layer being between each gate pattern and the vertical channel that insulates the gate pattern from the vertical channel.
摘要翻译：在半导体器件及其制造方法中，该器件包括在水平方向上延伸的单晶半导体材料的衬底和在衬底上的多个层间电介质层。提供多个栅极图案，每个栅极图案位于相邻的下层间介电层和相邻的上层间电介质层之间。单晶半导体材料的垂直沟道在垂直方向上延伸穿过多个层间电介质层和多个栅极图案，栅极绝缘层位于每个栅极图案和垂直沟道之间，其将栅极图案与垂直沟道绝缘渠道。

8. 发明申请

US20100109079A1 Vertical type semiconductor device 有权
标题翻译：垂直型半导体器件
公开(公告)号：US20100109079A1
公开(公告)日：2010-05-06
申请号：US12588948
申请日：2009-11-03
申请人： Yong-Hoon Son , Jong-Wook Lee , Jong-Hyuk Kang
发明人： Yong-Hoon Son , Jong-Wook Lee , Jong-Hyuk Kang
IPC分类号： H01L29/78
CPC分类号： H01L29/7827 , H01L29/66666
摘要： A vertical pillar semiconductor device may include a substrate, a group of channel patterns, a gate insulation layer pattern and a gate electrode. The substrate may be divided into an active region and an isolation layer. A first impurity region may be formed in the substrate corresponding to the active region. The group of channel patterns may protrude from a surface of the active region and may be arranged parallel to each other. A second impurity region may be formed on an upper portion of the group of channel patterns. The gate insulation layer pattern may be formed on the substrate and a sidewall of the group of channel patterns. The gate insulation layer pattern may be spaced apart from an upper face of the group of channel patterns. The gate electrode may contact the gate insulation layer and may enclose a sidewall of the group of channel patterns.
摘要翻译：垂直柱半导体器件可以包括衬底，沟道图案组，栅极绝缘层图案和栅电极。衬底可分为有源区和隔离层。可以在对应于有源区的衬底中形成第一杂质区。通道图案组可以从有源区域的表面突出并且可以彼此平行地布置。第二杂质区可以形成在沟道图案组的上部。栅极绝缘层图案可以形成在衬底和沟道图案组的侧壁上。栅极绝缘层图案可以与沟道图案组的上表面间隔开。栅电极可以接触栅极绝缘层并且可以包围沟道图案组的侧壁。

9. 发明申请

US20100078698A1 Vertical semiconductor device, dram device including the same 审中-公开
标题翻译：垂直半导体器件，包括相同的电容器件
公开(公告)号：US20100078698A1
公开(公告)日：2010-04-01
申请号：US12585776
申请日：2009-09-24
申请人： Yong-Hoon Son , Jong-Wook Lee , Jong-Hyuk Kang
发明人： Yong-Hoon Son , Jong-Wook Lee , Jong-Hyuk Kang
IPC分类号： H01L27/06 , H01L29/78
CPC分类号： H01L27/10852 , B82Y10/00 , H01L21/823487 , H01L27/10876 , H01L29/0673 , H01L29/0676 , H01L29/66439 , H01L29/66666 , H01L29/775 , H01L29/7827
摘要： A vertical semiconductor device, a DRAM device, and associated methods, the vertical semiconductor device including single crystalline active bodies vertically disposed on an upper surface of a single crystalline substrate, each of the single crystalline active bodies having a first active portion on the substrate and a second active portion on the first active portion, and the first active portion having a first width smaller than a second width of the second active portion, a gate insulating layer on a sidewall of the first active portion and the upper surface of the substrate, a gate electrode on the gate insulating layer, the gate electrode having a linear shape surrounding the active bodies, a first impurity region in the upper surface of the substrate under the active bodies, and a second impurity region in the second active portion.
摘要翻译：垂直半导体器件，DRAM器件和相关方法，垂直半导体器件包括垂直设置在单晶衬底的上表面上的单晶有源体，每个单晶有源体在衬底上具有第一有源部分，所述第一有源部分的第二有源部分和所述第一有源部分具有小于所述第二有源部分的第二宽度的第一宽度，所述第一有源部分的侧壁和所述衬底的上表面上的栅极绝缘层，所述栅电极在所述栅极绝缘层上，所述栅电极具有围绕所述有源体的直线形状，所述基板的所述有源体下方的上表面中的第一杂质区域和所述第二有源部分中的第二杂质区域。

10. 发明申请

US20090242966A1 Vertical-type semiconductor devices 有权
标题翻译：垂直型半导体器件
公开(公告)号：US20090242966A1
公开(公告)日：2009-10-01
申请号：US12380565
申请日：2009-02-27
申请人： Yong-Hoon Son , Jong-Wook Lee , Jong-Hyuk Kang
发明人： Yong-Hoon Son , Jong-Wook Lee , Jong-Hyuk Kang
IPC分类号： H01L29/792
CPC分类号： H01L27/11582 , H01L21/02524 , H01L21/02587 , H01L21/02598 , H01L21/02675 , H01L21/28282 , H01L21/28518 , H01L21/30604 , H01L21/32133 , H01L27/1052 , H01L27/11568 , H01L27/11578 , H01L27/1158 , H01L29/4234 , H01L29/45 , H01L29/665 , H01L29/66666 , H01L29/66787 , H01L29/66833 , H01L29/792 , H01L29/7926
摘要： In a vertical-type memory device and a method of manufacturing the vertical-type memory device, the vertical memory device includes an insulation layer pattern of a linear shape provided on a substrate, pillar-shaped single-crystalline semiconductor patterns provided on both sidewalls of the insulation layer pattern and transistors provided on a sidewall of each of the single-crystalline semiconductor patterns. The transistors are arranged in a vertical direction of the single-crystalline semiconductor pattern, and thus the memory device may be highly integrated.
摘要翻译：在垂直型存储器件和垂直型存储器件的制造方法中，垂直存储器件包括设置在衬底上的线状绝缘层图形，柱状单晶半导体图案设置在两侧壁上设置在每个单晶半导体图案的侧壁上的绝缘层图案和晶体管。晶体管沿着单晶半导体图案的垂直方向排列，因此存储器件可以高度集成。

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