专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07719043B2 Semiconductor device with fin-type field effect transistor and manufacturing method thereof. 失效
标题翻译：具有鳍式场效应晶体管的半导体器件及其制造方法。
公开(公告)号：US07719043B2
公开(公告)日：2010-05-18
申请号：US11632352
申请日：2005-07-04
申请人： Shigeharu Yamagami , Hitoshi Wakabayashi , Risho Koh , Kiyoshi Takeuchi , Masahiro Nomura , Koichi Takeda , Koichi Terashima , Masayasu Tanaka , Katsuhiko Tanaka
发明人： Shigeharu Yamagami , Hitoshi Wakabayashi , Risho Koh , Kiyoshi Takeuchi , Masahiro Nomura , Koichi Takeda , Koichi Terashima , Masayasu Tanaka , Katsuhiko Tanaka
IPC分类号： H01L27/108 , H01L29/94
CPC分类号： H01L21/84 , H01L21/823807 , H01L21/823821 , H01L21/823828 , H01L21/823878 , H01L27/1203 , H01L29/7851
摘要： The present invention relates to a semiconductor device including a Fin type field effect transistor (FET) having a protrusive semiconductor layer protruding from a substrate plane, a gate electrode formed so as to straddle the protrusive semiconductor layer, a gate insulating film between the gate electrode and the protrusive semiconductor layer, and source and drain regions provided in the protrusive semiconductor layer, wherein the semiconductor device has on a semiconductor substrate an element forming region having a Fin type FET, a trench provided on the semiconductor substrate for separating the element forming region from another element forming region, and an element isolation insulating film in the trench; the element forming region has a shallow substrate flat surface formed by digging to a depth shallower than the bottom surface of the trench and deeper than the upper surface of the semiconductor substrate, a semiconductor raised portion protruding from the substrate flat surface and formed of a part of the semiconductor substrate, and an insulating film on the shallow substrate flat surface; and the protrusive semiconductor layer of the Fin type FET is formed of a portion protruding from the insulating film of the semiconductor raised portion.
摘要翻译：本发明涉及一种半导体器件，其包括具有从衬底平面突出的突出半导体层的鳍型场效应晶体管（FET），形成为跨越突出半导体层的栅极电极，栅极电极所述突出半导体层以及设置在所述突出半导体层中的源极和漏极区域，其中所述半导体器件在半导体衬底上具有具有鳍型FET的元件形成区域，设置在所述半导体衬底上的沟槽，用于将所述元件形成区域来自另一个元件形成区域，以及沟槽中的元件隔离绝缘膜; 元件形成区域具有通过挖掘到比沟槽的底表面浅的深度而比半导体衬底的上表面更深的深浅的衬底平坦表面，从衬底平坦表面突出并形成的半导体凸起部分的半导体衬底，以及在浅衬底平面上的绝缘膜; 并且鳍式FET的突出半导体层由从半导体凸起部分的绝缘膜突出的部分形成。

2. 发明申请

US20070158700A1 Field effect transistor and method for producing the same 审中-公开
标题翻译：场效应晶体管及其制造方法
公开(公告)号：US20070158700A1
公开(公告)日：2007-07-12
申请号：US10587845
申请日：2005-01-28
申请人： Risho Koh , Katsuhiko Tanaka , Kiyoshi Takeuchi
发明人： Risho Koh , Katsuhiko Tanaka , Kiyoshi Takeuchi
IPC分类号： H01L29/76
CPC分类号： H01L29/785 , H01L29/66795 , H01L29/66803 , H01L29/7854 , H01L29/78609
摘要： A field effect transistor comprising: a semiconductor layer projecting from the plane of a base; a gate electrode provided on opposite side surfaces of the semiconductor layer; a gate insulating film interposed between the gate electrode and the side surface of the semiconductor layer; and source/drain regions where a first conductivity type impurity is introduced, wherein the semiconductor layer has a channel forming region in a portion sandwiched between the source/drain regions, and has in the upper part of the semiconductor layer in the channel forming region a channel impurity concentration adjusting region of which the concentration of a second conductivity type impurity is higher than that in the lower part of the semiconductor layer, and in the channel impurity concentration adjusting region, a channel is formed in a side surface portion facing the gate insulating film of the semiconductor layer in the channel impurity concentration adjusting region in a state of operation in which a signal voltage is applied to the gate electrode.
摘要翻译：一种场效应晶体管，包括：从基底的平面突出的半导体层; 设置在所述半导体层的相对侧表面上的栅电极; 介于栅电极和半导体层的侧表面之间的栅极绝缘膜; 以及引入第一导电型杂质的源极/漏极区域，其中半导体层在夹在源极/漏极区域之间的部分中具有沟道形成区域，并且在沟道形成区域a中的半导体层的上部沟道杂质浓度调整区域，其中第二导电类型杂质的浓度高于半导体层的下部，并且在沟道杂质浓度调节区域中，在面向栅极绝缘体的侧表面部分中形成沟道在对栅电极施加信号电压的工作状态下的沟道杂质浓度调整区域中的半导体层的膜。

3. 发明授权

US07211517B2 Semiconductor device and method that includes reverse tapering multiple layers 有权
标题翻译：半导体器件和方法，包括反向逐渐变细多层
公开(公告)号：US07211517B2
公开(公告)日：2007-05-01
申请号：US10476978
申请日：2002-09-05
申请人： Yukishige Saito , Risho Koh , Jyonu Ri , Hisashi Takemura
发明人： Yukishige Saito , Risho Koh , Jyonu Ri , Hisashi Takemura
IPC分类号： H01L21/311
CPC分类号： H01L29/66757 , H01L21/76264 , H01L21/76283 , H01L29/66742 , H01L29/66772 , H01L29/78609 , H01L29/78618 , H01L29/78636 , Y10S438/978
摘要： A method of manufacturing a semiconductor device of the present invention includes (a) sequentially forming a gate insulating film 14, a first conductive layer 15 and a first insulating film 16 on a semiconductor layer 13 provided on an insulating film 12; (b) selectively removing the semiconductor layer, the gate insulating film, the first conductive layer and the first insulating film to form a device isolation trench; (c) forming a second insulating film 17 in the device isolation [element separation] trench, wherein a height of an upper surface of the second insulating film is substantially coincident with that of an upper surface of the first insulating film; (d) removing a part of the second insulating film and the first insulating film such that a height of an upper surface of the exposed first conductive layer is substantially coincident with that of the top surface of the second insulating film; and (e) patterning the first conductive layer to form a gate electrode.
摘要翻译：本发明的半导体器件的制造方法包括：（a）在设置在绝缘膜12上的半导体层13上依次形成栅极绝缘膜14，第一导电层15和第一绝缘膜16; （b）选择性地去除半导体层，栅极绝缘膜，第一导电层和第一绝缘膜，以形成器件隔离沟槽; （c）在器件隔离[元件分离]沟槽中形成第二绝缘膜17，其中第二绝缘膜的上表面的高度与第一绝缘膜的上表面的高度基本一致; （d）去除第二绝缘膜和第一绝缘膜的一部分，使得暴露的第一导电层的上表面的高度与第二绝缘膜的顶表面的高度基本一致; 和（e）图案化第一导电层以形成栅电极。

4. 发明授权

US07485923B2 SOI semiconductor device with improved halo region and manufacturing method of the same 有权
标题翻译：具有改善的卤素区域的SOI半导体器件及其制造方法
公开(公告)号：US07485923B2
公开(公告)日：2009-02-03
申请号：US10490599
申请日：2002-10-02
申请人： Hisashi Takemura , Risho Koh , Yukishige Saito , Jyonu Ri
发明人： Hisashi Takemura , Risho Koh , Yukishige Saito , Jyonu Ri
IPC分类号： H01L29/772
CPC分类号： H01L29/78696 , H01L21/26586 , H01L29/66772 , H01L29/78612 , H01L29/78621 , H01L2029/7863
摘要： A semiconductor device includes a first insulating layer, a semiconductor layer formed on the first insulating layer, a second insulating layer on a part of the semiconductor layer, and a gate electrode formed on the semiconductor layer through the second insulating layer. The semiconductor layer includes a low concentration region formed under the gate electrode through the second insulating layer, two high concentration regions which are formed in at least upper regions on outer sides of the low concentration region under the gate electrode through the second insulating layer, and have an impurity concentration higher than an impurity concentration of the low concentration region, respectively, and two source/drain regions which are formed in side portions of the high concentration regions to have low concentration region side end portions, respectively. A width of the high concentration region is equal to or less than 30 nm.
摘要翻译：半导体器件包括第一绝缘层，形成在第一绝缘层上的半导体层，半导体层的一部分上的第二绝缘层和通过第二绝缘层形成在半导体层上的栅电极。半导体层包括通过第二绝缘层形成在栅电极下方的低浓度区域，通过第二绝缘层形成在栅电极下方的低浓度区域的至少上侧区域中的至少上部区域的两个高浓度区域，以及分别具有高于低浓度区域的杂质浓度的杂质浓度，以及分别形成在高浓度区域的侧部的两个源极/漏极区域，以分别具有低浓度区域侧端部。高浓度区域的宽度等于或小于30nm。

5. 发明申请

US20050250317A1 Semiconductor device and method of fabricating the same 有权
公开(公告)号：US20050250317A1
公开(公告)日：2005-11-10
申请号：US11182150
申请日：2005-07-15
申请人： Risho Koh , Yukishige Saito , Jong-Wook Lee , Hisashi Takemura
发明人： Risho Koh , Yukishige Saito , Jong-Wook Lee , Hisashi Takemura
IPC分类号： H01L21/28 , H01L21/8238 , H01L21/84 , H01L27/08 , H01L27/092 , H01L27/12 , H01L29/786 , H01L21/44
CPC分类号： H01L27/1203 , H01L21/84
摘要： A semiconductor device includes (a) a semiconductor layer formed on an electrically insulating layer, (b) a gate insulating film formed on the semiconductor layer, (c) a gate electrode formed on the gate insulating film, and (d) a field insulating film formed on the semiconductor layer for defining a region in which a semiconductor device is to be fabricated. The semiconductor layer includes (a1) source and drain regions formed in the semiconductor layer around the gate electrode, the source and drain regions containing first electrically conductive type impurity, (a2) a body contact region formed in the semiconductor layer, the body contact region containing second electrically conductive type impurity, and (a3) a carrier path region formed in the semiconductor layer such that the carrier path region does not make contact with the source and drain regions, but makes contact with the body contact region, the carrier path region containing second electrically conductive type impurity.

6. 发明授权

US06306691B1 Body driven SOI-MOS field effect transistor and method of forming the same 有权
标题翻译：体驱动SOI-MOS场效应晶体管及其形成方法
公开(公告)号：US06306691B1
公开(公告)日：2001-10-23
申请号：US09470505
申请日：1999-12-22
申请人： Risho Koh
发明人： Risho Koh
IPC分类号： H01L2100
CPC分类号： H01L29/66772 , H01L29/785 , H01L29/78648
摘要： In a body driven SOIMOSFET, a semiconductor layer extends over the insulator and comprises a first conductivity type high impurity concentration diffusion layer, a low impurity concentration region and another first conductivity type high impurity concentration diffusion layer which are in this order connected with each other. A second conductivity type high impurity concentration semiconductor layer is formed in contact with a top of the low impurity concentration region. A bottom electrode is formed within the insulation layer so that the bottom electrode is surrounded by the insulation layer. The bottom electrode is positioned under the low impurity concentration region and being separated by the insulation layer from the low impurity concentration region. It is important that the bottom electrode does not extend under the first conductivity high impurity concentration regions.
摘要翻译：在体驱动的SOIMOSFET中，半导体层在绝缘体上方延伸，并且包括第一导电型高杂质浓度扩散层，低杂质浓度区和另一第一导电型高杂质浓度扩散层。形成与低杂质浓度区域的顶部接触的第二导电型高杂质浓度半导体层。底部电极形成在绝缘层内，使得底部电极被绝缘层包围。底部电极位于低杂质浓度区域的下方，并由绝缘层与低杂质浓度区域分开。重要的是，底部电极不会在第一导电性高杂质浓度区域之下延伸。

7. 发明授权

US5668046A Method of producing a semiconductor on insulating substrate, and a method of forming transistor thereon 失效
标题翻译：在绝缘基板上制造半导体的方法及其上形成晶体管的方法
公开(公告)号：US5668046A
公开(公告)日：1997-09-16
申请号：US413613
申请日：1995-03-30
申请人： Risho Koh , Atsushi Ogura
发明人： Risho Koh , Atsushi Ogura
IPC分类号： H01L21/02 , H01L21/20 , H01L21/336 , H01L27/12 , H01L29/78 , H01L29/786
CPC分类号： H01L29/66772 , H01L21/02381 , H01L21/02488 , H01L21/02532 , H01L21/02546 , H01L21/0262 , H01L21/02639 , H01L29/78621 , H01L29/78654 , H01L29/78678 , Y10S148/026 , Y10S148/053 , Y10S148/164
摘要： In a field intensity relaxation of the drain end of a MOSFET, a projective area is not increased with a reduced electrostatic coupling of the source or drain with the gate. The MOSFET satisfying such condition is fabricated on the SOIS film formed by processes of the lateral vapor phase epitaxial growth and the like. A U-shape low concentration impurity region is provided on a gate electrode through a gate dioxide film and high concentration impurity regions are formed at the tops of protrusions. The gate electrode is embedded in insulation films, and the transistor region is fabricated by the lateral vapor phase epitaxial growth and the like.
摘要翻译：在MOSFET的漏极端的场强弛豫中，投影区域不会随着源极或漏极与栅极的静电耦合减小而增加。满足这种条件的MOSFET在由侧向气相外延生长等的工艺形成的SOIS膜上制造。通过栅极二氧化物膜在栅电极上设置U形低浓度杂质区，在突起的顶部形成高浓度杂质区。栅电极嵌入在绝缘膜中，晶体管区域由横向气相外延生长等制成。

8. 发明申请

US20080029821A1 Semiconductor Device and Method for Production Thereof 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US20080029821A1
公开(公告)日：2008-02-07
申请号：US11632352
申请日：2005-07-04
申请人： Shigeharu Yamagami , Hitoshi Wakabayashi , Risho Koh , Kiyoshi Takeuchi , Masahiro Nomura , Koichi Takeda , Koichi Terashima , Masayasu Tanaka , Katsuhiko Tanaka
发明人： Shigeharu Yamagami , Hitoshi Wakabayashi , Risho Koh , Kiyoshi Takeuchi , Masahiro Nomura , Koichi Takeda , Koichi Terashima , Masayasu Tanaka , Katsuhiko Tanaka
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/84 , H01L21/823807 , H01L21/823821 , H01L21/823828 , H01L21/823878 , H01L27/1203 , H01L29/7851
摘要： The present invention relates to a semiconductor device including a Fin type field effect transistor (FET) having a protrusive semiconductor layer protruding from a substrate plane, a gate electrode formed so as to straddle the protrusive semiconductor layer, a gate insulating film between the gate electrode and the protrusive semiconductor layer, and source and drain regions provided in the protrusive semiconductor layer, wherein the semiconductor device has on a semiconductor substrate an element forming region having a Fin type FET, a trench provided on the semiconductor substrate for separating the element forming region from another element forming region, and an element isolation insulating film in the trench; the element forming region has a shallow substrate flat surface formed by digging to a depth shallower than the bottom surface of the trench and deeper than the upper surface of the semiconductor substrate, a semiconductor raised portion protruding from the substrate flat surface and formed of a part of the semiconductor substrate, and an insulating film on the shallow substrate flat surface; and the protrusive semiconductor layer of the Fin type FET is formed of a portion protruding from the insulating film of the semiconductor raised portion.
摘要翻译：本发明涉及一种半导体器件，其包括具有从衬底平面突出的突出半导体层的鳍型场效应晶体管（FET），形成为跨越突出半导体层的栅极电极，栅极电极所述突出半导体层以及设置在所述突出半导体层中的源极和漏极区域，其中所述半导体器件在半导体衬底上具有具有鳍型FET的元件形成区域，设置在所述半导体衬底上的沟槽，用于将所述元件形成区域来自另一个元件形成区域，以及沟槽中的元件隔离绝缘膜; 元件形成区域具有通过挖掘到比沟槽的底表面浅的深度而比半导体衬底的上表面更深的深浅的衬底平坦表面，从衬底平坦表面突出并形成的半导体凸起部分的半导体衬底，以及在浅衬底平面上的绝缘膜; 并且鳍式FET的突出半导体层由从半导体凸起部分的绝缘膜突出的部分形成。

9. 发明申请

US20070257277A1 Semiconductor Device and Method for Manufacturing the Same 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20070257277A1
公开(公告)日：2007-11-08
申请号：US11570025
申请日：2005-05-07
申请人： Koichi Takeda , Hitoshi Wakabayashi , Kiyoshi Takeuchi , Shigeharu Yamagami , Masahiro Nomura , Masayasu Tanaka , Koichi Terashima , Risho Koh , Katsuhiko Tanaka
发明人： Koichi Takeda , Hitoshi Wakabayashi , Kiyoshi Takeuchi , Shigeharu Yamagami , Masahiro Nomura , Masayasu Tanaka , Koichi Terashima , Risho Koh , Katsuhiko Tanaka
IPC分类号： H01L21/8244 , H01L21/82
CPC分类号： H01L27/11 , H01L21/84 , H01L21/86 , H01L27/1104 , H01L27/1108 , H01L27/1203 , H01L29/785
摘要： A semiconductor device having SRAM cell units each comprising a pair of driving transistors, a pair of load transistors and a pair of access transistors, in which each of the transistors has a semiconductor layer projecting upward from a substrate plane, a gate electrode extending on opposite sides of the semiconductor layer so as to stride over a top of the semiconductor layer, a gate insulting film interposed between the gate electrode and the semiconductor layer, and a pair of source/drain areas formed in the semiconductor layer; a longitudinal direction of each semiconductor layer extends along a first direction; and between the adjacent SRAM cell units in the first direction, the semiconductor layer in one of the corresponding transistors is located on a center line of the semiconductor layer in the other transistor which center line extends along the first direction.
摘要翻译：一种具有SRAM单元单元的半导体器件，每个单元包括一对驱动晶体管，一对负载晶体管和一对存取晶体管，其中每个晶体管具有从衬底平面向上突出的半导体层，相对延伸的栅电极半导体层的侧面，跨越半导体层的顶部，插入在栅极电极和半导体层之间的栅极绝缘膜，以及形成在半导体层中的一对源极/漏极区域; 每个半导体层的纵向方向沿第一方向延伸; 并且在第一方向上的相邻SRAM单元单元之间，一个对应的晶体管中的半导体层位于另一个晶体管的半导体层的中心线上，该中心线沿第一方向延伸。

10. 发明授权

US06933569B2 SOI MOSFET 失效
公开(公告)号：US06933569B2
公开(公告)日：2005-08-23
申请号：US10668349
申请日：2003-09-24
申请人： Risho Koh , Shigeharu Yamagami , Jong-wook Lee , Hitoshi Wakabayashi , Yukishige Saito , Atsushi Ogura , Mitsuru Narihiro , Kohichi Arai , Hisashi Takemura , Tohru Mogami , Toyoji Yamamoto , Yukinori Ochiai
发明人： Risho Koh , Shigeharu Yamagami , Jong-wook Lee , Hitoshi Wakabayashi , Yukishige Saito , Atsushi Ogura , Mitsuru Narihiro , Kohichi Arai , Hisashi Takemura , Tohru Mogami , Toyoji Yamamoto , Yukinori Ochiai
IPC分类号： H01L21/76 , H01L21/336 , H01L21/8238 , H01L21/84 , H01L27/01 , H01L27/08 , H01L27/092 , H01L27/12 , H01L29/786 , H01L21/01
CPC分类号： H01L29/66772 , H01L21/84 , H01L27/1203 , H01L29/78609 , H01L29/78615 , H01L29/78621
摘要： A semiconductor device includes a semiconductor layer formed on an insulator, a gate insulating film formed on the semiconductor layer, a gate electrode formed on the gate insulating film and extending in a first direction, source/drain regions formed in the semiconductor layer on both sides of the gate electrode, a body contact region in the semiconductor layer, a partial isolating region in which a field insulating film thicker than the gate insulating film intervenes between the semiconductor layer and an extending portion of the gate electrode, and a full isolating region in which the semiconductor layer on the insulator is removed. The full isolating region is formed to be in contact with at least a part of a side parallel to the first direction of the source/drain regions.
摘要翻译：半导体器件包括形成在绝缘体上的半导体层，形成在半导体层上的栅极绝缘膜，形成在栅极绝缘膜上并沿第一方向延伸的栅电极，在两侧的半导体层中形成的源/漏区所述半导体层中的主体接触区域，其中比所述栅极绝缘膜更厚的场绝缘膜介于所述半导体层和所述栅电极的延伸部分之间的部分隔离区域，以及完全隔离区域去除绝缘体上的半导体层。完全隔离区域形成为与平行于源极/漏极区域的第一方向的一侧的至少一部分接触。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式