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    • 9. 发明授权
    • Method for minimizing clock skew in integrated circuits and printed
circuits
    • 集成电路和印刷电路中时钟偏移最小化的方法
    • US5691662A
    • 1997-11-25
    • US632166
    • 1996-04-15
    • Alfred J. SoboleskiYukio Sakaguchi
    • Alfred J. SoboleskiYukio Sakaguchi
    • G06F1/10G06F17/50H03K19/096H03K19/177
    • G06F1/10G06F17/5077
    • Clock skew is minimized in an ASIC by grid-partitioning the IC chip into a number of preferably equal sized regions. An on-chip clock or buffer unit provides a clock signal to be distributed to buffers and clocked loads also on the IC. Equal length metal interconnect traces are formed in a preferably "H"-shaped configuration such that the termini and the center of the traces overlie buffer regions that will receive the distributed clock signal. Metallization interconnect paths are dictated by placement of joiner cells. By making each metal interconnect trace equal in overall length and in layer sub-lengths (if multiple metallization layers are present), clock skew along the interconnect traces is minimized macroscopically. A series of prioritized net lists is generated, defining interconnect paths to each region. A buffer is centrally located within each region, and is surrounded by a ring containing clocked loads to be coupled to the clock signal. The ring-shape causes the clocked loads to be substantially electrically equidistant from the associated region buffer, which minimizes skew microscopically. An updated series of netlists and a clocked load preplacement batch command file are generated, defining the clocked load connections. Placement and routing of the buffers, the clocked loads and then the remainder of the ASIC is accomplished using a conventional placement and router system. The invention may also be practiced to reduce skew in designing printed circuit boards.
    • 通过将IC芯片网格划分成若干优选相等尺寸的区域,ASIC中的时钟偏移被最小化。 片上时钟或缓冲单元提供时钟信号,分配给IC上的缓冲器和时钟负载。 相等长度的金属互连迹线以优选“H”形配置形成,使得迹线的末端和中心覆盖将接收分布式时钟信号的缓冲区。 金属化互连路径由接合单元的放置决定。 通过使每个金属互连轨迹的总长度和层子长度相等(如果存在多个金属化层),则沿着互连轨迹的时钟偏移在宏观上被最小化。 生成一系列优先的网络列表,定义到每个区域的互连路径。 缓冲器位于每个区域的中心,并被包含时钟负载的环包围以耦合到时钟信号。 环形导致时钟负载与相关联的区域缓冲器基本上电等距离,这使得显微镜下的偏移最小化。 生成更新的一系列网表和时钟负载预置批量命令文件,定义时钟负载连接。 缓冲器的放置和路由,时钟负载,然后ASIC的其余部分使用传统的放置和路由器系统来实现。 还可以实施本发明以减少设计印刷电路板的偏斜。