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1. 发明申请

US20130171799A1 CURRENT STEERING ELEMENT AND NON-VOLATILE MEMORY ELEMENT INCORPORATING CURRENT STEERING ELEMENT 有权
标题翻译：电流转向元件和非易失性存储元件包含电流转向元件
公开(公告)号：US20130171799A1
公开(公告)日：2013-07-04
申请号：US13823667
申请日：2011-09-16
申请人： Ryoko Miyanaga , Takumi Mikawa , Yukio Hayakawa , Takeki Ninomiya , Koji Arita
发明人： Ryoko Miyanaga , Takumi Mikawa , Yukio Hayakawa , Takeki Ninomiya , Koji Arita
IPC分类号： H01L45/00 , H01L21/768
CPC分类号： H01L45/16 , H01L21/768 , H01L27/101 , H01L27/2409 , H01L27/2418 , H01L45/00 , H01L45/04 , H01L45/1233 , H01L45/146
摘要： A current steering element (100) formed such that the current steering element covers a lower opening (105) of a via hole (104) formed in an interlayer insulating layer (102), comprises: a corrosion-suppressing layer (106) formed on a lower side of a lower opening of the via hole such that the corrosion-suppressing layer covers an entire portion of the lower opening; a second electrode layer (108) formed under the corrosion-suppressing layer and comprising a material different from a material of the corrosion-suppressing layer; a current steering layer (110) formed under the second electrode layer such that the current steering layer is physically in contact with the second electrode layer; and a first electrode layer (112) formed under the current steering layer such that the first electrode layer is physically in contact with the current steering layer; and the first electrode layer, the current steering layer and the second electrode layer constitute one of a MSM diode and a MIM diode.
摘要翻译：一种形成为当前的操舵元件覆盖形成在层间绝缘层（102）中的通孔（104）的下开口（105）的电流控制元件（100），包括：形成在通孔的下开口的下侧，使得防蚀层覆盖下开口的整个部分; 形成在所述腐蚀抑制层下方并且包含不同于所述腐蚀抑制层的材料的材料的第二电极层（108）形成在所述第二电极层下方的电流转向层（110），使得所述电流导向层物理地与所述第二电极层接触; 以及第一电极层（112），形成在所述电流导向层下方，使得所述第一电极层物理地与所述电流转向层接触; 并且第一电极层，电流导向层和第二电极层构成MSM二极管和MIM二极管之一。

2. 发明授权

US08759190B2 Current steering element and non-volatile memory element incorporating current steering element 有权
标题翻译：目前的导向元件和非易失性存储元件结合了当前的转向元件
公开(公告)号：US08759190B2
公开(公告)日：2014-06-24
申请号：US13823667
申请日：2011-09-16
申请人： Ryoko Miyanaga , Takumi Mikawa , Yukio Hayakawa , Takeki Ninomiya , Koji Arita
发明人： Ryoko Miyanaga , Takumi Mikawa , Yukio Hayakawa , Takeki Ninomiya , Koji Arita
IPC分类号： H01L21/20
CPC分类号： H01L45/16 , H01L21/768 , H01L27/101 , H01L27/2409 , H01L27/2418 , H01L45/00 , H01L45/04 , H01L45/1233 , H01L45/146
摘要： A current steering element (100) formed such that the current steering element covers a lower opening (105) of a via hole (104) formed in an interlayer insulating layer (102), comprises: a corrosion-suppressing layer (106) formed on a lower side of a lower opening of the via hole such that the corrosion-suppressing layer covers an entire portion of the lower opening; a second electrode layer (108) formed under the corrosion-suppressing layer and comprising a material different from a material of the corrosion-suppressing layer; a current steering layer (110) formed under the second electrode layer such that the current steering layer is physically in contact with the second electrode layer; and a first electrode layer (112) formed under the current steering layer such that the first electrode layer is physically in contact with the current steering layer; and the first electrode layer, the current steering layer and the second electrode layer constitute one of a MSM diode and a MIM diode.
摘要翻译：一种形成为当前的操舵元件覆盖形成在层间绝缘层（102）中的通孔（104）的下开口（105）的电流控制元件（100），包括：形成在通孔的下开口的下侧，使得防蚀层覆盖下开口的整个部分; 形成在所述腐蚀抑制层下方并且包含不同于所述腐蚀抑制层的材料的材料的第二电极层（108）形成在所述第二电极层下方的电流转向层（110），使得所述电流导向层物理地与所述第二电极层接触; 以及第一电极层（112），形成在所述电流导向层下方，使得所述第一电极层物理地与所述电流转向层接触; 并且第一电极层，电流导向层和第二电极层构成MSM二极管和MIM二极管之一。

3. 发明申请

US20120069632A1 CURRENT CONTROL, MEMORY ELEMENT, MEMORY DEVICE, AND PRODUCTION METHOD FOR CURRENT CONTROL ELEMENT 有权
标题翻译：电流控制，存储元件，存储器件和电流控制元件的生产方法
公开(公告)号：US20120069632A1
公开(公告)日：2012-03-22
申请号：US13321018
申请日：2011-03-10
申请人： Yukio Hayakawa , Koji Arita , Takumi Mikawa , Takeki Ninomiya
发明人： Yukio Hayakawa , Koji Arita , Takumi Mikawa , Takeki Ninomiya
IPC分类号： G11C11/00 , H01L21/66 , H01L47/00
CPC分类号： H01L27/2409 , H01L45/146
摘要： Provided is a current steering element that can prevent write didturb even when an electrical pulse with different polarities is applied and that can cause a large current to flow through a variable resistance element. The current steering element includes a first electrode (32), a second electrode (31), and a current steering layer (33). The current steering layer (33) comprises SiNx (where 0
摘要翻译：提供了即使当施加具有不同极性的电脉冲并且可能导致大电流流过可变电阻元件时也能够防止写入干扰的电流导向元件。当前的转向元件包括第一电极（32），第二电极（31）和电流转向层（33）。当前的转向层（33）包括添加有氢或氟的SiNx（其中0

4. 发明授权

US08482958B2 Current steering element, memory element, memory, and method of manufacturing current steering element 有权
标题翻译：当前的导向元件，存储元件，存储器以及制造电流转向元件的方法
公开(公告)号：US08482958B2
公开(公告)日：2013-07-09
申请号：US13321018
申请日：2011-03-10
申请人： Yukio Hayakawa , Koji Arita , Takumi Mikawa , Takeki Ninomiya
发明人： Yukio Hayakawa , Koji Arita , Takumi Mikawa , Takeki Ninomiya
IPC分类号： G11C11/00
CPC分类号： H01L27/2409 , H01L45/146
摘要： Provided is a current steering element that can prevent write didturb even when an electrical pulse with different polarities is applied and that can cause a large current to flow through a variable resistance element. The current steering element includes a first electrode (32), a second electrode (31), and a current steering layer (33). The current steering layer (33) comprises SiNx (where 0
摘要翻译：提供了即使当施加具有不同极性的电脉冲并且可能导致大电流流过可变电阻元件时也能够防止写入干扰的电流导向元件。当前的转向元件包括第一电极（32），第二电极（31）和电流转向层（33）。当前的转向层（33）包括加入氢或氟的SiNx（其中0 <0.85）。当D（D = D0×1022原子/ cm3）表示氢或氟的密度时，d（nm）表示电流导向层（33）的厚度，V0（V）表示适用于第一电极（32）和第二电极（31）D，x，d和V0满足下式。（ln（1000（C·exp（α·d）exp（β·x））-1）γ）2 @ V0 ）γ）2-（ln（10000（C·exp（α·d）exp（β·x））-1）γ）2/2> = 0其中C = k1×D0k2，α，β， k1和k2是常数。

5. 发明授权

US08537605B2 Nonvolatile semiconductor memory device having coplanar surfaces at resistance variable layer and wiring layer and manufacturing method thereof 有权
标题翻译：在电阻变化层和布线层具有共面的非易失性半导体存储器件及其制造方法
公开(公告)号：US08537605B2
公开(公告)日：2013-09-17
申请号：US12867437
申请日：2009-02-09
申请人： Takumi Mikawa , Yoshio Kawashima , Koji Arita , Takeki Ninomiya
发明人： Takumi Mikawa , Yoshio Kawashima , Koji Arita , Takeki Ninomiya
IPC分类号： G11C11/14
CPC分类号： H01L27/101 , H01L27/2436 , H01L45/04 , H01L45/1233 , H01L45/146 , H01L45/1675
摘要： A nonvolatile semiconductor memory device (100) comprises a substrate (102) provided with a transistor (101); a first interlayer insulating layer (103) formed over the substrate to cover the transistor; a first contact plug (104) formed in the first interlayer insulating layer and electrically connected to either of a drain electrode (101a) or a source electrode (101b) of the transistor, and a second contact plug (105) formed in the first interlayer insulating layer and electrically connected to the other of the drain electrode or the source electrode of the transistor; a resistance variable layer (106) formed to cover a portion of the first contact plug; a first wire (107) formed on the resistance variable layer; and a second wire (108) formed to cover a portion of the second contact plug; an end surface of the resistance variable layer being coplanar with an end surface of the first wire.
摘要翻译：非易失性半导体存储器件（100）包括设置有晶体管（101）的衬底（102）; 形成在所述衬底上以覆盖所述晶体管的第一层间绝缘层（103）形成在所述第一层间绝缘层中并电连接到所述晶体管的漏电极（101a）或源电极（101b）中的任一个的第一接触插塞（104）和形成在所述第一中间层绝缘层并与晶体管的漏电极或源电极中的另一个电连接; 形成为覆盖所述第一接触插塞的一部分的电阻变化层（106）形成在电阻变化层上的第一线（107）以及形成为覆盖所述第二接触插塞的一部分的第二线（108）所述电阻变化层的端面与所述第一线的端面共面。

6. 发明授权

US09000506B2 Variable resistance nonvolatile memory element and method for manufacturing the same 有权
标题翻译：可变电阻非易失性存储元件及其制造方法
公开(公告)号：US09000506B2
公开(公告)日：2015-04-07
申请号：US13501624
申请日：2011-11-18
申请人： Takeki Ninomiya , Takumi Mikawa , Yukio Hayakawa
发明人： Takeki Ninomiya , Takumi Mikawa , Yukio Hayakawa
IPC分类号： H01L27/108 , H01L45/00 , H01L27/24
CPC分类号： H01L45/146 , H01L27/2463 , H01L27/2481 , H01L45/08 , H01L45/1233 , H01L45/145 , H01L45/1675
摘要： A nonvolatile memory element which inhibits deterioration of an oxygen concentration profile of a variable resistance layer due to a thermal budget and is able to stably operate at low voltages, and a method for manufacturing the nonvolatile memory element are provided. The nonvolatile memory element includes a first electrode layer formed above a substrate, a variable resistance layer disposed on the first electrode layer, and a second electrode layer disposed on the variable resistance layer, and the variable resistance layer has a two-layer structure in which an oxygen- and/or nitrogen-deficient tantalum oxynitride layer and a tantalum oxide layer are stacked.
摘要翻译：提供一种非易失性存储元件，其抑制由于热预算导致的可变电阻层的氧浓度分布的劣化，并能够在低电压下稳定地工作，并且提供了一种制造非易失性存储元件的方法。非易失性存储元件包括形成在基板上的第一电极层，设置在第一电极层上的可变电阻层和设置在可变电阻层上的第二电极层，可变电阻层具有两层结构，其中氧和/或氮缺乏的氮氧化钽层和氧化钽层被堆叠。

7. 发明授权

US08969168B2 Method for manufacturing variable resistance element 有权
标题翻译：制造可变电阻元件的方法
公开(公告)号：US08969168B2
公开(公告)日：2015-03-03
申请号：US13809473
申请日：2012-01-30
申请人： Takeki Ninomiya , Yukio Hayakawa , Takumi Mikawa , Takeshi Takagi
发明人： Takeki Ninomiya , Yukio Hayakawa , Takumi Mikawa , Takeshi Takagi
IPC分类号： H01L45/00 , G11C13/00
CPC分类号： H01L45/1641 , G11C13/0007 , H01L45/08 , H01L45/146 , H01L45/1608 , H01L45/1675
摘要： Provided is a method for manufacturing a variable resistance element, the method including: forming a first electrode material layer above a substrate; forming a first tantalum oxide material layer; forming a second tantalum oxide material layer; forming a second electrode material layer; and annealing at least the first tantalum oxide material layer after forming the first tantalum oxide material layer and before forming the second electrode material layer, wherein an oxygen content percentage of one of the first tantalum oxide material layer and the second tantalum oxide material layer is higher than an oxygen content percentage of the other.
摘要翻译：提供一种制造可变电阻元件的方法，该方法包括：在衬底上形成第一电极材料层; 形成第一钽氧化物材料层; 形成第二钽氧化物材料层; 形成第二电极材料层; 以及在形成所述第一钽氧化物材料层之后并且在形成所述第二电极材料层之前至少退火所述第一钽氧化物材料层，其中所述第一钽氧化物材料层和所述第二氧化钽材料层中的一个的氧含量百分比较高比另一个的氧含量百分比。

8. 发明申请

US20120199805A1 NONVOLATILE MEMORY DEVICE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US20120199805A1
公开(公告)日：2012-08-09
申请号：US13501228
申请日：2011-08-11
申请人： Haruyuki Sorada , Takeki Ninomiya , Takumi Mikawa , Yukio Hayakawa
发明人： Haruyuki Sorada , Takeki Ninomiya , Takumi Mikawa , Yukio Hayakawa
IPC分类号： H01L47/00 , H01L21/02
CPC分类号： H01L27/101 , H01L27/2409 , H01L27/2463 , H01L45/08 , H01L45/1233 , H01L45/146 , H01L45/1608 , H01L45/1675
摘要： Provided are a nonvolatile memory device which can suppress non-uniformity in initial breakdown voltages among nonvolatile memory elements and prevent reduction of yield, and a manufacturing method thereof. The nonvolatile memory device includes a nonvolatile memory element (108) having a stacked-layer structure in which a resistance variable layer (106) is parallel to a main surface of a substrate (117) and is planarized, and a plug (103) electrically connected to either a first electrode (105) or a second electrode (107), and an area of an end surface of a plug (103) at which the plug (103) and the nonvolatile memory element (108) are connected together, the end surface being parallel to the main surface of the substrate (117), is greater than a cross-sectional area of a cross-section of a first transition metal oxide layer (115) which is an electrically-conductive region, the cross-section being parallel to the main surface of the substrate (117).
摘要翻译：提供一种能够抑制非易失性存储元件之间的初始击穿电压的不均匀性并且防止产量降低的非易失性存储器件及其制造方法。非易失性存储器件包括具有堆叠层结构的非易失性存储元件（108），其中电阻变化层（106）平行于衬底（117）的主表面并被平坦化;以及电极（103）连接到第一电极（105）或第二电极（107），以及插头（103）的端面（103）的与插头（103）和非易失性存储元件（108）连接在一起的区域，平行于基板（117）的主表面的端面大于作为导电区域的第一过渡金属氧化物层（115）的截面的横截面积，横截面平行于基板（117）的主表面。

9. 发明申请

US20120112153A1 NONVOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US20120112153A1
公开(公告)日：2012-05-10
申请号：US13380159
申请日：2011-07-13
申请人： Takeki Ninomiya , Satoru Fujii , Yukio Hayakawa , Takumi Mikawa
发明人： Takeki Ninomiya , Satoru Fujii , Yukio Hayakawa , Takumi Mikawa
IPC分类号： H01L45/00
CPC分类号： H01L45/08 , H01L45/1233 , H01L45/146 , H01L45/1625 , H01L45/1675
摘要： Provided is a nonvolatile memory device which requires a lower initializing voltage such that the nonvolatile memory device can be operated at a low voltage. The nonvolatile memory device (10) includes: a first electrode layer (105) formed above a semiconductor substrate (100); a first oxygen-deficient tantalum oxide layer (106x) formed on the first electrode layer (105) and having a composition represented by TaOx where 0.8≦x≦1.9; a second oxygen-deficient tantalum oxide layer (106y) formed on the first oxygen-deficient tantalum oxide layer (106x) and having a composition represented by TaOy where 2.1≦y; and a second electrode layer (107) formed on the second tantalum oxide layer (106y). The second tantalum oxide layer (106y) has a pillar structure including a plurality of pillars.
摘要翻译：提供了一种非易失性存储器件，其需要较低的初始化电压，使得非易失性存储器件可以在低电压下操作。非易失性存储器件（10）包括：形成在半导体衬底（100）上方的第一电极层（105）; 形成在第一电极层（105）上并具有由TaOx表示的组成的第一缺氧钽氧化物层（106x），其中0.8＆lt; 1; x＆nlE; 1.9; 在第一缺氧钽氧化物层（106x）上形成的第二氧缺陷氧化钽层（106y），其具有由TaOy表示的组成，其中2.1＆amp; 和形成在第二钽氧化物层（106y）上的第二电极层（107）。第二钽氧化物层（106y）具有包括多个柱的柱结构。

10. 发明申请

US20110114912A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US20110114912A1
公开(公告)日：2011-05-19
申请号：US12867437
申请日：2009-02-09
申请人： Takumi Mikawa , Yoshio Kawashima , Koji Arita , Takeki Ninomiya
发明人： Takumi Mikawa , Yoshio Kawashima , Koji Arita , Takeki Ninomiya
IPC分类号： H01L45/00 , H01L21/02
CPC分类号： H01L27/101 , H01L27/2436 , H01L45/04 , H01L45/1233 , H01L45/146 , H01L45/1675
摘要： A nonvolatile semiconductor memory device (100) comprises a substrate (102) provided with a transistor (101); a first interlayer insulating layer (103) formed over the substrate to cover the transistor; a first contact plug (104) formed in the first interlayer insulating layer and electrically connected to either of a drain electrode (101a) or a source electrode (101b) of the transistor, and a second contact plug (105) formed in the first interlayer insulating layer and electrically connected to the other of the drain electrode or the source electrode of the transistor; a resistance variable layer (106) formed to cover a portion of the first contact plug; a first wire (107) formed on the resistance variable layer; and a second wire (108) formed to cover a portion of the second contact plug; an end surface of the resistance variable layer being coplanar with an end surface of the first wire.
摘要翻译：非易失性半导体存储器件（100）包括设置有晶体管（101）的衬底（102）; 形成在所述衬底上以覆盖所述晶体管的第一层间绝缘层（103）形成在所述第一层间绝缘层中并电连接到所述晶体管的漏电极（101a）或源电极（101b）中的任一个的第一接触插塞（104）和形成在所述第一中间层绝缘层并与晶体管的漏电极或源电极中的另一个电连接; 形成为覆盖所述第一接触插塞的一部分的电阻变化层（106）形成在电阻变化层上的第一线（107）以及形成为覆盖所述第二接触插塞的一部分的第二线（108）所述电阻变化层的端面与所述第一线的端面共面。

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