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1. 发明授权

US08759190B2 Current steering element and non-volatile memory element incorporating current steering element 有权
标题翻译：目前的导向元件和非易失性存储元件结合了当前的转向元件
公开(公告)号：US08759190B2
公开(公告)日：2014-06-24
申请号：US13823667
申请日：2011-09-16
申请人： Ryoko Miyanaga , Takumi Mikawa , Yukio Hayakawa , Takeki Ninomiya , Koji Arita
发明人： Ryoko Miyanaga , Takumi Mikawa , Yukio Hayakawa , Takeki Ninomiya , Koji Arita
IPC分类号： H01L21/20
CPC分类号： H01L45/16 , H01L21/768 , H01L27/101 , H01L27/2409 , H01L27/2418 , H01L45/00 , H01L45/04 , H01L45/1233 , H01L45/146
摘要： A current steering element (100) formed such that the current steering element covers a lower opening (105) of a via hole (104) formed in an interlayer insulating layer (102), comprises: a corrosion-suppressing layer (106) formed on a lower side of a lower opening of the via hole such that the corrosion-suppressing layer covers an entire portion of the lower opening; a second electrode layer (108) formed under the corrosion-suppressing layer and comprising a material different from a material of the corrosion-suppressing layer; a current steering layer (110) formed under the second electrode layer such that the current steering layer is physically in contact with the second electrode layer; and a first electrode layer (112) formed under the current steering layer such that the first electrode layer is physically in contact with the current steering layer; and the first electrode layer, the current steering layer and the second electrode layer constitute one of a MSM diode and a MIM diode.
摘要翻译：一种形成为当前的操舵元件覆盖形成在层间绝缘层（102）中的通孔（104）的下开口（105）的电流控制元件（100），包括：形成在通孔的下开口的下侧，使得防蚀层覆盖下开口的整个部分; 形成在所述腐蚀抑制层下方并且包含不同于所述腐蚀抑制层的材料的材料的第二电极层（108）形成在所述第二电极层下方的电流转向层（110），使得所述电流导向层物理地与所述第二电极层接触; 以及第一电极层（112），形成在所述电流导向层下方，使得所述第一电极层物理地与所述电流转向层接触; 并且第一电极层，电流导向层和第二电极层构成MSM二极管和MIM二极管之一。

2. 发明申请

US20130224930A1 METHOD FOR MANUFACTURING VARIABLE RESISTANCE ELEMENT 审中-公开
标题翻译：制造可变电阻元件的方法
公开(公告)号：US20130224930A1
公开(公告)日：2013-08-29
申请号：US13805198
申请日：2011-06-21
申请人： Koji Arita , Takumi Mikawa
发明人： Koji Arita , Takumi Mikawa
IPC分类号： H01L45/00
CPC分类号： H01L45/16 , H01L27/2409 , H01L27/2418 , H01L27/2436 , H01L45/08 , H01L45/1233 , H01L45/146 , H01L45/1675
摘要： A variable resistance element manufacturing method includes: forming a conductive plug in an interlayer insulating film on a substrate; planarizing an upper surface of the insulating film such that an upper part of the conductive plug protrudes from an upper surface of the insulating film by removing (i) a depression in the insulating film formed around the conductive plug and (ii) a depression in the insulating film formed across a plurality of conductive plugs; forming, on the insulating film and the plug, a lower electrode layer electrically connected to the plug; planarizing an upper surface of the lower electrode layer to remove a protruding part on the upper surface of the lower electrode layer; forming, on the lower electrode layer, a variable resistance layer; forming an upper electrode layer on the variable resistance layer; and forming a lower electrode, the variable resistance layer, and an upper electrode layer.
摘要翻译：一种可变电阻元件制造方法，包括：在基板上的层间绝缘膜中形成导电插塞; 平面化绝缘膜的上表面，使得导电插塞的上部从绝缘膜的上表面突出，通过去除（i）形成在导电插塞周围的绝缘膜中的凹陷，以及（ii）形成在多个导电插塞上的绝缘膜; 在所述绝缘膜和所述插塞上形成电连接到所述插头的下电极层; 平面化下电极层的上表面以去除下电极层的上表面上的突出部分; 在下电极层上形成可变电阻层; 在所述可变电阻层上形成上电极层; 以及形成下电极，可变电阻层和上电极层。

3. 发明授权

US08394669B2 Resistance variable element and resistance variable memory device 有权
标题翻译：电阻可变元件和电阻变量存储器件
公开(公告)号：US08394669B2
公开(公告)日：2013-03-12
申请号：US13128575
申请日：2010-07-12
申请人： Koji Arita , Takumi Mikawa , Atsushi Himeno , Yoshio Kawashima , Kenji Tominaga
发明人： Koji Arita , Takumi Mikawa , Atsushi Himeno , Yoshio Kawashima , Kenji Tominaga
IPC分类号： H01L21/02 , H01L45/00
CPC分类号： H01L27/2409 , H01L27/2418 , H01L27/2463 , H01L45/08 , H01L45/1233 , H01L45/146 , H01L45/1666 , H01L45/1675
摘要： A resistance variable element (100) used in a through-hole cross-point structure memory device, according to the present invention, and a resistance variable memory device including the resistance variable element, includes a substrate (7) and an interlayer insulating layer (3) formed on the substrate, and have a configuration in which a through-hole (4) is formed to penetrate the interlayer insulating layer, a first resistance variable layer (2) comprising transition metal oxide is formed outside the through-hole, a second resistance variable layer (5) comprising transition metal oxide is formed inside the through-hole, the first resistance variable layer is different in resistivity from the second resistance variable layer, and the first resistance variable layer and the second resistance variable layer are in contact with each other only in an opening (20) of the through-hole which is closer to the substrate.
摘要翻译：在根据本发明的通孔交叉点结构存储装置中使用的电阻可变元件（100）和包括电阻可变元件的电阻变化存储装置包括基板（7）和层间绝缘层（ 3），并且具有形成贯通层间绝缘层的通孔（4）的构造，在通孔的外侧形成有包含过渡金属氧化物的第一电阻变化层（2），在通孔内形成有包含过渡金属氧化物的第二电阻变化层（5），第一电阻变化层的电阻率与第二电阻变化层不同，第一电阻变化层和第二电阻变化层接触彼此仅在更靠近基板的通孔的开口（20）中。

4. 发明授权

US08304908B2 Semiconductor device having a multilevel interconnect structure and method for fabricating the same 失效
标题翻译：具有多层互连结构的半导体器件及其制造方法
公开(公告)号：US08304908B2
公开(公告)日：2012-11-06
申请号：US12382624
申请日：2009-03-19
申请人： Junichi Koike , Yoshito Fujii , Jun Iijima , Noriyoshi Shimizu , Kazuyoshi Maekawa , Koji Arita , Ryotaro Yagi , Masaki Yoshimaru
发明人： Junichi Koike , Yoshito Fujii , Jun Iijima , Noriyoshi Shimizu , Kazuyoshi Maekawa , Koji Arita , Ryotaro Yagi , Masaki Yoshimaru
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40 , H01L27/10 , H01L29/74
CPC分类号： H01L21/76853 , H01L21/288 , H01L21/76834 , H01L21/76849 , H01L21/76856 , H01L21/76861 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A multilevel interconnect structure in a semiconductor device includes a first insulating layer formed on a semiconductor wafer, a Cu interconnect layer formed on the first insulating layer, a second insulating layer formed on the Cu interconnect layer, and a metal oxide layer formed at an interface between the Cu interconnect layer and the second insulating layer. The metal oxide layer is formed by immersion-plating a metal, such as Sn or Zn, on the Cu interconnect layer and then heat-treating the plated layer in an oxidizing atmosphere.
摘要翻译：半导体器件中的多层互连结构包括形成在半导体晶片上的第一绝缘层，形成在第一绝缘层上的Cu互连层，形成在Cu互连层上的第二绝缘层和形成在界面处的金属氧化物层在Cu互连层和第二绝缘层之间。金属氧化物层通过在Cu互连层上浸渍诸如Sn或Zn的金属，然后在氧化气氛中对镀层进行热处理而形成。

5. 发明申请

US20080023335A1 METHOD OF FABRICATING SEMICONDUCTOR DEVICE, AND PLATING APPARATUS 有权
标题翻译：制造半导体器件的方法和镀膜设备
公开(公告)号：US20080023335A1
公开(公告)日：2008-01-31
申请号：US11829129
申请日：2007-07-27
申请人： Koji ARITA , Ryohei KITAO
发明人： Koji ARITA , Ryohei KITAO
IPC分类号： C25D7/12 , C25D17/00 , C25D21/12 , C25D5/00
CPC分类号： C25D21/12 , H01L21/2885 , H01L21/76877
摘要： A method of fabricating a semiconductor device of the invention includes a plating process of filling a plurality of recesses provided to an insulating film formed on a substrate with an electro-conductive material, wherein the plating process includes a process step (S104) of performing the plating with a first current density which was obtained by correcting a predetermined first reference current density based on ratio of surface area Sr═S1/S2 of a first surface area S1 over the entire surface of the substrate which includes the area of side walls of the plurality of recesses over the entire surface of the semiconductor substrate, and a second surface area S2 over the entire surface of the substrate which does not include the area of side walls of the plurality of recesses, when fine recesses not larger than a predetermined width, out of all of the plurality of recesses, are filled with the electro-conductive material.
摘要翻译：制造本发明的半导体器件的方法包括：用导电材料填充设置在形成在基板上的绝缘膜的多个凹槽的电镀工艺，其中所述电镀工艺包括执行步骤（S104）的工艺步骤（S104）通过基于第一表面积S的表面积Sr-S 1/2的比例来校正预定的第一参考电流密度而获得的第一电流密度的电镀在衬底的整个表面上，包括在半导体衬底的整个表面上的多个凹槽的侧壁的面积，以及第二表面区域2＆lt; 2＆gt; 在不包括多个凹部的侧壁的区域的基板的整个表面上，当在多个凹部的所有凹部中的不大于预定宽度的细小凹部填充有导电材料时。

6. 发明申请

US20070190341A1 Semiconductor device and method for manufacturing same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20070190341A1
公开(公告)日：2007-08-16
申请号：US11704950
申请日：2007-02-12
申请人： Akira Furuya , Koji Arita , Tetsuya Kurokawa , Kaori Noda
发明人： Akira Furuya , Koji Arita , Tetsuya Kurokawa , Kaori Noda
IPC分类号： C25D5/02 , B32B13/04
CPC分类号： C25D3/38 , C25D5/50 , C25D7/123 , C25D15/00 , H01L21/2885 , H01L21/76801 , H01L21/76829 , H01L21/76873 , H01L21/76877 , H01L21/76883
摘要： An improved SIV resistance and an improved EM resistance are achieved in the coupling structure containing copper films. A semiconductor device includes: a semiconductor substrate; a second insulating layer formed on or over the semiconductor substrate; a second barrier metal film, formed on the second insulating film, and being capable of preventing copper from diffusing into the second insulating film; and an electrically conducting film formed on the second barrier metal film so as to be in contact with the second barrier metal film, and containing copper and carbon, wherein a distribution of carbon concentration along a depositing direction in the second electrically conducting film includes a first peak and a second peak.
摘要翻译：在包含铜膜的耦合结构中实现了改进的SIV电阻和改进的EM电阻。半导体器件包括：半导体衬底; 形成在所述半导体衬底上或之上的第二绝缘层; 第二阻挡金属膜，形成在所述第二绝缘膜上，并且能够防止铜扩散到所述第二绝缘膜中; 以及形成在所述第二阻挡金属膜上以与所述第二阻挡金属膜接触并且含有铜和碳的导电膜，其中所述第二导电膜中沿着沉积方向的碳浓度的分布包括第一峰值和第二高峰。

7. 发明授权

US07132732B2 Semiconductor device having two distinct sioch layers 失效
标题翻译：半导体器件具有两个不同的透镜层
公开(公告)号：US07132732B2
公开(公告)日：2006-11-07
申请号：US10767786
申请日：2004-01-29
申请人： Koichi Ohto , Tatsuya Usami , Noboru Morita , Sadayuki Ohnishi , Koji Arita , Ryohei Kitao , Yoichi Sasaki
发明人： Koichi Ohto , Tatsuya Usami , Noboru Morita , Sadayuki Ohnishi , Koji Arita , Ryohei Kitao , Yoichi Sasaki
IPC分类号： H01L23/58 , H01L23/48
CPC分类号： H01L23/53228 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device has a semiconductor substrate, and a multi-layered wiring arrangement provided thereon. The multi-layered wring arrangement includes at least one insulating layer structure having a metal wiring pattern formed therein. The insulating layer structure includes a first SiOCH layer, a second SiOCH layer formed on the first SiOCH layer, and a silicon dioxide (SiO2) layer formed on the second SiOCH layer. The second SiOCH layer features a carbon (C) density lower than that of the first SiOCH layer, a hydrogen (H) density lower than that of the first SiOCH layer, and an oxygen (O) density higher than that of the first SiOCH layer.
摘要翻译：半导体器件具有半导体衬底和设置在其上的多层布线装置。多层绞合装置包括其中形成有金属布线图案的至少一个绝缘层结构。绝缘层结构包括第一SiOCH层，形成在第一SiOCH层上的第二SiOCH层和形成在第二SiOCH层上的二氧化硅（SiO 2）层。第二SiOCH层的碳（C）密度低于第一SiOCH层的碳（C）密度，氢（H）密度低于第一SiOCH层的密度，氧（O）密度高于第一SiOCH层。

8. 发明授权

US06989328B2 Method of manufacturing semiconductor device having damascene interconnection 有权
标题翻译：制造具有镶嵌互连的半导体器件的方法
公开(公告)号：US06989328B2
公开(公告)日：2006-01-24
申请号：US10777198
申请日：2004-02-13
申请人： Koji Arita , Kaoru Mikagi , Ryohei Kitao
发明人： Koji Arita , Kaoru Mikagi , Ryohei Kitao
IPC分类号： H01L21/44
CPC分类号： H01L21/76877 , H01L21/2885
摘要： In copper plating using a damascene method, in order to prevent cost rise, dishing, erosion and the like due to the protrusion of plating on the dense wiring area to increase the time for CMP polishing, the copper plating is performed so that the current step of the copper plating has only one step for flowing current in the direction opposite to the direction of growing the plating as shown in FIG. 1. In this time, this opposite direction current step is performed under the condition of a current-time product within a range between 1.0 and 120 mA×sec/cm2.
摘要翻译：在使用镶嵌方法的镀铜中，为了防止由于在致密配线区域上的电镀突出而引起的成本上升，凹陷，侵蚀等，以增加CMP抛光的时间，进行镀铜，使得电流步骤的铜电镀仅在与电镀方向相反的方向流动电流的一个步骤，如图3所示。 1。此时，在1.0〜120mA / sec / cm 2范围内的当前时间积的条件下进行该相反方向电流步骤。

9. 发明授权

US06639262B2 Metal oxide integrated circuit on silicon germanium substrate 失效
标题翻译：硅锗基板上的金属氧化物集成电路
公开(公告)号：US06639262B2
公开(公告)日：2003-10-28
申请号：US09906285
申请日：2001-07-16
申请人： Carlos A. Paz de Araujo , Masamichi Azuma , Larry D. McMillan , Koji Arita
发明人： Carlos A. Paz de Araujo , Masamichi Azuma , Larry D. McMillan , Koji Arita
IPC分类号： H01L31119
CPC分类号： H01L21/02197 , C04B35/4682 , C04B35/6264 , C04B2235/3213 , C04B2235/3224 , C04B2235/3227 , C04B2235/3229 , C04B2235/3243 , C04B2235/3268 , C04B2235/441 , C04B2235/449 , C04B2235/72 , C23C16/4412 , C23C16/448 , C23C16/4486 , C23C16/45561 , C23C16/4558 , C23C16/46 , C23C16/482 , C23C16/52 , C23C18/1216 , C23C18/1225 , C23C18/1245 , C23C18/1275 , C23C18/1279 , C23C18/1283 , C23C18/14 , C30B7/00 , C30B7/005 , C30B29/68 , H01C7/1013 , H01L21/02164 , H01L21/0217 , H01L21/022 , H01L21/02282 , H01L21/314 , H01L21/31691 , H01L27/10805 , H01L27/11502 , H01L28/55 , H01L28/56 , H01L28/60 , H01L28/75
摘要： Integrated circuit capacitors in which the capacitor dielectric is a thin film of BST having a grain size smaller than 200 nanometers formed above a silicon germanium substrate. Typical grain sizes are 40 nm and less. The BST is formed by deposition of a liquid precursor by a spin-on process. The original liquid precursor includes an alkoxycarboxylate dissolved in 2-methoxyethanol and a xylene exchange is performed just prior to spinning. The precursor is dried in air at a temperature of about 400° C. and then furnace annealed in oxygen at a temperature of between 600° C. and 850° C.
摘要翻译：集成电路电容器，其中电容器电介质是在硅锗衬底上方形成的具有小于200纳米的晶粒尺寸的BST薄膜。典型的晶粒尺寸为40nm以下。 BST通过旋涂工艺沉积液体前体而形成。原始液体前体包括溶解在2-甲氧基乙醇中的烷氧基羧酸酯，并且在旋转之前进行二甲苯交换。前体在空气中在约400℃的温度下干燥，然后在600℃至850℃的温度下在氧气中进行炉退火。

10. 发明授权

US06537830B1 Method of making ferroelectric FET with polycrystalline crystallographically oriented ferroelectric material 失效
标题翻译：制造具有多晶结晶取向铁电材料的铁电FET的方法
公开(公告)号：US06537830B1
公开(公告)日：2003-03-25
申请号：US09533204
申请日：2000-03-23
申请人： Koji Arita , Carlos A. Paz de Araujo , Larry D. McMillan , Masamichi Azuma
发明人： Koji Arita , Carlos A. Paz de Araujo , Larry D. McMillan , Masamichi Azuma
IPC分类号： H01L2100
CPC分类号： C23C16/4558 , C23C16/4412 , C23C16/448 , C23C16/4486 , C23C16/45561 , C23C16/482 , C23C16/52 , C23C18/1216 , C23C18/1279 , C23C18/1283 , C23C18/14 , C30B7/00 , C30B7/005 , C30B29/68 , H01L21/31691 , H01L27/10805 , H01L27/11502 , H01L28/55 , H01L28/56 , H01L28/60
摘要： A nondestructive read-out, nonvolatile ferroelectric field effect transistor (“FET”) memory in an integrated circuit, containing a thin film of polycrystalline crystallographically oriented ferroelectric material. Preferably, the material is polycrystalline c-axis oriented layered superlattice material. More preferably, it is c-axis oriented strontium bismuth tantalate or strontium bismuth tantalum niobate.
摘要翻译：集成电路中的非破坏性读出非易失性铁电场效应晶体管（“FET”）存储器，其包含多晶结晶取向铁电材料的薄膜。优选地，材料是多晶c轴取向层状超晶格材料。更优选的是c轴取向的钽酸铋铋或铌酸铋钽铌酸盐。

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