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1. 发明授权

US6033953A Method for manufacturing dielectric capacitor, dielectric memory device 失效
标题翻译：介质电容器的制造方法，介质存储器件
公开(公告)号：US6033953A
公开(公告)日：2000-03-07
申请号：US991132
申请日：1997-12-16
申请人： Katsuhiro Aoki , Yukio Fukuda , Ken Numata , Yasutoshi Okuno , Akitoshi Nishimura
发明人： Katsuhiro Aoki , Yukio Fukuda , Ken Numata , Yasutoshi Okuno , Akitoshi Nishimura
IPC分类号： H01G4/33 , H01L21/02 , H01L21/321 , H01L21/8242 , H01L21/8246 , H01L27/10 , H01L27/105 , H01L27/108
CPC分类号： H01L27/1085 , H01L28/60 , H01L21/32115
摘要： A dielectric capacitor is provided which has a reduced leakage current. The surface of a first electrode (38) of the capacitor is electropolished and a dielectric film (40) and a second electrode (37) are successively laminated on it. The convex parts pointed end (38a) existing on the surface of the first electrode is very finely polished uniformly by dissolving according to electropolishing, a spherical curved surface in which the radius of curvature has been enlarged is formed, and the surface of the first electrode is flattened. Therefore, concentration of electrolysis can be prevented during the operation at the interface of the first electrode and the dielectric film, and the leakage current can be reduced considerably.
摘要翻译：提供了具有减小的漏电流的介质电容器。对电容器的第一电极（38）的表面进行电解抛光，并在其上依次层压电介质膜（40）和第二电极（37）。存在于第一电极表面上的凸部尖端（38a）通过电解抛光溶解而形成非常细微的抛光，形成曲面半径扩大的球面曲面，第一电极的表面扁平化因此，在第一电极和电介质膜的界面的操作期间可以防止电解浓度，并且可以显着降低泄漏电流。

2. 发明授权

US5654567A Capacitor, electrode or wiring structure, and semi conductor device 失效
标题翻译：电容器，电极或布线结构以及半导体器件
公开(公告)号：US5654567A
公开(公告)日：1997-08-05
申请号：US724159
申请日：1996-10-01
申请人： Ken Numata , Katsuhiro Aoki , Yukio Fukuda , Akitoshi Nishimura
发明人： Ken Numata , Katsuhiro Aoki , Yukio Fukuda , Akitoshi Nishimura
IPC分类号： H01L21/3205 , H01L21/822 , H01L21/8242 , H01L21/8246 , H01L23/52 , H01L27/04 , H01L27/10 , H01L27/105 , H01L27/108 , H01L27/115 , H01L29/78 , H01L23/48 , H01L27/02 , H01L29/68
CPC分类号： H01L27/11502
摘要： A capacitor, electrode, or wiring structure having an alpha ray emitting source (in particular, a Pt electrode), and an alpha ray shielding layer 18, having at least one type selected from the group of simple metals of nickel, cobalt, copper, and tungsten, their compounds or alloys made of at least two types of these simple metals, and compounds and alloys made of these simple metals and silicon is provided. It is possible to shield off the alpha ray effectively, to suppress generation of soft errors, to enable the use of Pt and other new materials in making the electrodes and wiring, and to reduce the cost of the mold resin.
摘要翻译：具有α射线发射源（特别是Pt电极）的电容器，电极或布线结构以及具有选自镍，钴，铜等的一类金属的至少一种的α射线屏蔽层18，提供了由这些简单金属中的至少两种类型制成的钨，它们的化合物或合金，以及由这些简单金属和硅制成的化合物和合金。可以有效地屏蔽α射线，以抑制软错误的产生，从而能够在制造电极和布线中使用Pt等新材料，并降低模制树脂的成本。

3. 发明授权

US5793600A Method for forming high dielectric capacitor electrode structure and semiconductor memory devices 失效
标题翻译：高介电电容电极结构和半导体存储器件的形成方法
公开(公告)号：US5793600A
公开(公告)日：1998-08-11
申请号：US545980
申请日：1995-10-20
申请人： Yukio Fukuda , Katsuhiro Aoki , Akitoshi Nishimura , Ken Numata
发明人： Yukio Fukuda , Katsuhiro Aoki , Akitoshi Nishimura , Ken Numata
IPC分类号： H01L21/02 , H01G4/06 , H01G7/00
CPC分类号： H01L28/75 , H01L28/60 , H01L28/55 , Y10T29/435
摘要： A capacitor and electrode structure comprising a PZT ferroelectric layer 17 with a primary component (Pb) and secondary component (Ti), a lower electrode layer 16 formed on the underside of the ferroelectric layer and made up of a special element (Pt) and Ti, and compounds thereof, and a diffusion barrier layer 18 which is formed on the underside of the lower electrode layer and which functions as a diffusion barrier with respect to Pb. The capacitor and the electrode structure, which may be a component of a semiconductor memory device, suppress fluctuations in the composition of the ferroelectric layer in PZT, etc., so as to maintain the intended performance of the PZT ferroelectric layer, thereby simplifying and stabilizing film fabrication, and preventing the degradation of electrical characteristics and adverse effects on lower layers.
摘要翻译：包括具有主要组分（Pb）和次要组分（Ti）的PZT铁电层17的电容器和电极结构，形成在铁电层的下侧上并由特殊元素（Pt）和Ti构成的下电极层16 ，及其化合物，以及扩散阻挡层18，其形成在下电极层的下侧，并且用作相对于Pb的扩散阻挡层。可以是半导体存储器件的组件的电容器和电极结构抑制PZT等中的铁电层的组成的波动，以保持PZT铁电层的预期性能，从而简化和稳定薄膜制造，并防止电气特性的劣化和对较低层的不利影响。

4. 发明授权

US5508953A Capacitor, electrode structure, and semiconductor memory device 失效
标题翻译：电容器，电极结构和半导体存储器件
公开(公告)号：US5508953A
公开(公告)日：1996-04-16
申请号：US242924
申请日：1994-05-16
申请人： Yukio Fukuda , Katsuhiro Aoki , Akitoshi Nishimura , Ken Numata
发明人： Yukio Fukuda , Katsuhiro Aoki , Akitoshi Nishimura , Ken Numata
IPC分类号： H01L27/04 , H01L21/02 , H01L21/822 , H01L21/8242 , H01L21/8246 , H01L27/10 , H01L27/105 , H01L27/108 , G11C11/22
CPC分类号： H01L28/55 , H01L28/60 , H01L28/75
摘要： A capacitor and electrode structure comprising a PZT ferroelectric layer 17 with a primary component (Pb) and secondary component (Ti), a lower electrode layer 16 formed on the underside of the ferroelectric layer and made up of a special element (Pt) and Ti, and compounds thereof, and a diffusion barrier layer 18 which is formed on the underside of the lower electrode layer and which functions as a diffusion barrier with respect to Pb. The capacitor and the electrode structure, which may be a component of a semiconductor memory device, suppress fluctuations in the composition of the ferroelectric layer in PZT, etc., so as to maintain the intended performance of the PZT ferroelectric layer, thereby simplifying and stabilizing film fabrication, and preventing the degradation of electrical characteristics and adverse effects on lower layers.
摘要翻译：包括具有主要组分（Pb）和次要组分（Ti）的PZT铁电层17的电容器和电极结构，形成在铁电层的下侧上并由特殊元素（Pt）和Ti构成的下电极层16 ，及其化合物，以及扩散阻挡层18，其形成在下电极层的下侧，并且用作相对于Pb的扩散阻挡层。可以是半导体存储器件的组件的电容器和电极结构抑制PZT等中的铁电层的组成的波动，以保持PZT铁电层的预期性能，从而简化和稳定薄膜制造，并防止电气特性的劣化和对较低层的不利影响。

5. 发明授权

US06297085B1 Method for manufacturing ferroelectric capacitor and method for manufacturing ferroelectric memory 失效
标题翻译：铁电电容器的制造方法及其制造方法
公开(公告)号：US06297085B1
公开(公告)日：2001-10-02
申请号：US08988687
申请日：1997-12-11
申请人： Katsuhiro Aoki , Yukio Fukuda , Ikuko Murayama , Ken Numata , Akitoshi Nishimura
发明人： Katsuhiro Aoki , Yukio Fukuda , Ikuko Murayama , Ken Numata , Akitoshi Nishimura
IPC分类号： H01L218242
CPC分类号： H01L27/11502 , H01L21/02197 , H01L21/02266 , H01L21/31691 , H01L27/1085 , H01L28/56
摘要： To provide a method that can be used to form a high-qualility ferroelectric film by forming good nuclei when using the sputtering method to manufacture a PZT capacitor or other forroelectric capacitors using Ir or other electrode substances in addition to Pt for the electrode. In the method for manufacturing a PZT ferroelectric capacitor CAP, after titanium film 31 is deposited on Ir electrode 6, lead oxide 32 is deposited at a substrate temperature higher than the crystallization temperature of lead titanate using the sputtering method. Lead zirconate titanate 34 is then deposited at a substrate temperature higher than the aforementioned substrate temperature using the sputtering temperature. Afterwards, a heat treatment of the deposited film is performed to produce PZT film 17.
摘要翻译：为了提供一种方法，当使用溅射方法制造PZT电容器或使用Ir或其它电极物质的其它电介质电容器或除电极用Pt之外的其他电介质电容器时，可以通过形成良好的核来形成高质量铁电体膜。在制造PZT铁电体电容器CAP的方法中，在氧化钛电极6上沉积钛膜31之后，使用溅射法在高于钛酸铅的结晶温度的衬底温度下沉积氧化铅32。然后使用溅射温度在高于上述衬底温度的衬底温度下沉积锆钛酸铅34。然后，进行沉积膜的热处理以产生PZT膜17。

6. 发明授权

US6150183A Method for manufacturing metal oxide capacitor and method for manufacturing semiconductor memory device 失效
标题翻译：制造金属氧化物电容器的方法及半导体存储器件的制造方法
公开(公告)号：US6150183A
公开(公告)日：2000-11-21
申请号：US993873
申请日：1997-12-18
申请人： Yukio Fukuda , Katsuhiro Aoki , Akitoshi Nishimura , Ken Numata
发明人： Yukio Fukuda , Katsuhiro Aoki , Akitoshi Nishimura , Ken Numata
IPC分类号： H01L27/04 , H01L21/02 , H01L21/314 , H01L21/316 , H01L21/822 , H01L21/8242 , H01L27/108 , H01G7/06
CPC分类号： H01L21/02197 , H01L21/02266 , H01L21/31691 , H01L28/55
摘要： A metal oxide capacitor is manufactured by sequentially laminating a metal oxide film and a secon electrode on a first electrode. The metal oxide film is formed and then heat-treated in an atmosphere with an oxygen pressure higher than 1 atm.
摘要翻译：通过在第一电极上依次层叠金属氧化物膜和第二电极来制造金属氧化物电容器。形成金属氧化物膜，然后在氧气压力高于1atm的气氛中进行热处理。

7. 发明授权

US06472229B1 Method for manufacturing a ferroelectric capacitor having improved polarization characteristics and a method for manufacturing a ferroelectric memory device incorporating such capacitor 失效
标题翻译：具有改善偏振特性的铁电电容器的制造方法以及包含这种电容器的铁电存储器件的制造方法
公开(公告)号：US06472229B1
公开(公告)日：2002-10-29
申请号：US09092686
申请日：1998-06-05
申请人： Katsuhiro Aoki , Yukio Fukuda , Ken Numata
发明人： Katsuhiro Aoki , Yukio Fukuda , Ken Numata
IPC分类号： H01L2100
CPC分类号： H01L27/11502 , H01L21/02197 , H01L21/02356 , H01L21/31122 , H01L21/31691 , H01L27/11507
摘要： The purpose of this invention is to provide a method for manufacturing capacitors free of polarization fatigue even when the treatment is performed at a low temperature. Amorphous layer 32 made of lead zirconate titanate and containing excess lead is formed on lower electrode 13 made of iridium. The amorphous layer is crystallized by a heat treatment to form PZT film 14. Structural transition layer 33 containing excess Pb formed on the surface of PZT film 14 during the aforementioned crystallization is removed by means of dry etching. In this way, a PZT capacitor is obtained.
摘要翻译：本发明的目的是提供即使在低温下进行处理而制造没有极化疲劳的电容器的方法。在由铱制成的下电极13上形成由锆钛酸铅制成并含有过量铅的无定形层32。通过热处理使非晶层结晶以形成PZT膜14.通过干蚀刻除去在上述结晶期间含有在PZT膜14的表面上形成的过量Pb的结构过渡层33。以这种方式，获得PZT电容器。

8. 发明申请

US20100244027A1 Semiconductor device and method of controlling the same 审中-公开
标题翻译：半导体装置及其控制方法
公开(公告)号：US20100244027A1
公开(公告)日：2010-09-30
申请号：US12659941
申请日：2010-03-25
申请人： Ken Numata
发明人： Ken Numata
IPC分类号： H01L29/92 , H01L27/06
CPC分类号： H01L28/60 , G11C11/404 , G11C11/4076 , G11C11/4091 , G11C11/4094 , H01L27/10814 , H01L27/10852 , H01L28/65
摘要： A semiconductor device includes a capacitor element that stores charge to perform as a memory that stores information. The capacitor may include, but is not limited to, an insulating layer, a first electrode, and a second electrode. The insulating layer includes metal oxide. The insulating layer has a high dielectric constant. The first electrode contacts with a first surface of the insulating layer. The first electrode is made of a first conductive material including at least one of precious metals and compounds thereof. The second electrode contacts with a second surface of the insulating layer. The second electrode is made of a second conductive material including at least one of metals and compounds thereof. The metals are different from the precious metals. The second conductive material is lower in work function than the first conductive material. The first electrode is lower in potential than the second electrode.
摘要翻译：半导体器件包括存储电荷作为存储信息的存储器的电容器元件。电容器可以包括但不限于绝缘层，第一电极和第二电极。绝缘层包括金属氧化物。绝缘层具有高介电常数。第一电极与绝缘层的第一表面接触。第一电极由包括贵金属及其化合物中的至少一种的第一导电材料制成。第二电极与绝缘层的第二表面接触。第二电极由包括金属及其化合物中的至少一种的第二导电材料制成。金属与贵金属不同。第二导电材料的功函数低于第一导电材料。第一电极的电位低于第二电极。

9. 发明授权

US5811352A Method of making reliable metal leads in high speed LSI semiconductors using dummy leads 失效
标题翻译：使用虚拟引线在高速LSI半导体中制造可靠的金属引线的方法
公开(公告)号：US5811352A
公开(公告)日：1998-09-22
申请号：US857803
申请日：1996-11-06
申请人： Ken Numata , Kay Houston
发明人： Ken Numata , Kay Houston
IPC分类号： H01L23/52 , H01L21/3205 , H01L21/768 , H01L23/522 , H01L21/28
CPC分类号： H01L23/522 , H01L2924/0002 , Y10S438/926
摘要： A method for manufacturing semiconductor device having conductive metal leads 14 with improved reliability, and device for same, comprising conductive metal leads 14 on a substrate 12, a first insulating material 18 at least between the conductive metal leads 14, and dummy leads 16 proximate the conductive metal leads 14. Heat from the conductive metal leads 14 is transferable to the dummy leads 16, and the dummy leads 16 are capable of dissipating the heat. The first insulating material 18 has a dielectric constant of less than 3.5. An optional heatsink 22 may be formed in contact with the first dummy leads 16 to further dissipate the Joule's heat from the conductive metal leads 14. An advantage of the invention is to improve reliability of metal leads for circuits using low-dielectric constant materials.
摘要翻译：一种用于制造具有改善的可靠性的导电金属引线14及其装置的半导体器件的方法，其包括在基底12上的导电金属引线14，至少在导电金属引线14之间的第一绝缘材料18和靠近导电金属引线14.来自导电金属引线14的热量可转移到虚拟引线16，虚拟引线16能够散热。第一绝缘材料18的介电常数小于3.5。可选的散热器22可形成为与第一虚拟引线16接触，以进一步从导电金属引线14消散焦耳热。本发明的优点在于提高使用低介电常数材料的电路的金属引线的可靠性。

10. 发明授权

US06326695B1 Twisted bit line structures and method for making same 有权
标题翻译：双绞线结构及其制作方法
公开(公告)号：US06326695B1
公开(公告)日：2001-12-04
申请号：US09405263
申请日：1999-09-23
申请人： Ken Numata
发明人： Ken Numata
IPC分类号： H01L2941
CPC分类号： G11C11/4097 , H01L23/5225 , H01L2924/0002 , H01L2924/00
摘要： A twisted bit line structure (69) in an integrated memory circuit, and method for making it are presented. The structure is constructed by forming bit line traces (70-73) on an integrated circuit substrate using phase shift lithography techniques. Using these techniques, the bit line traces are arranged with a plurality of substantially parallel bit lines trace segments (70, 70′; 71, 71′; 72, 72′; 73, 73′) with discontinuous regions between segments of each trace along a path substantially perpendicular to the bit line traces. Thus, each “phase &pgr;” bit line trace is adjacent a “phase 0” bit line trace along two perpendicular axes. A twist connection (74) is formed between first segments (72, 71′) of a center pair (71, 72) of said bit line trace segments, and a bit line twist interconnection (82) is formed between second segments (71, 72′) of said center pair of said bit line trace segments on a second integrated circuit level from a level containing the bit line traces. Linear interconnections (75, 76) are also formed between segments of outside bit line segments (70, 70′; 73, 73′) to form continuous untwisted bit lines. The linear interconnections are also formed on an integrated circuit level different from the level containing the bit line traces.
摘要翻译：提出了一种集成存储器电路中的扭曲位线结构（69）及其制造方法。通过使用相移光刻技术在集成电路基板上形成位线迹线（70-73）来构造该结构。使用这些技术，位线迹线布置有多个基本上平行的位线迹线段（70,70'; 71,71'; 72,72'; 73,73'），其中每个迹线的段之间具有不连续区域基本上垂直于位线迹线的路径。因此，每个“相位”位线迹线沿着两个垂直轴相邻于“相位0”位线迹线。在所述位线迹线段的中心对（71,72）的第一段（72,71'）之间形成扭转连接（74），并且位线扭转互连（82）形成在第二段 72'）位于来自包含位线迹线的电平的第二集成电路电平上的所述中心对的所述位线迹线段。在外部位线段（70,70'; 73,73'）的段之间也形成线性互连（75,76），以形成连续的未扭绞位线。线性互连也形成在与包含位线迹线的电平不同的集成电路电平上。

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