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1. 发明授权

US06728128B2 Dummy cell structure for 1T1C FeRAM cell array 有权
标题翻译： 1T1C FeRAM单元阵列的虚拟单元结构
公开(公告)号：US06728128B2
公开(公告)日：2004-04-27
申请号：US10397878
申请日：2003-03-26
申请人： Akitoshi Nishimura , Yukio Fukuda , Katsuhiro Aoki
发明人： Akitoshi Nishimura , Yukio Fukuda , Katsuhiro Aoki
IPC分类号： G11C1122
CPC分类号： G11C11/22 , G11C7/14
摘要： A ferroelectric memory structure is described for the 1T1C arrangement in a ferroelectric capacitor cell array for FeRAM memory device applications. The device structure provides an accurate reference voltage and a simple sensing scheme for the sense amplifier used for reading the state of a target memory cell of the FeRAM array. A reference circuit generates a reference voltage which is a function of a charge shared between a plurality of FeRAM dummy cells. Each dummy cell of the plurality of FeRAM dummy cells is selectively coupleable to a plurality of bitlines. A shorting transistor in the reference circuit couples two bitlines or two bitline-bars neighboring the selected target memory cell. One dummy cell is coupled to a select one of the two shorted bitlines or bitline-bars, and another dummy cell is coupled to a another of the two shorted bitlines or bitline-bars, wherein at least one dummy cell is biased to a “0” state, and at least one other dummy cell is biased to a “1” state. As charge sharing takes place between the bias states of the dummy cells and the shorted bitlines, an averaged reference voltage is produced which is substantially centered between the “0” or “1” states. A sense amplifier receives a sense signal from the target memory cell on an associated bitline, and the averaged reference voltage is received on another bitline input of the sense amplifier. Thus, a new ferroelectric memory structure provides a centered reference voltage and a simple sensing scheme for the accurate sensing of the logic state of an FeRAM 1T1C cell for a read operation.
摘要翻译：对于FeRAM存储器件应用的铁电电容器单元阵列中的1T1C布置描述了铁电存储器结构。器件结构为读取FeRAM阵列的目标存储单元的状态的读出放大器提供精确的参考电压和简单的感测方案。参考电路产生参考电压，其是在多个FeRAM虚拟单元之间共享的电荷的函数。多个FeRAM虚拟单元中的每个虚拟单元选择性地耦合到多个位线。参考电路中的短路晶体管将与所选择的目标存储器单元相邻的两个位线或两个位线条耦合。一个虚拟单元耦合到两个短路位线或位线条中的选择一个，另一个虚设单元耦合到两个短路位线或位线条中的另一个，其中至少一个虚设单元偏置为“0” “状态，并且至少一个其他虚拟单元被偏置到”1“状态。由于在虚设单元的偏置状态和短路位线之间发生电荷共享，产生基本上以“0”或“1”状态为中心的平均参考电压。感测放大器在相关联的位线上接收来自目标存储器单元的感测信号，并且平均参考电压在读出放大器的另一位线输入端上被接收。因此，新的铁电存储器结构提供了居中的参考电压和用于精确检测用于读取操作的FeRAM 1T1C单元的逻辑状态的简单感测方案。

2. 发明授权

US06724646B2 Dummy cell structure for 1T1C FeRAM cell array 有权
公开(公告)号：US06724646B2
公开(公告)日：2004-04-20
申请号：US10397409
申请日：2003-03-26
申请人： Akitoshi Nishimura , Yukio Fukuda , Katsuhiro Aoki
发明人： Akitoshi Nishimura , Yukio Fukuda , Katsuhiro Aoki
IPC分类号： G11C1122
CPC分类号： G11C11/22 , G11C7/14
摘要： A ferroelectric memory structure is described for the 1T1C arrangement in a ferroelectric capacitor cell array for FeRAM memory device applications. The device structure provides an accurate reference voltage and a simple sensing scheme for the sense amplifier used for reading the state of a target memory cell of the FeRAM array. A reference circuit generates a reference voltage which is a function of a charge shared between a plurality of FeRAM dummy cells. Each dummy cell of the plurality of FeRAM dummy cells is selectively coupleable to a plurality of bitlines. A shorting transistor in the reference circuit couples two bitlines or two bitline-bars neighboring the selected target memory cell. One dummy cell is coupled to a select one of the two shorted bitlines or bitline-bars, and another dummy cell is coupled to a another of the two shorted bitlines or bitline-bars, wherein at least one dummy cell is biased to a “0” state, and at least one other dummy cell is biased to a “1” state. As charge sharing takes place between the bias states of the dummy cells and the shorted bitlines, an averaged reference voltage is produced which is substantially centered between the “0” or “1” states. A sense amplifier receives a sense signal from the target memory cell on an associated bitline, and the averaged reference voltage is received on another bitline input of the sense amplifier. Thus, a new ferroelectric memory structure provides a centered reference voltage and a simple sensing scheme for the accurate sensing of the logic state of an FeRAM 1T1C cell for a read operation.

3. 发明授权

US06587367B1 Dummy cell structure for 1T1C FeRAM cell array 有权
标题翻译： 1T1C FeRAM单元阵列的虚拟单元结构
公开(公告)号：US06587367B1
公开(公告)日：2003-07-01
申请号：US10102418
申请日：2002-03-19
申请人： Akitoshi Nishimura , Yukio Fukuda , Katsuhiro Aoki
发明人： Akitoshi Nishimura , Yukio Fukuda , Katsuhiro Aoki
IPC分类号： G11C1122
CPC分类号： G11C11/22 , G11C7/14
摘要： A ferroelectric memory structure is described for the 1T1C arrangement in ferroelectric capacitor cell array for FeRAM memory device applications. The device structure provides an accurate reference voltage and a simple sensing scheme for the sense amplifier used for reading the state of a target memory cell of the FeRAM array. A reference circuit generates a reference voltage which is a function of a charge shared between a plurality of FeRAM dummy cells. Each dummy cell of the plurality of FeRAM dummy cells is selectively coupleable to a plurality of bitlines. A shorting transistor in the reference circuit couples two bitlines or two bitline-bars neighboring the selected target memory cell. One dummy cell is coupled to a select one of the two shorted bitlines or bitline-bars, and another dummy cell is coupled to a another of the two shorted bitlines or bitline-bars, wherein at least one dummy cell is biased to a “0” state, and at least one other dummy cell is biased to a “1” state. As charge sharing takes place between the bias states of the dummy cells and the shorted bitlines, an averaged reference voltage is produced which is substantially centered between the “0” or “1” states. A sense amplifier receives a sense signal from the target memory cell on an associated bitline, and the averaged reference voltage is received on another bitline input of the sense amplifier. Thus, a new ferroelectric memory structure provides a centered reference voltage and a simple sensing scheme for the accurate sensing of the logic state of an FeRAM 1T1C cell for a read operation.
摘要翻译：铁电存储器结构描述了用于FeRAM存储器件应用的铁电电容器阵列中的1T1C布置。器件结构为读取FeRAM阵列的目标存储单元的状态的读出放大器提供精确的参考电压和简单的感测方案。参考电路产生参考电压，其是在多个FeRAM虚拟单元之间共享的电荷的函数。多个FeRAM虚拟单元中的每个虚拟单元选择性地耦合到多个位线。参考电路中的短路晶体管将与所选择的目标存储器单元相邻的两个位线或两个位线条耦合。一个虚拟单元耦合到两个短路位线或位线条中的选择一个，另一个虚设单元耦合到两个短路位线或位线条中的另一个，其中至少一个虚设单元偏置为“0” “状态，并且至少一个其他虚拟单元被偏置到”1“状态。由于在虚设单元的偏置状态和短路位线之间发生电荷共享，产生基本上以“0”或“1”状态为中心的平均参考电压。感测放大器在相关联的位线上接收来自目标存储器单元的感测信号，并且平均参考电压在读出放大器的另一位线输入端上被接收。因此，新的铁电存储器结构提供了居中的参考电压和用于精确检测用于读取操作的FeRAM 1T1C单元的逻辑状态的简单感测方案。

4. 发明授权

US5793600A Method for forming high dielectric capacitor electrode structure and semiconductor memory devices 失效
标题翻译：高介电电容电极结构和半导体存储器件的形成方法
公开(公告)号：US5793600A
公开(公告)日：1998-08-11
申请号：US545980
申请日：1995-10-20
申请人： Yukio Fukuda , Katsuhiro Aoki , Akitoshi Nishimura , Ken Numata
发明人： Yukio Fukuda , Katsuhiro Aoki , Akitoshi Nishimura , Ken Numata
IPC分类号： H01L21/02 , H01G4/06 , H01G7/00
CPC分类号： H01L28/75 , H01L28/60 , H01L28/55 , Y10T29/435
摘要： A capacitor and electrode structure comprising a PZT ferroelectric layer 17 with a primary component (Pb) and secondary component (Ti), a lower electrode layer 16 formed on the underside of the ferroelectric layer and made up of a special element (Pt) and Ti, and compounds thereof, and a diffusion barrier layer 18 which is formed on the underside of the lower electrode layer and which functions as a diffusion barrier with respect to Pb. The capacitor and the electrode structure, which may be a component of a semiconductor memory device, suppress fluctuations in the composition of the ferroelectric layer in PZT, etc., so as to maintain the intended performance of the PZT ferroelectric layer, thereby simplifying and stabilizing film fabrication, and preventing the degradation of electrical characteristics and adverse effects on lower layers.
摘要翻译：包括具有主要组分（Pb）和次要组分（Ti）的PZT铁电层17的电容器和电极结构，形成在铁电层的下侧上并由特殊元素（Pt）和Ti构成的下电极层16 ，及其化合物，以及扩散阻挡层18，其形成在下电极层的下侧，并且用作相对于Pb的扩散阻挡层。可以是半导体存储器件的组件的电容器和电极结构抑制PZT等中的铁电层的组成的波动，以保持PZT铁电层的预期性能，从而简化和稳定薄膜制造，并防止电气特性的劣化和对较低层的不利影响。

5. 发明授权

US5776788A Method for forming a strong dielectric film by the sol-gel technique and a method for manufacturing a capacitor 失效
标题翻译：通过溶胶凝胶技术形成强电介质膜的方法和电容器的制造方法
公开(公告)号：US5776788A
公开(公告)日：1998-07-07
申请号：US601884
申请日：1996-02-15
申请人： Katsuhiro Aoki , Yukio Fukuda , Akitoshi Nishimura
发明人： Katsuhiro Aoki , Yukio Fukuda , Akitoshi Nishimura
IPC分类号： C01B13/32 , C04B35/49 , C23C18/12 , H01B3/00 , H01G4/12 , H01L21/314 , H01L21/316 , H01L21/70
CPC分类号： H01L21/31691 , C23C18/1216 , C23C18/1225 , C23C18/1254 , C23C18/1279 , H01L21/02197 , H01L21/02282 , H01L21/02337 , H01L21/02356
摘要： A method for forming a PZT strong dielectric film by the sol-gel technique, in which the thickness of the film is substantially no greater than 1000 .ANG.. In another aspect, the drying temperature of the raw material sol-gel solution for forming the PZT dielectric film is maintained within the range of 130.degree.-200.degree. C., and is particularly set lower than the boiling point of the stabilizer contained in the sol-gel raw material and higher than the boiling point of the solvent contained in the sol-gel raw material. As a result of performing the oxidative sintering treatment at a temperature at which perovskite crystals form, it becomes possible to readily form thin films exhibiting a (100) crystal orientation in particular. Additionally, completely crack-free thick films can be formed.
摘要翻译：通过溶胶 - 凝胶技术形成PZT强电介质膜的方法，其中膜的厚度基本上不大于1000。在另一方面，用于形成PZT电介质膜的原料溶胶 - 凝胶溶液的干燥温度保持在130℃-200℃的范围内，并且特别设定为低于所述稳定剂的沸点溶胶凝胶原料，高于溶胶凝胶原料中所含溶剂的沸点。作为在钙钛矿晶体形成的温度下进行氧化烧结处理的结果，可以容易地形成具有（100）晶体取向的薄膜。另外，可以形成完全无裂纹的厚膜。

6. 发明授权

US5508953A Capacitor, electrode structure, and semiconductor memory device 失效
标题翻译：电容器，电极结构和半导体存储器件
公开(公告)号：US5508953A
公开(公告)日：1996-04-16
申请号：US242924
申请日：1994-05-16
申请人： Yukio Fukuda , Katsuhiro Aoki , Akitoshi Nishimura , Ken Numata
发明人： Yukio Fukuda , Katsuhiro Aoki , Akitoshi Nishimura , Ken Numata
IPC分类号： H01L27/04 , H01L21/02 , H01L21/822 , H01L21/8242 , H01L21/8246 , H01L27/10 , H01L27/105 , H01L27/108 , G11C11/22
CPC分类号： H01L28/55 , H01L28/60 , H01L28/75
摘要： A capacitor and electrode structure comprising a PZT ferroelectric layer 17 with a primary component (Pb) and secondary component (Ti), a lower electrode layer 16 formed on the underside of the ferroelectric layer and made up of a special element (Pt) and Ti, and compounds thereof, and a diffusion barrier layer 18 which is formed on the underside of the lower electrode layer and which functions as a diffusion barrier with respect to Pb. The capacitor and the electrode structure, which may be a component of a semiconductor memory device, suppress fluctuations in the composition of the ferroelectric layer in PZT, etc., so as to maintain the intended performance of the PZT ferroelectric layer, thereby simplifying and stabilizing film fabrication, and preventing the degradation of electrical characteristics and adverse effects on lower layers.
摘要翻译：包括具有主要组分（Pb）和次要组分（Ti）的PZT铁电层17的电容器和电极结构，形成在铁电层的下侧上并由特殊元素（Pt）和Ti构成的下电极层16 ，及其化合物，以及扩散阻挡层18，其形成在下电极层的下侧，并且用作相对于Pb的扩散阻挡层。可以是半导体存储器件的组件的电容器和电极结构抑制PZT等中的铁电层的组成的波动，以保持PZT铁电层的预期性能，从而简化和稳定薄膜制造，并防止电气特性的劣化和对较低层的不利影响。

7. 发明授权

US06363002B1 Ferroelectric memory with bipolar drive pulses 有权
标题翻译：带双极驱动脉冲的铁电存储器
公开(公告)号：US06363002B1
公开(公告)日：2002-03-26
申请号：US09224616
申请日：1998-12-31
申请人： Akitoshi Nishimura , Katsuhiro Aoki
发明人： Akitoshi Nishimura , Katsuhiro Aoki
IPC分类号： G11C1122
CPC分类号： G11C11/22
摘要： An FeRAM in which sensing occurs without a dummy cell, using an unselected bitline as a reference. The read cycle includes two opposed pulses on the drive line: the first pulse provides a data-dependent signal out of the selected cell, and the second pulse restores the bit line to a level such that the DC bias voltage on an unselected bitline provides an optimal reference.
摘要翻译：在不使用虚拟单元的情况下，使用未选择的位线作为参考的FeRAM。读周期在驱动线上包括两个相对的脉冲：第一个脉冲从所选择的单元提供数据相关的信号，第二个脉冲将位线恢复到一个电平，使得未选择的位线上的直流偏置电压提供最佳参考。

8. 发明授权

US6033953A Method for manufacturing dielectric capacitor, dielectric memory device 失效
标题翻译：介质电容器的制造方法，介质存储器件
公开(公告)号：US6033953A
公开(公告)日：2000-03-07
申请号：US991132
申请日：1997-12-16
申请人： Katsuhiro Aoki , Yukio Fukuda , Ken Numata , Yasutoshi Okuno , Akitoshi Nishimura
发明人： Katsuhiro Aoki , Yukio Fukuda , Ken Numata , Yasutoshi Okuno , Akitoshi Nishimura
IPC分类号： H01G4/33 , H01L21/02 , H01L21/321 , H01L21/8242 , H01L21/8246 , H01L27/10 , H01L27/105 , H01L27/108
CPC分类号： H01L27/1085 , H01L28/60 , H01L21/32115
摘要： A dielectric capacitor is provided which has a reduced leakage current. The surface of a first electrode (38) of the capacitor is electropolished and a dielectric film (40) and a second electrode (37) are successively laminated on it. The convex parts pointed end (38a) existing on the surface of the first electrode is very finely polished uniformly by dissolving according to electropolishing, a spherical curved surface in which the radius of curvature has been enlarged is formed, and the surface of the first electrode is flattened. Therefore, concentration of electrolysis can be prevented during the operation at the interface of the first electrode and the dielectric film, and the leakage current can be reduced considerably.
摘要翻译：提供了具有减小的漏电流的介质电容器。对电容器的第一电极（38）的表面进行电解抛光，并在其上依次层压电介质膜（40）和第二电极（37）。存在于第一电极表面上的凸部尖端（38a）通过电解抛光溶解而形成非常细微的抛光，形成曲面半径扩大的球面曲面，第一电极的表面扁平化因此，在第一电极和电介质膜的界面的操作期间可以防止电解浓度，并且可以显着降低泄漏电流。

9. 发明授权

US5168340A Semiconductor integrated circuit device with guardring regions to prevent the formation of an MOS diode 失效
标题翻译：具有防护区域的半导体集成电路器件，以防止形成MOS二极管
公开(公告)号：US5168340A
公开(公告)日：1992-12-01
申请号：US596614
申请日：1990-10-12
申请人： Akitoshi Nishimura
发明人： Akitoshi Nishimura
IPC分类号： H01L29/06
CPC分类号： H01L29/0692
摘要： This invention relates to a semiconductor integrated circuit device wherein guardring regions are formed between a first element region and a second element region so as to surround the first element region, wherein gate electrodes are provided to cross the guardring regions, wherein the guardring regions are continuously formed even directly below the gate electrodes, and wherein an insulator film directly below the gate electrodes is relatively thick.
摘要翻译：本发明涉及一种半导体集成电路器件，其中防护区域形成在第一元件区域和第二元件区域之间以包围第一元件区域，其中设置栅电极以跨越防护区域，其中防护区域连续地甚至直接形成在栅极下方，并且其中在栅电极正下方的绝缘膜相对较厚。

10. 发明授权

US06342420B1 Hexagonally symmetric integrated circuit cell 有权
标题翻译：六边形对称集成电路单元
公开(公告)号：US06342420B1
公开(公告)日：2002-01-29
申请号：US09542002
申请日：2000-04-03
申请人： Akitoshi Nishimura , Yasutoshi Okuno , Rajesh Khamankar , Shane R. Palmer
发明人： Akitoshi Nishimura , Yasutoshi Okuno , Rajesh Khamankar , Shane R. Palmer
IPC分类号： H01L218242
CPC分类号： H01L27/10888 , H01L27/10805 , Y10S257/905
摘要： An apparatus and method for fabrication a hexagonally symmetric cell, (e.g., a dynamic random access memory cell (100)). The cell can comprise a bitline contact (38), storage node contacts (32) hexagonally surrounding the bitline contact (38), storage nodes (36) also surrounding the bitline contact (38), a wordline (30) portions of which form field effect transistor gates. Large distances between bitline contacts (38) and storage node contact (32) cause large problems during photolithography because dark areas are difficult to achieve when using Levenson Phaseshift. Because Levenson Phaseshift depends on wave cancellations between nearby features, commonly known as destructive interferences, the resultant printability of the pattern is largely a function of the symmetry and separation distances. When non-symmetries in the pattern occur, the result is weaker cancellations of fields (i.e. between features) and a large loss of image contrast and depth of focus during the printing step. The net result are defects, which increase device failure, can be significantly reduced by the geometry modifications disclosed herein.
摘要翻译：用于制造六边形对称单元（例如，动态随机存取存储单元（100））的装置和方法。电池可以包括位线触点（38），六边形围绕位线触点（38）的存储节点触点（32），也围绕位线触点（38）的存储节点（36），其中一部分形成字段效应晶体管栅极。位线触点（38）和存储节点触点（32）之间的大距离在光刻期间引起很大的问题，因为使用Levenson Phaseshift时很难实现暗区。因为Levenson Phaseshift取决于附近特征之间的波浪消除，通常被称为破坏性干扰，所以模式的最终可印刷性主要是对称性和分离距离的函数。当图案中的非对称性发生时，结果是在打印步骤期间，场的更弱的取消（即，特征之间）和图像对比度的大的损失和焦点的深度。最终结果是通过本文公开的几何修改可以显着地减少增加设备故障的缺陷。

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