会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 1. 发明授权
    • Fused proteins comprising glycoprotein gD of HSV-1 and LTB
    • 包含HSV-1和LTB的糖蛋白gD的融合蛋白
    • US5241053A
    • 1993-08-31
    • US577915
    • 1990-09-05
    • Yukio FujisawaShuji HinumaAki MayumiTatsuo Yamamoto
    • Yukio FujisawaShuji HinumaAki MayumiTatsuo Yamamoto
    • A61K39/00A61K47/48C07K14/035C07K14/245
    • C07K14/245A61K47/4833C07K14/005A61K39/00C07K2319/40C07K2319/55C12N2710/16622
    • Disclosed are (1) a fused protein comprising heat-labile enterotoxin B subunit and a protein heterologous to heat-labile enterotoxin, (2) a recombinant DNA containing a nucleotide sequence coding for the above fused protein, (3) a transformant harboring the above recombinant DNA, (4) a method for producing the fused protein which comprises cultivating the above transformant, producing and accumulating the above fused protein in a culture, and collecting the fused protein, and (5) a method for purifying a fused protein comprising a herpes simplex virus surface antigen and heat-labile enterotoxin B subunit, which comprises cultivating a transformant harboring a recombinant DNA containing a nucleotide sequence coding for the fused protein, producing an accumulating the fused protein in a culture, collecting the fused protein and subjecting the collected fused protein to purification processes comprising cationic exchange chromatography and gel permeation chromatography.
    • 公开了(1)包含热不稳定肠毒素B亚基和与热不稳定肠毒素异源的蛋白质的融合蛋白,(2)含有编码上述融合蛋白的核苷酸序列的重组DNA,(3)含有上述 重组DNA,(4)生产融合蛋白的方法,包括培养上述转化体,在培养物中产生和积累上述融合蛋白,并收集融合蛋白,和(5)纯化融合蛋白的方法, 单纯疱疹病毒表面抗原和热不稳定肠毒素B亚基,其包括培养含有编码融合蛋白的核苷酸序列的重组DNA的转化体,产生在培养物中积聚融合蛋白,收集融合蛋白并使收集的 融合蛋白与包含阳离子交换层析和凝胶渗透色谱的纯化方法。
    • 6. 发明授权
    • All digital switching regulator for use in power supplies, battery
chargers, and DC motor control circuits
    • 用于电源,电池充电器和直流电机控制电路的所有数字开关稳压器
    • US5675240A
    • 1997-10-07
    • US495391
    • 1995-06-28
    • Yukio FujisawaIsao Takinoue
    • Yukio FujisawaIsao Takinoue
    • H02P7/29G05F1/575H02M3/155H02M3/157G05F1/40
    • H02M3/157G05F1/575
    • A switching regulator is composed of digital circuits only. A switching regulator (30) comprises a driver (2) for directly controlling the operation of a switching transistor (1), and an OR gate (6) for determining the logic issued by the driver (2). An output terminal (Q) of an RS flip-flop (5) is connected to one input end of the OR gate (6), the output of a timer (40c) is applied to a set terminal (S) of the RS flip-flop (5), and the output of a comparator (4) is applied to a reset terminal (R1) through an OR gate (7). At a non-reverse input end of the comparator (4), a reference voltage (VE) is applied by a D/A convertor (40b), while a feedback voltage (VFB) is applied to a reverse input end. Accordingly, chopping of the switching transistor (1) is done on the basis of a rectangular pulse.
    • 开关稳压器仅由数字电路组成。 开关调节器(30)包括用于直接控制开关晶体管(1)的操作的驱动器(2)和用于确定由驱动器(2)发出的逻辑的或门(6)。 RS触发器(5)的输出端(Q)连接到或门(6)的一个输入端,定时器(40c)的输出被施加到RS翻转的设定端(S) (5),并且比较器(4)的输出通过或门(7)施加到复位端子(R1)。 在比较器(4)的非反相输入端,由D / A转换器(40b)施加参考电压(VE),而反馈电压(VFB)施加到反向输入端。 因此,开关晶体管(1)的斩波是基于矩形脉冲进行的。
    • 10. 发明授权
    • Address match determining device, communication control system, and address match determining method
    • 地址匹配确定装置,通信控制系统和地址匹配确定方法
    • US06314099B1
    • 2001-11-06
    • US09146044
    • 1998-09-02
    • Yukio FujisawaKazutoshi MiyamotoChristoph GottschalkHans-Michael Loch
    • Yukio FujisawaKazutoshi MiyamotoChristoph GottschalkHans-Michael Loch
    • H04L1256
    • H04L29/06H04L45/742H04L69/22
    • An address match determining device has an address filter memory (22) for storing a matrix or table having a plurality of elements each of which is a 1-bit address match determination data indicating whether or not a corresponding N-bit address code is available, and is distinguished by a pair of a first index composed of the m most significant or high-order m bits of the corresponding address code and a second index composed of the remaining lowest or low-order (N−m) bits of the corresponding address code. A received-address latch (21) extracts the high-order m bits and remaining low-order (N−m) bits from an address code latched thereinto. The device searches through the table for one 1-bit address match determination data specified by the first index composed of the extracted high-order m bits and the second index composed of the extracted low-order (N−m) bits, and then determines whether or not the latched address is available on the basis of the 1-bit address match determination data searched for.
    • 地址匹配确定装置具有用于存储具有多个元素的矩阵或表的地址过滤存储器(22),每个元素是表示对应的N位地址码是否可用的1位地址匹配确定数据, 并且由一对由相应地址码的m个最高有效位或高位m位组成的第一索引和由相应地址码的剩余最低位或低阶(Nm)位组成的第二索引来区分。 接收地址锁存器(21)从锁存在其中的地址码提取高阶m位和剩余低位(N-m)位。 设备通过表格搜索由提取的高阶m位组成的第一索引和由提取的低阶(Nm)位组成的第二索引指定的一个1位地址匹配确定数据,然后确定是否或 基于搜索到的1位地址匹配确定数据,不是锁存地址可用。