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1. 发明授权

US08027352B2 Gateway apparatus and data managing method 有权
标题翻译：网关设备和数据管理方法
公开(公告)号：US08027352B2
公开(公告)日：2011-09-27
申请号：US11976546
申请日：2007-10-25
申请人： Kaoru Noumi , Susumu Nishihashi , Tomoyuki Katou , Yukio Ishikawa , Yasuyuki Umezaki , Hidetaka Ebeshu , Shigeo Koide , Yukio Fujisawa , Hiroaki Shimauchi
发明人： Kaoru Noumi , Susumu Nishihashi , Tomoyuki Katou , Yukio Ishikawa , Yasuyuki Umezaki , Hidetaka Ebeshu , Shigeo Koide , Yukio Fujisawa , Hiroaki Shimauchi
IPC分类号： H04L12/66
CPC分类号： H04L47/10 , H04L12/40026 , H04L12/4625 , H04L43/106 , H04L47/283 , H04L47/31 , H04L47/32 , H04L49/206 , H04L49/30 , H04L49/351 , H04L2012/40215 , H04L2012/40273
摘要： A gateway apparatus for performing transfer control of frame data between a plurality of different communication channels is provided with a time stamp unit for adding time stamp information to received frame data and a data discarding unit for determining processing delay of the frame data or abnormality of the apparatus by referring to the time stamp information and for deleting the time stamp information added to the frame data at the time of sending the frame data.
摘要翻译：用于在多个不同的通信信道之间执行帧数据的传送控制的网关装置设置有用于将时间戳信息添加到接收到的帧数据的时间戳单元和用于确定帧数据的处理延迟或异常的数据丢弃单元通过参考时间戳信息和删除在发送帧数据时添加到帧数据的时间戳信息的装置。

2. 发明授权

US08265087B2 Gateway apparatus and data transfer control method 有权
标题翻译：网关设备和数据传输控制方法
公开(公告)号：US08265087B2
公开(公告)日：2012-09-11
申请号：US11976687
申请日：2007-10-26
申请人： Kaoru Noumi , Susumu Nishihashi , Tomoyuki Katou , Yukio Ishikawa , Yasuyuki Umezaki , Hidetaka Ebeshu , Shigeo Koide , Yukio Fujisawa , Hiroaki Shimauchi
发明人： Kaoru Noumi , Susumu Nishihashi , Tomoyuki Katou , Yukio Ishikawa , Yasuyuki Umezaki , Hidetaka Ebeshu , Shigeo Koide , Yukio Fujisawa , Hiroaki Shimauchi
IPC分类号： H04L12/28
CPC分类号： H04L12/66 , H04L12/4135 , H04L12/4625 , H04L2012/40215 , H04L2012/40273
摘要： A gateway apparatus for performing transfer control of frame data between communication channels includes a routing map that stores ID information about the frame data and information about a communication channel that uses the ID information, and a search engine unit that routes the frame data to a transfer destination on the basis of the ID information of the frame data received and the routing map. The search engine unit does not transfer the frame data to the transfer destination when the ID information about the frame data received is ID information that is not used in the communication channel through which the frame data is received.
摘要翻译：用于在通信信道之间执行帧数据的传输控制的网关装置包括存储关于帧数据的ID信息和关于使用该ID信息的通信信道的信息的路由图，以及将帧数据路由到传送的搜索引擎单元基于接收的帧数据的ID信息和路由图。当接收到的帧数据的ID信息是在接收帧数据的通信信道中未使用的ID信息时，搜索引擎单元不将帧数据传送到传送目的地。

3. 发明申请

US20080101394A1 Gateway apparatus and data transfer control method 有权
标题翻译：网关设备和数据传输控制方法
公开(公告)号：US20080101394A1
公开(公告)日：2008-05-01
申请号：US11976687
申请日：2007-10-26
申请人： Kaoru Noumi , Susumu Nishihashi , Tomoyuki Katou , Yukio Ishikawa , Yasuyuki Umezaki , Hidetaka Ebeshu , Shigeo Koide , Yukio Fujisawa , Hiroaki Shimauchi
发明人： Kaoru Noumi , Susumu Nishihashi , Tomoyuki Katou , Yukio Ishikawa , Yasuyuki Umezaki , Hidetaka Ebeshu , Shigeo Koide , Yukio Fujisawa , Hiroaki Shimauchi
IPC分类号： H04L12/28
CPC分类号： H04L12/66 , H04L12/4135 , H04L12/4625 , H04L2012/40215 , H04L2012/40273
摘要： A gateway apparatus for performing transfer control of frame data between communication channels includes a routing map that stores ID information about the frame data and information about a communication channel that uses the ID information, and a search engine unit that routes the frame data to a transfer destination on the basis of the ID information of the frame data received and the routing map. The search engine unit does not transfer the frame data to the transfer destination when the ID information about the frame data received is ID information that is not used in the communication channel through which the frame data is received.
摘要翻译：用于在通信信道之间执行帧数据的传输控制的网关装置包括存储关于帧数据的ID信息和关于使用该ID信息的通信信道的信息的路由图，以及将帧数据路由到传送的搜索引擎单元基于接收的帧数据的ID信息和路由图。当接收到的帧数据的ID信息是在接收帧数据的通信信道中未使用的ID信息时，搜索引擎单元不将帧数据传送到传送目的地。

4. 发明授权

US08122316B2 Error detector and error detection method 有权
标题翻译：误差检测器和误差检测方法
公开(公告)号：US08122316B2
公开(公告)日：2012-02-21
申请号：US11976544
申请日：2007-10-25
申请人： Kaoru Noumi , Susumu Nishihashi , Tomoyuki Katou , Yukio Ishikawa , Yasuyuki Umezaki , Hidetaka Ebeshu , Shigeo Koide , Yukio Fujisawa , Hiroaki Shimauchi
发明人： Kaoru Noumi , Susumu Nishihashi , Tomoyuki Katou , Yukio Ishikawa , Yasuyuki Umezaki , Hidetaka Ebeshu , Shigeo Koide , Yukio Fujisawa , Hiroaki Shimauchi
IPC分类号： H03M13/00 , G06F11/00 , G06F11/30 , G08C25/00 , H04L1/00
CPC分类号： H04L1/0045 , G06F11/10 , H04L1/0063 , H04L1/243 , H04L1/244
摘要： An error detector has a parity bit generator which generates error detection data for data strings sent from a CPU I/F to a memory, a parity checker which detects an error in the data strings output from the memory based on the error detection data, and a selector circuit which switchingly outputs the data from the parity bit generator and the data from a CPU which sends diagnostic data. While the selector circuit is switched to output the data from the CPU, based on the error detection data output from the selector circuit, the error detector conducts a failure diagnosis of error detection functions including at least one of the parity bit generator and the parity checker.
摘要翻译：错误检测器具有产生从CPU I / F向存储器发送的数据串的错误检测数据的奇偶校验位产生器，基于检错数据检测从存储器输出的数据串中的错误的奇偶检验器，以及选择器电路，其切换地输出来自奇偶位产生器的数据和来自发送诊断数据的CPU的数据。当选择器电路被切换以从CPU输出数据时，基于从选择器电路输出的错误检测数据，误差检测器进行包括奇偶位产生器和奇偶校验器中的至少一个的错误检测功能的故障诊断。

5. 发明申请

US20080101393A1 Gateway apparatus and data managing method 有权
标题翻译：网关设备和数据管理方法
公开(公告)号：US20080101393A1
公开(公告)日：2008-05-01
申请号：US11976546
申请日：2007-10-25
申请人： Kaoru Noumi , Susumu Nishihashi , Tomoyuki Katou , Yukio Ishikawa , Yasuyuki Umezaki , Hidetaka Ebeshu , Shigeo Koide , Yukio Fujisawa , Hiroaki Shimauchi
发明人： Kaoru Noumi , Susumu Nishihashi , Tomoyuki Katou , Yukio Ishikawa , Yasuyuki Umezaki , Hidetaka Ebeshu , Shigeo Koide , Yukio Fujisawa , Hiroaki Shimauchi
IPC分类号： H04L12/66
CPC分类号： H04L47/10 , H04L12/40026 , H04L12/4625 , H04L43/106 , H04L47/283 , H04L47/31 , H04L47/32 , H04L49/206 , H04L49/30 , H04L49/351 , H04L2012/40215 , H04L2012/40273
摘要： A gateway apparatus for performing transfer control of frame data between a plurality of different communication channels is provided with a time stamp unit for adding time stamp information to received frame data and a data discarding unit for determining processing delay of the frame data or abnormality of the apparatus by referring to the time stamp information and for deleting the time stamp information added to the frame data at the time of sending the frame data.
摘要翻译：用于在多个不同的通信信道之间执行帧数据的传送控制的网关装置设置有用于将时间戳信息添加到接收的帧数据的时间戳单元和用于确定帧数据的处理延迟或异常的数据丢弃单元通过参考时间戳信息和删除在发送帧数据时添加到帧数据的时间戳信息的装置。

6. 发明授权

US6026498A Clock signal generator circuit using a logical result of an output of a computer and a source clock to generate plurality of clock signals 失效
标题翻译：时钟信号发生器电路使用计数器和源时钟的输出的逻辑结果来产生多个时钟信号
公开(公告)号：US6026498A
公开(公告)日：2000-02-15
申请号：US448894
申请日：1995-05-24
申请人： Takeshi Fuse , Toshiyuki Igarashi , Masaaki Tani , Atsushi Fujita , Osamu Tago , Shigeo Koide , Takashi Sugimoto
发明人： Takeshi Fuse , Toshiyuki Igarashi , Masaaki Tani , Atsushi Fujita , Osamu Tago , Shigeo Koide , Takashi Sugimoto
IPC分类号： G06F1/04 , G06F1/06 , G06F1/08 , H03K5/15 , G06F13/00
CPC分类号： G06F1/08 , G06F1/06 , H03K5/15013
摘要： A clock signal generator circuit has a clock generator for generating clock signals to be supplied to a central processing unit and to functional blocks, and clock selectors. The clock generator divides the frequency of a source clock signal, to form a clock signal having an optional period. Namely, the clock generator suppresses at least one active or inactive state of the source clock signal, to generate a clock signal whose period is an integer multiple of that of the source clock signal. The clock selectors receive the clock signals generated by the clock generator and selectively supply them to the CPU and functional blocks. The clock signal generator circuit is capable of operating a microcontroller system at a required minimum speed, to optimize the power consumption of the system.
摘要翻译：时钟信号发生器电路具有用于产生要提供给中央处理单元和功能块的时钟信号的时钟发生器以及时钟选择器。时钟发生器分频源时钟信号的频率，以形成具有可选周期的时钟信号。也就是说，时钟发生器抑制源时钟信号的至少一个有效或无效状态，以产生其周期是源时钟信号的周期的整数倍的时钟信号。时钟选择器接收时钟发生器产生的时钟信号，并有选择地将它们提供给CPU和功能块。时钟信号发生器电路能够以所需的最小速度操作微控制器系统，以优化系统的功耗。

7. 发明申请

US20080141074A1 Error detector and error detection method 有权
标题翻译：误差检测器和误差检测方法
公开(公告)号：US20080141074A1
公开(公告)日：2008-06-12
申请号：US11976544
申请日：2007-10-25
申请人： Kaoru Noumi , Susumu Nishihashi , Tomoyuki Katou , Yukio Ishikawa , Yasuyuki Umezaki , Hidetaka Ebeshu , Shigeo Koide , Yukio Fujisawa , Hiroaki Shimauchi
发明人： Kaoru Noumi , Susumu Nishihashi , Tomoyuki Katou , Yukio Ishikawa , Yasuyuki Umezaki , Hidetaka Ebeshu , Shigeo Koide , Yukio Fujisawa , Hiroaki Shimauchi
IPC分类号： G06F11/00
CPC分类号： H04L1/0045 , G06F11/10 , H04L1/0063 , H04L1/243 , H04L1/244
摘要： An error detector has a parity bit generator which generates error detection data for data strings sent from a CPU I/F to a memory, a parity checker which detects an error in the data strings output from the memory based on the error detection data, and a selector circuit which switchingly outputs the data from the parity bit generator and the data from a CPU which sends diagnostic data. While the selector circuit is switched to output the data from the CPU, based on the error detection data output from the selector circuit, the error detector conducts a failure diagnosis of error detection functions including at least one of the parity bit generator and the parity checker.
摘要翻译：错误检测器具有产生从CPU I / F向存储器发送的数据串的错误检测数据的奇偶校验位产生器，基于检错数据检测从存储器输出的数据串中的错误的奇偶检验器，以及选择器电路，其切换地输出来自奇偶位产生器的数据和来自发送诊断数据的CPU的数据。当选择器电路被切换以从CPU输出数据时，基于从选择器电路输出的错误检测数据，误差检测器进行包括奇偶位产生器和奇偶校验器中的至少一个的错误检测功能的故障诊断。

8. 发明授权

US4352178A Cartridge equalizer 失效
标题翻译：墨盒均衡器
公开(公告)号：US4352178A
公开(公告)日：1982-09-28
申请号：US149831
申请日：1980-05-14
申请人： Masaki Kitamura , Naoki Saisu , Shigeo Koide
发明人： Masaki Kitamura , Naoki Saisu , Shigeo Koide
IPC分类号： G11B3/14 , G11B3/16
CPC分类号： G11B3/14
摘要： A cartridge equalizer for obtaining excellent sound quality following the original sound with high fidelity by minimizing the positional shift of the cantilever fulcrum of a cartridge by mounting the cartridge equalizer to a portion near the cartridge of the tone arm of a record player and providing a well-balanced, suitable amount of weight. The cartridge equalizer includes a ring-shaped crossing rod made of a light alloy or the like having respective counterweights mounted at each end of the crossing rod, and a ring-shaped fitting positioned at the central portion of the crossing rod for fastening the cartridge equalizer to the tone arm.
摘要翻译：一种盒式平衡器，用于通过将盒式平衡器安装到记录播放器的音调臂的附近的部分的最小化盒的悬臂支点的位置偏移来获得具有高保真度的原始声音之后的优良音质，并提供一个井平衡，适量的重量。盒式均衡器包括由轻合金等形成的环形交叉杆，其具有安装在交叉杆的每个端部处的各自的配重，以及位于交叉杆的中心部分处的环形配件，用于紧固盒均衡器到音调臂。

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