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    • 6. 发明授权
    • Cache system with limited number of tag memory accesses
    • 具有有限数量的标签存储器访问的缓存系统
    • US06775741B2
    • 2004-08-10
    • US09768348
    • 2001-01-25
    • Hidetaka EbeshuHideaki Tomatsuri
    • Hidetaka EbeshuHideaki Tomatsuri
    • G06F1200
    • G06F12/0882G06F2212/1028Y02D10/13
    • The present invention is a cache system comprising a data memory for storing data in an external memory, and a tag memory for storing address information for data held in the data memory and a valid data bit indicating whether data controlled by the address information is valid; wherein the address information in the tag memory commonly controls a plurality of data items with consecutive addresses; wherein reading from tag memory is prohibited in a case where an address to be accessed corresponds to data controlled by address information in tag memory that matches a preceding address to be accessed; and wherein tag memory is read and a cache hit determination is performed in a case where the address to be accessed corresponds to data controlled by address information in tag memory that does not match the preceding address to be accessed.
    • 本发明是一种缓存系统,包括用于在外部存储器中存储数据的数据存储器和用于存储数据存储器中保存的数据的地址信息的标签存储器和指示由地址信息控制的数据是否有效的有效数据位; 其中,所述标签存储器中的地址信息共同地控制具有连续地址的多个数据项; 在要访问的地址对应于标签存储器中与要访问的先前地址匹配的地址信息控制的数据的情况下,禁止从标签存储器读取; 并且其中标签存储器被读取,并且在要访问的地址对应于标签存储器中与要访问的前一个地址不匹配的地址信息控制的数据的情况下执行高速缓存命中确定。