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1. 发明授权

US08122316B2 Error detector and error detection method 有权
标题翻译：误差检测器和误差检测方法
公开(公告)号：US08122316B2
公开(公告)日：2012-02-21
申请号：US11976544
申请日：2007-10-25
申请人： Kaoru Noumi , Susumu Nishihashi , Tomoyuki Katou , Yukio Ishikawa , Yasuyuki Umezaki , Hidetaka Ebeshu , Shigeo Koide , Yukio Fujisawa , Hiroaki Shimauchi
发明人： Kaoru Noumi , Susumu Nishihashi , Tomoyuki Katou , Yukio Ishikawa , Yasuyuki Umezaki , Hidetaka Ebeshu , Shigeo Koide , Yukio Fujisawa , Hiroaki Shimauchi
IPC分类号： H03M13/00 , G06F11/00 , G06F11/30 , G08C25/00 , H04L1/00
CPC分类号： H04L1/0045 , G06F11/10 , H04L1/0063 , H04L1/243 , H04L1/244
摘要： An error detector has a parity bit generator which generates error detection data for data strings sent from a CPU I/F to a memory, a parity checker which detects an error in the data strings output from the memory based on the error detection data, and a selector circuit which switchingly outputs the data from the parity bit generator and the data from a CPU which sends diagnostic data. While the selector circuit is switched to output the data from the CPU, based on the error detection data output from the selector circuit, the error detector conducts a failure diagnosis of error detection functions including at least one of the parity bit generator and the parity checker.
摘要翻译：错误检测器具有产生从CPU I / F向存储器发送的数据串的错误检测数据的奇偶校验位产生器，基于检错数据检测从存储器输出的数据串中的错误的奇偶检验器，以及选择器电路，其切换地输出来自奇偶位产生器的数据和来自发送诊断数据的CPU的数据。当选择器电路被切换以从CPU输出数据时，基于从选择器电路输出的错误检测数据，误差检测器进行包括奇偶位产生器和奇偶校验器中的至少一个的错误检测功能的故障诊断。

2. 发明授权

US07787479B2 Gateway apparatus and routing method 有权
标题翻译：网关设备和路由方法
公开(公告)号：US07787479B2
公开(公告)日：2010-08-31
申请号：US11412048
申请日：2006-04-27
申请人： Tomohiro Matsuo , Tsuyoshi Takatori , Kaoru Noumi , Susumu Nishihashi , Tomohide Kasame , Yukio Ishikawa , Junji Takahashi , Yasuyuki Umezaki , Akiko Furuya , Nobuaki Kawasoe , Naoto Shimoji , Masayoshi Kusumoto
发明人： Tomohiro Matsuo , Tsuyoshi Takatori , Kaoru Noumi , Susumu Nishihashi , Tomohide Kasame , Yukio Ishikawa , Junji Takahashi , Yasuyuki Umezaki , Akiko Furuya , Nobuaki Kawasoe , Naoto Shimoji , Masayoshi Kusumoto
IPC分类号： H04L12/56
CPC分类号： H04L49/555 , H04L12/4135 , H04L12/4625 , H04L45/00 , H04L47/10 , H04L49/254 , H04L49/501 , H04L49/90 , H04L49/901 , H04L49/9078 , H04L2012/40215
摘要： There is provided a gateway apparatus that controls a forwarding process of frame data between multiple communication channels, said gateway apparatus including a search engine that is respectively provided for each of the multiple communication channels to route the frame data between the multiple communication channels, and a first storage portion that is respectively provided for each of the multiple communication channels to temporarily stores the frame data routed.
摘要翻译：提供了一种网关装置，其控制多个通信信道之间的帧数据的转发处理，所述网关装置包括分别为多个通信信道中的每一个提供用于在多个通信信道之间路由帧数据的搜索引擎，以及第一存储部分，其分别为多个通信信道中的每一个提供临时存储路由的帧数据。

3. 发明申请

US20080101393A1 Gateway apparatus and data managing method 有权
标题翻译：网关设备和数据管理方法
公开(公告)号：US20080101393A1
公开(公告)日：2008-05-01
申请号：US11976546
申请日：2007-10-25
申请人： Kaoru Noumi , Susumu Nishihashi , Tomoyuki Katou , Yukio Ishikawa , Yasuyuki Umezaki , Hidetaka Ebeshu , Shigeo Koide , Yukio Fujisawa , Hiroaki Shimauchi
发明人： Kaoru Noumi , Susumu Nishihashi , Tomoyuki Katou , Yukio Ishikawa , Yasuyuki Umezaki , Hidetaka Ebeshu , Shigeo Koide , Yukio Fujisawa , Hiroaki Shimauchi
IPC分类号： H04L12/66
CPC分类号： H04L47/10 , H04L12/40026 , H04L12/4625 , H04L43/106 , H04L47/283 , H04L47/31 , H04L47/32 , H04L49/206 , H04L49/30 , H04L49/351 , H04L2012/40215 , H04L2012/40273
摘要： A gateway apparatus for performing transfer control of frame data between a plurality of different communication channels is provided with a time stamp unit for adding time stamp information to received frame data and a data discarding unit for determining processing delay of the frame data or abnormality of the apparatus by referring to the time stamp information and for deleting the time stamp information added to the frame data at the time of sending the frame data.
摘要翻译：用于在多个不同的通信信道之间执行帧数据的传送控制的网关装置设置有用于将时间戳信息添加到接收的帧数据的时间戳单元和用于确定帧数据的处理延迟或异常的数据丢弃单元通过参考时间戳信息和删除在发送帧数据时添加到帧数据的时间戳信息的装置。

4. 发明授权

US06799267B2 Packet processor 失效
标题翻译：分组处理器
公开(公告)号：US06799267B2
公开(公告)日：2004-09-28
申请号：US09742939
申请日：2000-12-20
申请人： Yuji Kojima , Tetsumei Tsuruoka , Kenichi Abiru , Yasuyuki Umezaki , Yoshitomo Shimozono
发明人： Yuji Kojima , Tetsumei Tsuruoka , Kenichi Abiru , Yasuyuki Umezaki , Yoshitomo Shimozono
IPC分类号： G06F9302
CPC分类号： G06F9/3885 , G06F9/30018 , G06F9/30032
摘要： A packet processor having a general-purpose arithmetic operator and another dedicated circuit, which extracts a particular field from the general-purpose register as object field, on which the predetermined general-purpose arithmetic operation is to be performed by the general-purpose arithmetic operator and writes a result of the arithmetic operation by the general-purpose arithmetic operator into the general-purpose register as updated information of the particular field. Based on the extraction and write process of the packet field designated by software (instructions), the packet processor realizes high flexibility and high speed processing.
摘要翻译：具有通用算术运算器和另一专用电路的分组处理器，其从通用寄存器中提取特定字段作为对象字段，由通用算术运算符执行预定的通用算术运算并将通用算术运算器的算术运算结果写入通用寄存器作为特定字段的更新信息。基于由软件（指令）指定的分组字段的提取和写入过程，分组处理器实现高灵活性和高速处理。

5. 发明授权

US06654823B2 Packet-data processing apparatus 失效
标题翻译：分组数据处理装置
公开(公告)号：US06654823B2
公开(公告)日：2003-11-25
申请号：US09818354
申请日：2001-03-27
申请人： Satoshi Soejima , Yuji Kojima , Yasuyuki Umezaki , Tetsumei Tsuruoka , Yoshitomo Shimozono
发明人： Satoshi Soejima , Yuji Kojima , Yasuyuki Umezaki , Tetsumei Tsuruoka , Yoshitomo Shimozono
IPC分类号： G06F300
CPC分类号： H04L12/4633
摘要： A packet-data-processing apparatus includes a first data-processing unit for computing information on a processing count; a memory; a second data-processing-unit for processing the input packet and storing first results in the memory; an access mechanism unit for reading out one of the first results written into the memory least recently from the memory at a request for a read operation and deleting the result of processing read out from the memory; a third data-processing unit for making the request for a read operation and carrying out processing based on the first result read out by the access control unit at the request and an input packet associated with the result of processing; and fourth data-processing unit constituting pipeline data-processing mechanism with the first and third data-processing unit.
摘要翻译：分组数据处理装置包括用于计算关于处理计数的信息的第一数据处理单元; 记忆第二数据处理单元，用于处理输入分组并将第一结果存储在存储器中; 访问机构单元，用于在请求读取操作时从存储器中最少读出写入存储器的第一结果中的一个，并从存储器中删除从该存储器读出的处理结果; 第三数据处理单元，用于基于由访问控制单元根据请求读出的第一结果和与处理结果相关联的输入分组进行读操作请求和执行处理; 以及与第一和第三数据处理单元构成流水线数据处理机构的第四数据处理单元。

6. 发明授权

US08027352B2 Gateway apparatus and data managing method 有权
标题翻译：网关设备和数据管理方法
公开(公告)号：US08027352B2
公开(公告)日：2011-09-27
申请号：US11976546
申请日：2007-10-25
申请人： Kaoru Noumi , Susumu Nishihashi , Tomoyuki Katou , Yukio Ishikawa , Yasuyuki Umezaki , Hidetaka Ebeshu , Shigeo Koide , Yukio Fujisawa , Hiroaki Shimauchi
发明人： Kaoru Noumi , Susumu Nishihashi , Tomoyuki Katou , Yukio Ishikawa , Yasuyuki Umezaki , Hidetaka Ebeshu , Shigeo Koide , Yukio Fujisawa , Hiroaki Shimauchi
IPC分类号： H04L12/66
CPC分类号： H04L47/10 , H04L12/40026 , H04L12/4625 , H04L43/106 , H04L47/283 , H04L47/31 , H04L47/32 , H04L49/206 , H04L49/30 , H04L49/351 , H04L2012/40215 , H04L2012/40273
摘要： A gateway apparatus for performing transfer control of frame data between a plurality of different communication channels is provided with a time stamp unit for adding time stamp information to received frame data and a data discarding unit for determining processing delay of the frame data or abnormality of the apparatus by referring to the time stamp information and for deleting the time stamp information added to the frame data at the time of sending the frame data.
摘要翻译：用于在多个不同的通信信道之间执行帧数据的传送控制的网关装置设置有用于将时间戳信息添加到接收到的帧数据的时间戳单元和用于确定帧数据的处理延迟或异常的数据丢弃单元通过参考时间戳信息和删除在发送帧数据时添加到帧数据的时间戳信息的装置。

7. 发明授权

US08812288B2 Speed converting apparatus with load controlling function and information processing system 有权
标题翻译：具有负载控制功能和信息处理系统的速度转换装置
公开(公告)号：US08812288B2
公开(公告)日：2014-08-19
申请号：US11153419
申请日：2005-06-16
申请人： Minoru Kawarabayashi , Takayuki Shimamura , Tatekuni Onoue , Yasuyuki Umezaki
发明人： Minoru Kawarabayashi , Takayuki Shimamura , Tatekuni Onoue , Yasuyuki Umezaki
IPC分类号： G06F9/455
CPC分类号： G06F11/261
摘要： A speed converting apparatus with a load controlling function comprises a first interface unit operating for an emulation device according to a system clock of the emulation device, a second interface unit operating for an arithmetic unit according to a system clock of the arithmetic unit, and a load controlling unit controlling at least either a load of a request outputted to the emulation device on the emulation device or a load of a request outputted to the arithmetic unit on the arithmetic unit. In performance verification or connection verification of a target to be verified, the speed converting apparatus can vary a load of a request issued to the target to be verified on the target or a load issued to a verification device on the verification device, while absorbing a difference in operation speed between the target to be verified and the verification device.
摘要翻译：具有负载控制功能的速度转换装置包括根据仿真装置的系统时钟为仿真装置操作的第一接口单元，根据运算单元的系统时钟对运算单元运行的第二接口单元，以及负载控制单元至少控制在仿真装置上输出到仿真装置的请求的负载或者在运算单元上输出到运算单元的请求的负载。在要验证的目标的性能验证或连接验证中，速度转换装置可以在发送给目标上的目标的请求的负载或发送给验证装置上的验证装置的负载上，同时吸收待验证目标与验证装置之间的运行速度差。

8. 发明申请

US20090222597A1 DATA TRANSFER DEVICE 审中-公开
标题翻译：数据传输设备
公开(公告)号：US20090222597A1
公开(公告)日：2009-09-03
申请号：US12238820
申请日：2008-09-26
申请人： Yasuyuki UMEZAKI , Nobuaki KAWASOE , Hidetaka EBESHU
发明人： Yasuyuki UMEZAKI , Nobuaki KAWASOE , Hidetaka EBESHU
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： A data transfer device for storing only transfer data for which updating is necessary in the storage unit of a transfer source, transferring the transfer data by a transfer control unit, temporarily storing the transfer data in a register provided in a transfer destination circuit, transferring the transfer data stored in the register to the discontinuous storage area of the transfer destination circuit according to the map information of a map register, and transferring data for which updating is necessary to the transfer destination circuit.
摘要翻译：一种数据传送装置，用于仅存储传送源的存储单元中需要更新的传送数据，由传送控制单元传送传送数据，将传送数据临时存储在设置在传送目的地电路中的寄存器中，传送根据地图寄存器的地图信息将存储在寄存器中的数据传送到传送目的地电路的不连续存储区域，并将需要更新的数据传送给传送目的地电路。

9. 发明申请

US20080141074A1 Error detector and error detection method 有权
标题翻译：误差检测器和误差检测方法
公开(公告)号：US20080141074A1
公开(公告)日：2008-06-12
申请号：US11976544
申请日：2007-10-25
申请人： Kaoru Noumi , Susumu Nishihashi , Tomoyuki Katou , Yukio Ishikawa , Yasuyuki Umezaki , Hidetaka Ebeshu , Shigeo Koide , Yukio Fujisawa , Hiroaki Shimauchi
发明人： Kaoru Noumi , Susumu Nishihashi , Tomoyuki Katou , Yukio Ishikawa , Yasuyuki Umezaki , Hidetaka Ebeshu , Shigeo Koide , Yukio Fujisawa , Hiroaki Shimauchi
IPC分类号： G06F11/00
CPC分类号： H04L1/0045 , G06F11/10 , H04L1/0063 , H04L1/243 , H04L1/244
摘要： An error detector has a parity bit generator which generates error detection data for data strings sent from a CPU I/F to a memory, a parity checker which detects an error in the data strings output from the memory based on the error detection data, and a selector circuit which switchingly outputs the data from the parity bit generator and the data from a CPU which sends diagnostic data. While the selector circuit is switched to output the data from the CPU, based on the error detection data output from the selector circuit, the error detector conducts a failure diagnosis of error detection functions including at least one of the parity bit generator and the parity checker.
摘要翻译：错误检测器具有产生从CPU I / F向存储器发送的数据串的错误检测数据的奇偶校验位产生器，基于检错数据检测从存储器输出的数据串中的错误的奇偶检验器，以及选择器电路，其切换地输出来自奇偶位产生器的数据和来自发送诊断数据的CPU的数据。当选择器电路被切换以从CPU输出数据时，基于从选择器电路输出的错误检测数据，误差检测器进行包括奇偶位产生器和奇偶校验器中的至少一个的错误检测功能的故障诊断。

10. 发明申请

US20060271694A1 Gateway apparatus and routing method 有权
标题翻译：网关设备和路由方法
公开(公告)号：US20060271694A1
公开(公告)日：2006-11-30
申请号：US11412048
申请日：2006-04-27
申请人： Tomohiro Matsuo , Tsuyoshi Takatori , Kaoru Noumi , Susumu Nishihashi , Tomohide Kasame , Yukio Ishikawa , Junji Takahashi , Yasuyuki Umezaki , Akiko Furuya , Nobuaki Kawasoe , Naoto Shimoji , Masayoshi Kusumoto
发明人： Tomohiro Matsuo , Tsuyoshi Takatori , Kaoru Noumi , Susumu Nishihashi , Tomohide Kasame , Yukio Ishikawa , Junji Takahashi , Yasuyuki Umezaki , Akiko Furuya , Nobuaki Kawasoe , Naoto Shimoji , Masayoshi Kusumoto
IPC分类号： G06F15/16
CPC分类号： H04L49/555 , H04L12/4135 , H04L12/4625 , H04L45/00 , H04L47/10 , H04L49/254 , H04L49/501 , H04L49/90 , H04L49/901 , H04L49/9078 , H04L2012/40215
摘要： There is provided a gateway apparatus that controls a forwarding process of frame data between multiple communication channels, said gateway apparatus including a search engine that is respectively provided for each of the multiple communication channels to route the frame data between the multiple communication channels, and a first storage portion that is respectively provided for each of the multiple communication channels to temporarily stores the frame data routed.
摘要翻译：提供了一种网关装置，其控制多个通信信道之间的帧数据的转发处理，所述网关装置包括分别为多个通信信道中的每一个提供用于在多个通信信道之间路由帧数据的搜索引擎，以及第一存储部分，其分别为多个通信信道中的每一个提供临时存储路由的帧数据。

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