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1. 发明申请

US20110213946A1 PARALLEL COMPUTING SYSTEM AND COMMUNICATION CONTROL PROGRAM 审中-公开
标题翻译：并行计算系统和通信控制程序
公开(公告)号：US20110213946A1
公开(公告)日：2011-09-01
申请号：US12872338
申请日：2010-08-31
申请人： Yuichiro Ajima , Toshiyuki Shimizu , Hiroaki Ishihata
发明人： Yuichiro Ajima , Toshiyuki Shimizu , Hiroaki Ishihata
IPC分类号： G06F15/80 , G06F9/02
CPC分类号： G06F15/803
摘要： A parallel computing system includes a plurality of processors multi-dimensionally commented by an interconnection network, wherein each of the processors in the parallel computing system determines, in dimensional order, communication channels to other processors in the interconnection network, each of the processors sets, as relative coordinates of destination processors with respect to the plurality of processors in data communications performed at a same timing, relative coordinates common to all of the processors, and each of the processors performs data communications with destination processors having the set relative coordinates.
摘要翻译：并行计算系统包括由互连网络多维注释的多个处理器，其中并行计算系统中的每个处理器以尺寸顺序确定到互连网络中的其他处理器的通信信道，每个处理器集合，作为在相同定时执行的数据通信中的目标处理器相对于多个处理器的相对坐标，所有处理器共同的相对坐标，并且每个处理器执行与具有设定的相对坐标的目标处理器的数据通信。

2. 发明授权

US10430375B2 Parallel computing system and communication control program 有权
公开(公告)号：US10430375B2
公开(公告)日：2019-10-01
申请号：US12872338
申请日：2010-08-31
申请人： Yuichiro Ajima , Toshiyuki Shimizu , Hiroaki Ishihata
发明人： Yuichiro Ajima , Toshiyuki Shimizu , Hiroaki Ishihata
IPC分类号： G06F15/80
摘要： A parallel computing system includes a plurality of processors multi-dimensionally commented by an interconnection network, wherein each of the processors in the parallel computing system determines, in dimensional order, communication channels to other processors in the interconnection network, each of the processors sets, as relative coordinates of destination processors with respect to the plurality of processors in data communications performed at a same timing, relative coordinates common to all of the processors, and each of the processors performs data communications with destination processors having the set relative coordinates.

3. 发明授权

US5765187A Control system for a ring buffer which prevents overrunning and underrunning 失效
标题翻译：环形缓冲器的控制系统，可防止超速和欠载
公开(公告)号：US5765187A
公开(公告)日：1998-06-09
申请号：US844852
申请日：1997-04-22
申请人： Toshiyuki Shimizu , Takeshi Horie , Hiroaki Ishihata
发明人： Toshiyuki Shimizu , Takeshi Horie , Hiroaki Ishihata
IPC分类号： G06F13/38 , G06F5/06 , G06F5/10 , G06F5/14 , G06F13/00
CPC分类号： G06F5/14 , H04L49/90 , H04L49/901 , H04L49/9031 , H04L49/9047 , H04L49/9057
摘要： A receiving buffer control system comprises a memory having a buffer area serving as a receiving buffer, data being applied to the memory via a bus, a write pointer indicating a write address of the buffer area, and a read pointer indicating a read address of the buffer area. An overrun/underrun detection circuit detects a situation in which an overrun or an underrun will occur in the buffer area in response to the write address indicated by the write pointer and the read address indicated by the read pointer. A control part disables the data from being written into and read out from the buffer area when the overrun/underrun detection circuit detects the situation.
摘要翻译：接收缓冲器控制系统包括具有用作接收缓冲器的缓冲区的存储器，经由总线被施加到存储器的数据，指示缓冲区的写入地址的写指针，以及指示读取地址的读指针缓冲区。溢出/欠载检测电路响应于由写指针指示的写地址和读指针指示的读地址，检测缓冲区内发生溢出或欠载的情况。当超限/欠载检测电路检测到这种情况时，控制部分禁止数据被写入缓冲区并从缓冲区读出。

4. 发明授权

US6055559A Process switch control apparatus and a process control method 失效
标题翻译：过程开关控制装置和过程控制方法
公开(公告)号：US6055559A
公开(公告)日：2000-04-25
申请号：US710552
申请日：1996-09-19
申请人： Toshiyuki Shimizu , Hiroaki Ishihata
发明人： Toshiyuki Shimizu , Hiroaki Ishihata
IPC分类号： G06F9/46 , G06F9/48
CPC分类号： G06F9/4812 , G06F9/54
摘要： A status management unit manages a free status capable of invoking a process switch and a critical status. When a process currently being executed is in an input/output process or in a critical status during a message communication, a switch control means controls a control signal for a process switch, such that a process switch does not take place.
摘要翻译：状态管理单元管理能够调用进程切换和关键状态的空闲状态。当正在执行的处理在消息通信期间处于输入/输出处理或处于关键状态时，开关控制装置控制用于处理开关的控制信号，使得处理开关不发生。

5. 发明授权

US5832215A Data gathering/scattering system for a plurality of processors in a parallel computer 失效
标题翻译：用于并行计算机中的多个处理器的数据收集/散射系统
公开(公告)号：US5832215A
公开(公告)日：1998-11-03
申请号：US727932
申请日：1991-07-10
申请人： Sadayuki Kato , Hiroaki Ishihata , Takeshi Horie , Satoshi Inano , Toshiyuki Shimizu
发明人： Sadayuki Kato , Hiroaki Ishihata , Takeshi Horie , Satoshi Inano , Toshiyuki Shimizu
IPC分类号： G06F15/173 , G06F15/163
CPC分类号： G06F15/17393
摘要： In a data gathering/scattering system having a data gathering system and a data scattering system in a parallel computer constituted by a plurality of processors connected in parallel through a common bus or hierarchical common buses, the data gathering/scattering system includes: one processor having a buffer for temporarily storing data gathered from or transmitted to other processors, a three-state buffer for transmitting data from the buffer to the common bus, and a switching unit for switching a connection between a transmission and a reception to form the data gathering system or the data scattering system; each of the other processors having a buffer for temporarily storing data to be transferred or data to be received, a transfer control unit for controlling data transmissions from the buffer to the common bus, a reception control unit for selecting the reception data from among all data on the common bus, a three-state buffer for transmitting data from the buffer to the common bus, and a switching unit for switching a connection between a transmission and a reception to form the data gathering system or the data scattering system, and an AND circuit for obtaining a coincidence of a data transmission or data reception among the processors, and for sending a command for a data transmission or data reception to other processors.
摘要翻译：在具有数据采集系统和数据散布系统的数据采集/散射系统中，数据采集/散射系统包括：一个处理器，具有：用于临时存储从其他处理器收集或发送到其他处理器的数据的缓冲器，用于从缓冲器向公共总线发送数据的三态缓冲器，以及用于切换发送和接收之间的连接以形成数据收集系统的切换单元或数据散射系统; 每个其他处理器具有用于临时存储要传送的数据的缓冲器或要接收的数据;传输控制单元，用于控制从缓冲器到公共总线的数据传输;接收控制单元，用于从所有数据中选择接收数据在公共总线上，用于将数据从缓冲器发送到公共总线的三态缓冲器，以及用于切换发送和接收之间的连接以形成数据收集系统或数据散射系统的切换单元，以及AND 用于获得处理器之间的数据传输或数据接收的一致性，并且用于向其他处理器发送用于数据传输或数据接收的命令。

6. 发明授权

US5742843A Control system for access between processing elements in a parallel computer 失效
标题翻译：用于在并行计算机中的处理元件之间进行访问的控制系统
公开(公告)号：US5742843A
公开(公告)日：1998-04-21
申请号：US503916
申请日：1995-07-19
申请人： Yoichi Koyanagi , Osamu Shiraki , Takeshi Horie , Toshiyuki Shimizu , Hiroaki Ishihata
发明人： Yoichi Koyanagi , Osamu Shiraki , Takeshi Horie , Toshiyuki Shimizu , Hiroaki Ishihata
IPC分类号： G06F15/17 , G06F15/80
CPC分类号： G06F15/17
摘要： When the processor writes a command data string into an address of the command entry area, a corresponding command is created by a bus interface. If an address output by the processor corresponds to a distributed shared memory area, the bus interface creates a remote access command. The send controller constructs a message based on the command created by the bus interface. This message is sent either to an interconnection network, or to a receive controller. The receive controller receives the message and interprets it. An address output by the processor is detected by a cache area access unit, and the cache area in the memory is accessed. When the processor receives an interrupt request while waiting for a response message to a remote read request, an deadlock control unit detects an abnormal end of the remote read request that the remote read has ended in an error, and, controls the processor to process the interrupt request with priority.
摘要翻译：当处理器将命令数据串写入命令输入区域的地址时，由总线接口创建相应的命令。如果处理器输出的地址对应于分布式共享存储器区域，则总线接口创建远程访问命令。发送控制器根据总线接口创建的命令构建消息。该消息被发送到互连网络或发送到接收控制器。接收控制器接收消息并对其进行解释。由处理器输出的地址由高速缓存区域访问单元检测，存储器中的高速缓存区域被访问。当处理器在等待对远程读取请求的响应消息的同时接收到中断请求时，死锁控制单元检测到远程读取已经结束的远程读取请求的异常结束，并且控制处理器中断请求优先。

7. 发明授权

US5935204A System for a multi-processor system wherein each processor transfers a data block from cache if a cache hit and from main memory only if cache miss 失效
标题翻译：用于多处理器系统的系统，其中如果缓存命中并且仅当高速缓存未命中时，每个处理器从高速缓存传送数据块
公开(公告)号：US5935204A
公开(公告)日：1999-08-10
申请号：US852026
申请日：1997-05-06
申请人： Toshiyuki Shimizu , Hiroaki Ishihata
发明人： Toshiyuki Shimizu , Hiroaki Ishihata
IPC分类号： G06F12/08 , G06F15/16 , G06F15/173 , G06F13/14
CPC分类号： G06F12/0813 , G06F12/0804 , G06F15/173
摘要： Data transmission control apparatus which controls data transmission between processing systems via a transmission line, each processing system including a memory system consisting of a main memory and a cache memory. The apparatus addresses data in the main memory by a memory address and gives an instruction to transmit the addressed data; determines whether or not the addressed data is in the cache memory; provides a match signal when the data is in the cache memory; reads the addressed data from the cache memory when instructed by the instruction and when a ready signal and the match signal are provided, and, otherwise reads the addressed data from the main memory; writes the data read into a port; transmits the data written in the port to the another processing system connected to the transmission line; and provides the ready signal when the port is ready to receive additional data.
摘要翻译：数据传输控制装置，其通过传输线控制处理系统之间的数据传输，每个处理系统包括由主存储器和高速缓冲存储器组成的存储器系统。该装置通过存储器地址对主存储器中的数据进行寻址，并给出发送寻址数据的指令; 确定所寻址的数据是否在高速缓冲存储器中; 当数据在高速缓冲存储器中时提供匹配信号; 当指令指示时，当提供就绪信号和匹配信号时，从高速缓冲存储器读取寻址数据，否则从主存储器读取寻址数据; 将读取的数据写入端口; 将写入端口的数据发送到连接到传输线的另一处理系统; 并在端口准备好接收附加数据时提供就绪信号。

8. 发明授权

US5892979A Queue control apparatus including memory to save data received when capacity of queue is less than a predetermined threshold 失效
标题翻译：队列控制装置，包括当队列容量小于预定阈值时存储接收的数据的存储器
公开(公告)号：US5892979A
公开(公告)日：1999-04-06
申请号：US967219
申请日：1997-10-29
申请人： Osamu Shiraki , Yoichi Koyanagi , Takeshi Horie , Toshiyuki Shimizu , Hiroaki Ishihata
发明人： Osamu Shiraki , Yoichi Koyanagi , Takeshi Horie , Toshiyuki Shimizu , Hiroaki Ishihata
IPC分类号： G11C7/00 , G06F5/06 , G06F13/00
CPC分类号： G06F5/06
摘要： An overflow control unit stores, in a FIFO buffer, data generated by a processor. The overflow control unit sets a predetermined flag, upon detecting that a FIFO buffer is full or nearly full. The overflow control unit stores, in a saving buffer, data sent from the processor, while the flag is set. Thereafter, the overflow control unit notifies the processor, by an interrupt, of an effect that an available capacity of the FIFO buffer rises above a predetermined threshold.Upon receiving an interrupt, the processor transfers to the FIFO buffer data saved in the saving buffer. Upon a completion of transferring to the FIFO buffer all data saved in the saving buffer, the processor resets the flag. This allows the overflow control unit to again store in the FIFO buffer, data sent from the processor. The overflow control unit also monitors the volume of data stored in the saving buffer, and notifies the processor, by an interrupt, of an effect that the saving buffer is full. Upon receiving an interrupt, the processor expands an available capacity of the saving buffer.
摘要翻译：溢出控制单元在FIFO缓冲器中存储由处理器生成的数据。检测到FIFO缓冲器已满或接近满时，溢出控制单元设置预定标志。在保存缓冲器中，溢出控制单元在设置标志时存储从处理器发送的数据。此后，溢出控制单元通过中断通知处理器FIFO缓冲器的可用容量上升到预定阈值以上的效果。在接收到中断时，处理器将传输到保存在保存缓冲区中的FIFO缓冲区数据。在完成向FIFO缓冲区传送保存在保存缓冲区中的所有数据后，处理器重置标志。这允许溢出控制单元再次存储在FIFO缓冲器中，从处理器发送的数据。溢出控制单元还监视存储在保存缓冲器中的数据量，并通过中断向处理器通知保存缓冲器已满的效果。在接收到中断时，处理器扩展了保存缓冲区的可用容量。

9. 发明授权

US5890217A Coherence apparatus for cache of multiprocessor 失效
标题翻译：多处理器缓存的一致性设备
公开(公告)号：US5890217A
公开(公告)日：1999-03-30
申请号：US598243
申请日：1996-02-07
申请人： Akira Kabemoto , Naohiro Shibata , Toshiyuki Muta , Takayuki Shimamura , Hirohide Sugahara , Junji Nishioka , Takatsugu Sasaki , Satoshi Shinohara , Yozo Nakayama , Jun Sakurai , Hiroaki Ishihata , Takeshi Horie , Toshiyuki Shimizu
发明人： Akira Kabemoto , Naohiro Shibata , Toshiyuki Muta , Takayuki Shimamura , Hirohide Sugahara , Junji Nishioka , Takatsugu Sasaki , Satoshi Shinohara , Yozo Nakayama , Jun Sakurai , Hiroaki Ishihata , Takeshi Horie , Toshiyuki Shimizu
IPC分类号： G06F12/08 , G06F15/17 , G06F13/00
CPC分类号： G06F12/0817 , G06F12/0831 , G06F2212/2542
摘要： A plurality of processors, each with caches provided for a plurality of processor modules and a local storage in which a main storage is distributed and arranged are mutually connected through an internal snoop bus. The processor modules are mutually connected through a second system bus. By using two separate buses, cache coherence operations within a processor group is kept separate from cache coherence operations outside the processor group.
摘要翻译：多个处理器，每个处理器具有为多个处理器模块提供的高速缓存和其中分配和布置主存储器的本地存储器通过内部监听总线相互连接。处理器模块通过第二系统总线相互连接。通过使用两个单独的总线，处理器组内的高速缓存一致性操作与处理器组之外的高速缓存一致性操作保持分开。

10. 发明授权

US10093083B2 Biaxially oriented, laminated polyamide resin film 有权
公开(公告)号：US10093083B2
公开(公告)日：2018-10-09
申请号：US14239720
申请日：2012-06-15
申请人： Yoshinori Miyaguchi , Toshiyuki Shimizu , Hirokazu Ooki
发明人： Yoshinori Miyaguchi , Toshiyuki Shimizu , Hirokazu Ooki
IPC分类号： B32B27/34 , B32B27/08 , B32B7/02 , B32B27/20
摘要： The present invention is to provide stable slipperiness in highly humid environments, further to provide suitability for printing and packaging with various design properties, stable bagmaking workability, and processability properties by simultaneously giving excellent transparency as same as that of common polyamide resin films, and still further to provide a biaxially oriented, laminated polyamide resin film producible at a low cost in the case of film production. A biaxially oriented, laminated polyamide resin film comprising at least one substrate layer and at least one slippery layer, wherein the substrate layer and the slippery layer contain polyamide resins and the biaxially oriented, laminated polyamide resin film has a static friction coefficient of 0.9 or lower in 65% RH environments and a haze value of 3.0% or lower.

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