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    • 1. 发明申请
    • Phase adjustment method, data transmission device, and data transmission system
    • 相位调整方式,数据传输装置和数据传输系统
    • US20120014461A1
    • 2012-01-19
    • US13200371
    • 2011-09-23
    • Takatsugu Sasaki
    • Takatsugu Sasaki
    • H04L27/00
    • H04L25/0272H03M9/00H04L7/0008H04L7/005H04L7/04H04L25/49H04L27/0014H04L2027/0093
    • A method of adjusting a phase includes generating phase adjustment patterns corresponding to transmission circuits by performing a serial-to-parallel conversion on a fundamental phase adjustment pattern in a transmission side circuit; transmitting, by the transmission circuits, transmission signals including the phase adjustment patterns; generating phase adjustment patterns corresponding to receiving circuits corresponding to the transmission circuits by performing the serial-to-parallel conversion on the fundamental phase adjustment pattern in a receiving side circuit; receiving, by the receiving circuits, the transmission signals using a reception clock signal; comparing signal patterns included in the transmission signals with the phase adjustment patterns and output comparison results; and adjusting a phase of the reception clock signal based on the comparison results.
    • 调整相位的方法包括通过对发送侧电路中的基波相位调整图案进行串并转换来生成与发送电路对应的相位调整模式; 由发送电路发送包括相位调整图案的发送信号; 通过对接收侧电路中的基相位调整图案进行串并转换来生成与发送电路对应的接收电路对应的相位调整图案; 由接收电路使用接收时钟信号接收发送信号; 将发送信号中包括的信号模式与相位调整模式和输出比较结果进行比较; 以及基于比较结果调整接收时钟信号的相位。
    • 3. 发明授权
    • Asynchronous access system controlling processing modules making
requests to a shared system memory
    • 控制处理模块的异步访问系统向共享系统存储器发出请求
    • US5761728A
    • 1998-06-02
    • US777184
    • 1996-12-27
    • Hiroshi SaitoTakatsugu SasakiHirohide SugaharaAkira KabemotoHajime TakahashiJun Funaki
    • Hiroshi SaitoTakatsugu SasakiHirohide SugaharaAkira KabemotoHajime TakahashiJun Funaki
    • G06F12/00G06F13/16G06F15/16G06F9/38
    • G06F13/1673
    • An asynchronous access system for a computer system includes processing modules performing processes, at least one shared system memory module, and a system bus connecting the processing modules and the shared system memory module. Each of the processing modules includes a processor, a plurality of buffers coupled to the processor and to the system bus, and a controlling unit for writing data from the plurality of processors into the shared system memory module. Data is written into the shared system memory module by a processor generating write instructions to write data via the plurality of buffers and the system bus. The controlling unit controls the writing such that one writing instruction writes data into a plurality of buffers, then transfers the data to the shared system memory module via the system bus, with another writing instruction writing additional data into another plurality of buffers and transferring the additional data to the shared system memory module.
    • 用于计算机系统的异步访问系统包括执行处理的处理模块,至少一个共享系统存储器模块以及连接处理模块和共享系统存储器模块的系统总线。 每个处理模块包括处理器,耦合到处理器和系统总线的多个缓冲器,以及用于将数据从多个处理器写入共享系统存储器模块的控制单元。 通过处理器将数据写入共享系统存储器模块,该处理器产生写入指令以经由多个缓冲器和系统总线写入数据。 控制单元控制写入,使得一个写入指令将数据写入多个缓冲器,然后经由系统总线将数据传送到共享系统存储器模块,另一个写入指令将另外的数据写入另一个多个缓冲器并传送附加的数据 数据到共享系统内存模块。
    • 4. 发明授权
    • Message control system for data communication system
    • 数据通信系统消息控制系统
    • US5410650A
    • 1995-04-25
    • US859319
    • 1992-05-28
    • Takatsugu SasakiAkira KabemotoHajime TakahashiHorihide Sugahara
    • Takatsugu SasakiAkira KabemotoHajime TakahashiHorihide Sugahara
    • G06F13/12G06F15/17G06F13/00
    • G06F15/17G06F13/128
    • A message control system for a data communication system which takes the form of a loosely coupled multiprocessing system in which a plurality of processing modules respectively having a memory unit are coupled to each other via a system bus. In the message control system, each processing module (10, 40) includes a central processing unit (11, 41), a memory unit (12, 42) and a connection unit (13, 43). The connection unit (13, 43) includes at least a logical transmitting port (21, 51) for transmitting a message, a logical receiving port (22, 53) for receiving a message, a transmission system connecting unit (23), a reception system connecting unit (24), a transmitting side fault generation monitoring unit (25) and a receiving side fault generation monitoring unit (26).
    • PCT No.PCT / JP91 / 01307 Sec。 371日期:1992年5月28日 102(e)日期1992年5月28日PCT 1991年9月27日PCT公布。 公开号WO92 / 06431 日期:1992年4月16日。一种用于数据通信系统的消息控制系统,其采取松散耦合的多处理系统的形式,其中分别具有存储器单元的多个处理模块经由系统总线彼此耦合。 在消息控制系统中,每个处理模块(10,40)包括中央处理单元(11,41),存储单元(12,42)和连接单元(13,43)。 连接单元(13,43)至少包括用于发送消息的逻辑发送端口(21,51),用于接收消息的逻辑接收端口(22,53),发送系统连接单元(23),接收 系统连接单元(24),发送侧故障生成监视单元(25)和接收侧故障生成监视单元(26)。
    • 8. 发明授权
    • Memory device and refresh adjusting method
    • 内存设备和刷新调整方式
    • US08539310B2
    • 2013-09-17
    • US12425756
    • 2009-04-17
    • Takatsugu Sasaki
    • Takatsugu Sasaki
    • G06F11/00
    • G11C11/406G06F11/106G11C2211/4062
    • When a single error of data is detected by an ECC circuit, a cycle adjusting unit provided on a memory board shortens a refresh cycle T1 of a refresh request generating unit to T2 and causes a patrol controlling unit to intensively carry out an error patrol of an error-occurred address at a cycle T3, which is slightly longer than the changed refresh cycle T2. If an error is not detected for more than a predetermined period of time after the error patrol is started, the error patrol is stopped.Furthermore, if a single error is not detected for more than a predetermined period of time after the error patrol is stopped, the shortening of the refresh cycle is cancelled and returned to the original cycle.
    • 当由ECC电路检测到数据的单个错误时,设置在存储器板上的循环调整单元将刷新请求生成单元的刷新周期T1缩短到T2,并使巡视控制单元集中地执行错误巡检 在周期T3的错误发生的地址,其比改变的刷新周期T2稍长。 如果在错误巡视开始之后没有检测到超过预定时间段的错误,则错误巡检停止。 此外,如果在错误巡视停止之后没有检测到多个预定时间段的单个错误,则刷新周期的缩短被取消并返回到原始周期。
    • 9. 发明申请
    • MEMORY REFRESHING APPARATUS AND METHOD FOR MEMORY REFRESH
    • 内存刷新装置和存储器刷新方法
    • US20100106901A1
    • 2010-04-29
    • US12683059
    • 2010-01-06
    • Masanori HIGETAKenji SuzukiTakatsugu Sasaki
    • Masanori HIGETAKenji SuzukiTakatsugu Sasaki
    • G06F12/06
    • G11C11/406G06F11/106G11C11/401G11C29/028G11C29/50016G11C29/52G11C2029/0409G11C2211/4061
    • The optimization of a refresh cycle is carried out in harmony with the error occurrence state in the memory with the presence of a normal patrol controlling section controlling a normal patrol operation that patrols the memory; an additional patrol controlling section controlling an additional patrol operation that patrols, if a first error in the memory is detected during the normal patrol operation, an error occurring area in which the first error occurs and which is included in the memory; a measuring section (15) measuring, if a second error is detected in the error occurring area during the additional patrol operation, an error frequency representing information of error in the error occurring area; and a refresh cycle adjusting section adjusting the refresh cycle in accordance with the error frequency measured by the measuring section.
    • 刷新周期的优化与存储器中的错误发生状态相一致地执行,存在正常巡视控制部分,其控制巡视存储器的正常巡视操作; 如果在正常巡视操作期间检测到存储器中的第一错误,则发生第一错误并且包括在存储器中的错误发生区域的附加巡检控制部分,其控制附加巡视操作, 测量部分,测量在所述附加巡视操作期间在所述错误发生区域中检测到第二误差的误差频率,所述误差频率表示所述错误发生区域中的误差信息; 以及刷新周期调整部,其根据由测量部测量的误差频率来调整刷新周期。
    • 10. 发明授权
    • Memory refreshing circuit and method for memory refresh
    • 内存刷新电路和内存刷新方法
    • US08549366B2
    • 2013-10-01
    • US12683059
    • 2010-01-06
    • Masanori HigetaKenji SuzukiTakatsugu Sasaki
    • Masanori HigetaKenji SuzukiTakatsugu Sasaki
    • G06F11/00G11C29/00
    • G11C11/406G06F11/106G11C11/401G11C29/028G11C29/50016G11C29/52G11C2029/0409G11C2211/4061
    • The optimization of a refresh cycle is carried out in harmony with the error occurrence state in the memory with the presence of a normal patrol controlling section controlling a normal patrol operation that patrols the memory; an additional patrol controlling section controlling an additional patrol operation that patrols, if a first error in the memory is detected during the normal patrol operation, an error occurring area in which the first error occurs and which is included in the memory; a measuring section (15) measuring, if a second error is detected in the error occurring area during the additional patrol operation, an error frequency representing information of error in the error occurring area; and a refresh cycle adjusting section adjusting the refresh cycle in accordance with the error frequency measured by the measuring section.
    • 刷新周期的优化与存储器中的错误发生状态相一致地执行,存在正常巡视控制部分,其控制巡视存储器的正常巡视操作; 如果在正常巡视操作期间检测到存储器中的第一错误,则发生第一错误并且包括在存储器中的错误发生区域的附加巡检控制部分,其控制附加巡视操作, 测量部分,测量在所述附加巡视操作期间在所述错误发生区域中检测到第二误差的误差频率,所述误差频率表示所述错误发生区域中的误差信息; 以及刷新周期调整部,其根据由测量部测量的误差频率来调整刷新周期。