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1. 发明授权

US5892979A Queue control apparatus including memory to save data received when capacity of queue is less than a predetermined threshold 失效
标题翻译：队列控制装置，包括当队列容量小于预定阈值时存储接收的数据的存储器
公开(公告)号：US5892979A
公开(公告)日：1999-04-06
申请号：US967219
申请日：1997-10-29
申请人： Osamu Shiraki , Yoichi Koyanagi , Takeshi Horie , Toshiyuki Shimizu , Hiroaki Ishihata
发明人： Osamu Shiraki , Yoichi Koyanagi , Takeshi Horie , Toshiyuki Shimizu , Hiroaki Ishihata
IPC分类号： G11C7/00 , G06F5/06 , G06F13/00
CPC分类号： G06F5/06
摘要： An overflow control unit stores, in a FIFO buffer, data generated by a processor. The overflow control unit sets a predetermined flag, upon detecting that a FIFO buffer is full or nearly full. The overflow control unit stores, in a saving buffer, data sent from the processor, while the flag is set. Thereafter, the overflow control unit notifies the processor, by an interrupt, of an effect that an available capacity of the FIFO buffer rises above a predetermined threshold.Upon receiving an interrupt, the processor transfers to the FIFO buffer data saved in the saving buffer. Upon a completion of transferring to the FIFO buffer all data saved in the saving buffer, the processor resets the flag. This allows the overflow control unit to again store in the FIFO buffer, data sent from the processor. The overflow control unit also monitors the volume of data stored in the saving buffer, and notifies the processor, by an interrupt, of an effect that the saving buffer is full. Upon receiving an interrupt, the processor expands an available capacity of the saving buffer.
摘要翻译：溢出控制单元在FIFO缓冲器中存储由处理器生成的数据。检测到FIFO缓冲器已满或接近满时，溢出控制单元设置预定标志。在保存缓冲器中，溢出控制单元在设置标志时存储从处理器发送的数据。此后，溢出控制单元通过中断通知处理器FIFO缓冲器的可用容量上升到预定阈值以上的效果。在接收到中断时，处理器将传输到保存在保存缓冲区中的FIFO缓冲区数据。在完成向FIFO缓冲区传送保存在保存缓冲区中的所有数据后，处理器重置标志。这允许溢出控制单元再次存储在FIFO缓冲器中，从处理器发送的数据。溢出控制单元还监视存储在保存缓冲器中的数据量，并通过中断向处理器通知保存缓冲器已满的效果。在接收到中断时，处理器扩展了保存缓冲区的可用容量。

2. 发明授权

US5742843A Control system for access between processing elements in a parallel computer 失效
标题翻译：用于在并行计算机中的处理元件之间进行访问的控制系统
公开(公告)号：US5742843A
公开(公告)日：1998-04-21
申请号：US503916
申请日：1995-07-19
申请人： Yoichi Koyanagi , Osamu Shiraki , Takeshi Horie , Toshiyuki Shimizu , Hiroaki Ishihata
发明人： Yoichi Koyanagi , Osamu Shiraki , Takeshi Horie , Toshiyuki Shimizu , Hiroaki Ishihata
IPC分类号： G06F15/17 , G06F15/80
CPC分类号： G06F15/17
摘要： When the processor writes a command data string into an address of the command entry area, a corresponding command is created by a bus interface. If an address output by the processor corresponds to a distributed shared memory area, the bus interface creates a remote access command. The send controller constructs a message based on the command created by the bus interface. This message is sent either to an interconnection network, or to a receive controller. The receive controller receives the message and interprets it. An address output by the processor is detected by a cache area access unit, and the cache area in the memory is accessed. When the processor receives an interrupt request while waiting for a response message to a remote read request, an deadlock control unit detects an abnormal end of the remote read request that the remote read has ended in an error, and, controls the processor to process the interrupt request with priority.
摘要翻译：当处理器将命令数据串写入命令输入区域的地址时，由总线接口创建相应的命令。如果处理器输出的地址对应于分布式共享存储器区域，则总线接口创建远程访问命令。发送控制器根据总线接口创建的命令构建消息。该消息被发送到互连网络或发送到接收控制器。接收控制器接收消息并对其进行解释。由处理器输出的地址由高速缓存区域访问单元检测，存储器中的高速缓存区域被访问。当处理器在等待对远程读取请求的响应消息的同时接收到中断请求时，死锁控制单元检测到远程读取已经结束的远程读取请求的异常结束，并且控制处理器中断请求优先。

3. 发明授权

US6115803A Parallel computer which verifies direct data transmission between local memories with a send complete flag 失效
标题翻译：并行计算机，通过发送完成标志来验证本地存储器之间的直接数据传输
公开(公告)号：US6115803A
公开(公告)日：2000-09-05
申请号：US10627
申请日：1998-01-22
申请人： Kenichi Hayashi , Yoichi Koyanagi , Takeshi Horie , Osamu Shiraki
发明人： Kenichi Hayashi , Yoichi Koyanagi , Takeshi Horie , Osamu Shiraki
IPC分类号： G06F15/17 , G06F9/46 , G06F9/54 , G06F15/163 , G06F15/177 , G06F9/345 , G06F9/38
CPC分类号： G06F9/54
摘要： A parallel computer including a plurality of processing elements, each of processing elements comprising a flag address holding unit for temporarily holding an address of a send complete flag of a direct remote write message when the direct remote write message is sent to another processing element, and a flag update unit for exclusively updating a flag represented by the address held in the flag address holding unit when data indicated by the direct remote write message has been sent.
摘要翻译：一种并行计算机，包括多个处理元件，每个处理元件包括标志地址保持单元，用于当直接远程写入消息被发送到另一个处理元件时临时保存直接远程写入消息的发送完成标志的地址;以及标志更新单元，用于当已经发送由直接远程写入消息指示的数据时，专门地更新由保持在标志地址保持单元中的地址表示的标志。

4. 发明授权

US5604913A Vector processor having a mask register used for performing nested conditional instructions 失效
标题翻译：矢量处理器具有用于执行嵌套条件指令的掩码寄存器
公开(公告)号：US5604913A
公开(公告)日：1997-02-18
申请号：US237305
申请日：1994-05-03
申请人： Yoichi Koyanagi , Takeshi Horie
发明人： Yoichi Koyanagi , Takeshi Horie
IPC分类号： G06F9/32 , G06F9/38 , G06F15/78 , G06F17/16 , G06F15/347
CPC分类号： G06F17/16 , G06F15/8084 , G06F9/30036 , G06F9/30072 , G06F9/30094
摘要： In a computer equipped with a mask register in which is stored mask data indicating, for each array element, whether or not a statement such as an IF statement or an ELSE statement should be applied, the computer having a vector processor executing vector operation processing according to the mask data stored in the mask register, a first executing unit acquires first and second memory areas in which the mask data is saved in a stack formation. A second executing unit generates, when an IF statement appears in execution of a program, mask data indicating truth/falsity of a conditional expression of the IF statement, and saves the mask data indicating the truth/falsity of the conditional expression in the first memory area. A third executing unit reads latest mask data saved in the second memory area in synchronism with a process of the second executing unit. A fourth executing unit performs a bit-base logic operation on the mask data saved by the second executing unit and the mask data read by the third executing unit, stores mask data thus generated and applied to the IF statement in the mask register, and saves the above mask data applied to the above IF statement in the second memory area.
摘要翻译：在配备有掩码寄存器的计算机中，存储掩码数据，指示对于每个数组元素，是否应该应用诸如IF语句或ELSE语句的语句，具有向量处理器的计算机执行向量操作处理对于存储在掩码寄存器中的掩码数据，第一执行单元获取在堆栈形成中保存掩码数据的第一和第二存储区域。第二执行单元在执行程序时出现IF语句时，产生表示IF语句的条件表达式的真实/虚假的数据，并将表示条件表达式的真值/虚假的掩码数据保存在第一存储器中区。第三执行单元与第二执行单元的处理同步地读取保存在第二存储区域中的最新掩码数据。第四执行单元对由第二执行单元保存的掩码数据和由第三执行单元读取的掩码数据执行位基逻辑运算，将由此生成并应用于掩码寄存器中的IF语句的掩码数据存储，并保存上述掩码数据应用于第二存储区域中的上述IF语句。

5. 发明授权

US5818755A Storage apparatus having a nonvolatile storage device capable of retaining data after an incomplete write operation and method of accessing same 失效
标题翻译：具有能够在不完整写入操作之后保留数据的非易失性存储装置的存储装置及其访问方法
公开(公告)号：US5818755A
公开(公告)日：1998-10-06
申请号：US828690
申请日：1997-03-31
申请人： Yoichi Koyanagi , Toshiyuki Shimizu
发明人： Yoichi Koyanagi , Toshiyuki Shimizu
IPC分类号： G11C16/10 , G11C16/06
CPC分类号： G11C16/105 , G11C16/102
摘要： A storage region formed of a nonvolatile storage device is divided into two blocks; block `0` and block `1`. In a process for writing data, the magic Nos. of the blocks `0` and `1` are checked. On condition that both the magic Nos. have a correct value, the sequential Nos. of the blocks `0` and `1` are compared so as to select the block whose sequential No. has a smaller value. The data to-be-written is written into the selected block. Subsequently, a value obtained by adding "1" to the sequential No. of the unselected block is written as the sequential No. of the selected block. Lastly, the magic No. is written into the selected block. On the other hand, in a process for reading data, the magic Nos. of the blocks `0` and `1` are checked. On condition that both the magic Nos. have the correct value, the block whose sequential No. has a larger value is selected, and the data to-be-read is read out of the selected block. According to the present invention, even in a case where the power of the storage device has turned off during the data write process and where the data write has not been completed, data before the write process remain. Even when the data are the set values or the likes of, for example, a computer system, the remaining data can be used for avoiding the state of the system incapable of starting.
摘要翻译：由非易失性存储装置形成的存储区域被分成两块; 块'0'和块'1'。在编写数据的过程中，检查块“0”和“1”的魔术编号。在两个魔术编号都具有正确的值的情况下，比较块'0'和'1'的顺序号，以便选择顺序号具有较小值的块。要写入的数据将写入所选块。随后，将未选择块的顺序号添加“1”而获得的值作为选择块的顺序编号。最后，魔术编号被写入所选的块。另一方面，在读取数据的过程中，检查块'0'和'1'的魔术编号。在两个魔术编号都具有正确的值的情况下，选择顺序号具有较大值的块，并且从所选择的块中读出要读取的数据。根据本发明，即使在数据写入处理期间存储装置的电源已经关闭并且数据写入尚未完成的情况下，仍然存在写入处理之前的数据。即使数据是例如计算机系统的设定值等，也可以使用剩余的数据来避免不能启动的系统的状态。

6. 发明授权

US06493320B1 Automatic initialization and tuning across a high speed, plesiochronous, parallel link 有权
标题翻译：通过高速，同步，并行链路自动初始化和调整
公开(公告)号：US06493320B1
公开(公告)日：2002-12-10
申请号：US09249825
申请日：1999-02-12
申请人： Richard L. Schober , Yoichi Koyanagi , Raghu Sastry , Hirotaka Tamura , Kohtaro Gotoh
发明人： Richard L. Schober , Yoichi Koyanagi , Raghu Sastry , Hirotaka Tamura , Kohtaro Gotoh
IPC分类号： G01R3108
CPC分类号： H04B17/0085
摘要： A method and apparatus automatically initialize and tune a link in a network system. The link couples one router to another router and may be implemented as a high speed, plesiochronous, parallel link. The apparatus includes a first link control unit coupled to a first end of the link and a second link control unit coupled to a second end of the link. The second link control unit is capable of communicating with the first link control unit to achieve automatic adjustment of the operating parameters of the link to maximize signal propagation across and minimize the power consumption of the link. The method of initializing and tuning across a high speed link in a network is also disclosed.
摘要翻译：方法和装置自动初始化和调整网络系统中的链路。该链路将一个路由器耦合到另一个路由器，并且可以被实现为高速，同步，并行链路。该装置包括耦合到链路的第一端的第一链路控制单元和耦合到链路的第二端的第二链路控制单元。第二链路控制单元能够与第一链路控制单元进行通信，以实现链路的操作参数的自动调整，以最大化跨越的信号传播并使链路的功率消耗最小化。还公开了通过网络中的高速链路进行初始化和调谐的方法。

7. 发明授权

US08593313B2 Parallel-to-serial conversion circuit, information processing apparatus, information processing system, and parallel-to-serial conversion method 有权
标题翻译：并行到串行转换电路，信息处理装置，信息处理系统以及并行到串行转换方法
公开(公告)号：US08593313B2
公开(公告)日：2013-11-26
申请号：US13476287
申请日：2012-05-21
申请人： Yoichi Koyanagi
发明人： Yoichi Koyanagi
IPC分类号： H03M9/00
CPC分类号： H03M9/00 , H04J3/0697 , H04L25/14
摘要： A parallel-to-serial conversion circuit includes a plurality of parallel-to-serial conversion units, each being configured to include a dividing circuit configured to divide a clock signal having a second clock cycle to generate a clock signal having a first clock cycle, a parallel input circuit configured to input a signal having a plurality of bits parallel to one another in the first clock cycle, and a serial output circuit configured to serially output the signal having the plurality of bits input to the parallel input circuit bit-by-bit in the second clock cycle, wherein, among the plurality of parallel-to-serial conversion units, one of the dividing circuits has a synchronization signal interface that causes an output clock signal to synchronize with a clock signal output from the other dividing circuit in another parallel-to-serial conversion unit.
摘要翻译：并行到串行转换电路包括多个并行到串行转换单元，每个并行转换单元被配置为包括分配电路，其被配置为对具有第二时钟周期的时钟信号进行分频，以产生具有第一时钟周期的时钟信号，并行输入电路，被配置为在第一时钟周期中输入具有彼此并行的多个位的信号;以及串行输出电路，被配置为串行输出具有输入到并行输入电路的多个位的信号，在所述多个并行到串行转换单元中，一个所述分频电路具有同步信号接口，该同步信号接口使得输出时钟信号与从其他分频电路输出的时钟信号同步另一个并行到串行转换单元。

8. 发明授权

US07427878B2 Low-voltage differential signal driver for high-speed digital transmission 有权
标题翻译：低电压差分信号驱动器，用于高速数字传输
公开(公告)号：US07427878B2
公开(公告)日：2008-09-23
申请号：US11421522
申请日：2006-06-01
申请人： Jian Hong Jiang , Yoichi Koyanagi
发明人： Jian Hong Jiang , Yoichi Koyanagi
IPC分类号： H03K19/0175 , H03K19/094
CPC分类号： H03K19/018528
摘要： A low-voltage differential signal (LVDS) driver includes at least two programmable fingers operable to drive a signal and at least two pre-drivers. Each pre-driver is associated with one or more of the programmable fingers and is operable to enable or disable the associated one or more programmable fingers. An enabled programmable finger drives the signal and contributes to the capacitive loading of the driver, and a disabled programmable finger does not drive the signal and does not contribute to the capacitive loading of the driver.
摘要翻译：低电压差分信号（LVDS）驱动器包括至少两个可编程手指，用于驱动信号和至少两个前驱动器。每个预驱动器与一个或多个可编程手指相关联并且可操作以启用或禁用相关联的一个或多个可编程手指。启用的可编程手指驱动信号并有助于驱动器的电容性负载，并且禁用的可编程手指不驱动信号并且不会对驱动器的电容性负载产生影响。

9. 发明授权

US07173965B2 Equalizing a signal for transmission 有权
标题翻译：将信号均衡以进行传输
公开(公告)号：US07173965B2
公开(公告)日：2007-02-06
申请号：US10357691
申请日：2003-02-03
申请人： Yoichi Koyanagi , Yasuo Hidaka , Weixin Gai , Hirotaka Tamura
发明人： Yoichi Koyanagi , Yasuo Hidaka , Weixin Gai , Hirotaka Tamura
IPC分类号： H03K5/159 , H04B3/04 , H04B3/14 , H01P9/00
CPC分类号： H04L25/03343
摘要： Equalizing a signal includes receiving a data sequence signal having an amplitude. An adjustment of the data sequence signal operable to equalize the data sequence signal is determined. A control signal operable to adjust the amplitude of the data sequence signal in accordance with the adjustment is generated, where the control signal has an analog form. The amplitude of the data sequence signal is adjusted using the control signal in order to equalize the data sequence signal.
摘要翻译：信号均衡包括接收具有振幅的数据序列信号。确定可操作以均衡数据序列信号的数据序列信号的调整。产生用于根据调整来调节数据序列信号的幅度的控制信号，其中控制信号具有模拟形式。使用控制信号调整数据序列信号的幅度，以便均衡数据序列信号。

10. 发明授权

US07065135B2 System and method for equalizing high-speed data transmission 有权
标题翻译：用于均衡高速数据传输的系统和方法
公开(公告)号：US07065135B2
公开(公告)日：2006-06-20
申请号：US10870019
申请日：2004-06-16
申请人： Yoichi Koyanagi
发明人： Yoichi Koyanagi
IPC分类号： H03K1/159
CPC分类号： H04L25/03044
摘要： According to one embodiment of the present invention, a method for equalizing a signal includes introducing a delay into an incoming data signal to generate a first delayed signal of a first format. A plurality of drivers operable to receive the incoming signal and the first delayed signal are identified. Each of the plurality of drivers have an associated drive strength. A first driver is selected from the plurality of drivers to receive the incoming signal. The selection is based at least in part on a comparison of the drive strength associated with the first driver to a maximum output current of the first driver. A second driver is selected from the plurality of drivers to receive the first delayed signal. The selection is based at least in part on a comparison of the drive strength associated with the second driver to a maximum output current of the second driver. The incoming signal is directed to the first driver, and the first delayed signal is directed to the second driver.
摘要翻译：根据本发明的一个实施例，一种用于均衡信号的方法包括将延迟引入到输入数据信号中以产生第一格式的第一延迟信号。识别可操作以接收输入信号和第一延迟信号的多个驱动器。多个驱动器中的每一个具有相关联的驱动强度。从多个驱动器中选择第一驱动器以接收输入信号。该选择至少部分地基于与第一驱动器相关联的驱动强度与第一驱动器的最大输出电流的比较。从多个驱动器中选择第二驱动器以接收第一延迟信号。该选择至少部分地基于与第二驱动器相关联的驱动强度与第二驱动器的最大输出电流的比较。输入信号被引导到第一驱动器，并且第一延迟信号被引导到第二驱动器。

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