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1. 发明授权

US5892979A Queue control apparatus including memory to save data received when capacity of queue is less than a predetermined threshold 失效
标题翻译：队列控制装置，包括当队列容量小于预定阈值时存储接收的数据的存储器
公开(公告)号：US5892979A
公开(公告)日：1999-04-06
申请号：US967219
申请日：1997-10-29
申请人： Osamu Shiraki , Yoichi Koyanagi , Takeshi Horie , Toshiyuki Shimizu , Hiroaki Ishihata
发明人： Osamu Shiraki , Yoichi Koyanagi , Takeshi Horie , Toshiyuki Shimizu , Hiroaki Ishihata
IPC分类号： G11C7/00 , G06F5/06 , G06F13/00
CPC分类号： G06F5/06
摘要： An overflow control unit stores, in a FIFO buffer, data generated by a processor. The overflow control unit sets a predetermined flag, upon detecting that a FIFO buffer is full or nearly full. The overflow control unit stores, in a saving buffer, data sent from the processor, while the flag is set. Thereafter, the overflow control unit notifies the processor, by an interrupt, of an effect that an available capacity of the FIFO buffer rises above a predetermined threshold.Upon receiving an interrupt, the processor transfers to the FIFO buffer data saved in the saving buffer. Upon a completion of transferring to the FIFO buffer all data saved in the saving buffer, the processor resets the flag. This allows the overflow control unit to again store in the FIFO buffer, data sent from the processor. The overflow control unit also monitors the volume of data stored in the saving buffer, and notifies the processor, by an interrupt, of an effect that the saving buffer is full. Upon receiving an interrupt, the processor expands an available capacity of the saving buffer.
摘要翻译：溢出控制单元在FIFO缓冲器中存储由处理器生成的数据。检测到FIFO缓冲器已满或接近满时，溢出控制单元设置预定标志。在保存缓冲器中，溢出控制单元在设置标志时存储从处理器发送的数据。此后，溢出控制单元通过中断通知处理器FIFO缓冲器的可用容量上升到预定阈值以上的效果。在接收到中断时，处理器将传输到保存在保存缓冲区中的FIFO缓冲区数据。在完成向FIFO缓冲区传送保存在保存缓冲区中的所有数据后，处理器重置标志。这允许溢出控制单元再次存储在FIFO缓冲器中，从处理器发送的数据。溢出控制单元还监视存储在保存缓冲器中的数据量，并通过中断向处理器通知保存缓冲器已满的效果。在接收到中断时，处理器扩展了保存缓冲区的可用容量。

2. 发明授权

US5742843A Control system for access between processing elements in a parallel computer 失效
标题翻译：用于在并行计算机中的处理元件之间进行访问的控制系统
公开(公告)号：US5742843A
公开(公告)日：1998-04-21
申请号：US503916
申请日：1995-07-19
申请人： Yoichi Koyanagi , Osamu Shiraki , Takeshi Horie , Toshiyuki Shimizu , Hiroaki Ishihata
发明人： Yoichi Koyanagi , Osamu Shiraki , Takeshi Horie , Toshiyuki Shimizu , Hiroaki Ishihata
IPC分类号： G06F15/17 , G06F15/80
CPC分类号： G06F15/17
摘要： When the processor writes a command data string into an address of the command entry area, a corresponding command is created by a bus interface. If an address output by the processor corresponds to a distributed shared memory area, the bus interface creates a remote access command. The send controller constructs a message based on the command created by the bus interface. This message is sent either to an interconnection network, or to a receive controller. The receive controller receives the message and interprets it. An address output by the processor is detected by a cache area access unit, and the cache area in the memory is accessed. When the processor receives an interrupt request while waiting for a response message to a remote read request, an deadlock control unit detects an abnormal end of the remote read request that the remote read has ended in an error, and, controls the processor to process the interrupt request with priority.
摘要翻译：当处理器将命令数据串写入命令输入区域的地址时，由总线接口创建相应的命令。如果处理器输出的地址对应于分布式共享存储器区域，则总线接口创建远程访问命令。发送控制器根据总线接口创建的命令构建消息。该消息被发送到互连网络或发送到接收控制器。接收控制器接收消息并对其进行解释。由处理器输出的地址由高速缓存区域访问单元检测，存储器中的高速缓存区域被访问。当处理器在等待对远程读取请求的响应消息的同时接收到中断请求时，死锁控制单元检测到远程读取已经结束的远程读取请求的异常结束，并且控制处理器中断请求优先。

3. 发明授权

US6115803A Parallel computer which verifies direct data transmission between local memories with a send complete flag 失效
标题翻译：并行计算机，通过发送完成标志来验证本地存储器之间的直接数据传输
公开(公告)号：US6115803A
公开(公告)日：2000-09-05
申请号：US10627
申请日：1998-01-22
申请人： Kenichi Hayashi , Yoichi Koyanagi , Takeshi Horie , Osamu Shiraki
发明人： Kenichi Hayashi , Yoichi Koyanagi , Takeshi Horie , Osamu Shiraki
IPC分类号： G06F15/17 , G06F9/46 , G06F9/54 , G06F15/163 , G06F15/177 , G06F9/345 , G06F9/38
CPC分类号： G06F9/54
摘要： A parallel computer including a plurality of processing elements, each of processing elements comprising a flag address holding unit for temporarily holding an address of a send complete flag of a direct remote write message when the direct remote write message is sent to another processing element, and a flag update unit for exclusively updating a flag represented by the address held in the flag address holding unit when data indicated by the direct remote write message has been sent.
摘要翻译：一种并行计算机，包括多个处理元件，每个处理元件包括标志地址保持单元，用于当直接远程写入消息被发送到另一个处理元件时临时保存直接远程写入消息的发送完成标志的地址;以及标志更新单元，用于当已经发送由直接远程写入消息指示的数据时，专门地更新由保持在标志地址保持单元中的地址表示的标志。

4. 发明授权

US5890217A Coherence apparatus for cache of multiprocessor 失效
标题翻译：多处理器缓存的一致性设备
公开(公告)号：US5890217A
公开(公告)日：1999-03-30
申请号：US598243
申请日：1996-02-07
申请人： Akira Kabemoto , Naohiro Shibata , Toshiyuki Muta , Takayuki Shimamura , Hirohide Sugahara , Junji Nishioka , Takatsugu Sasaki , Satoshi Shinohara , Yozo Nakayama , Jun Sakurai , Hiroaki Ishihata , Takeshi Horie , Toshiyuki Shimizu
发明人： Akira Kabemoto , Naohiro Shibata , Toshiyuki Muta , Takayuki Shimamura , Hirohide Sugahara , Junji Nishioka , Takatsugu Sasaki , Satoshi Shinohara , Yozo Nakayama , Jun Sakurai , Hiroaki Ishihata , Takeshi Horie , Toshiyuki Shimizu
IPC分类号： G06F12/08 , G06F15/17 , G06F13/00
CPC分类号： G06F12/0817 , G06F12/0831 , G06F2212/2542
摘要： A plurality of processors, each with caches provided for a plurality of processor modules and a local storage in which a main storage is distributed and arranged are mutually connected through an internal snoop bus. The processor modules are mutually connected through a second system bus. By using two separate buses, cache coherence operations within a processor group is kept separate from cache coherence operations outside the processor group.
摘要翻译：多个处理器，每个处理器具有为多个处理器模块提供的高速缓存和其中分配和布置主存储器的本地存储器通过内部监听总线相互连接。处理器模块通过第二系统总线相互连接。通过使用两个单独的总线，处理器组内的高速缓存一致性操作与处理器组之外的高速缓存一致性操作保持分开。

5. 发明授权

US5765187A Control system for a ring buffer which prevents overrunning and underrunning 失效
标题翻译：环形缓冲器的控制系统，可防止超速和欠载
公开(公告)号：US5765187A
公开(公告)日：1998-06-09
申请号：US844852
申请日：1997-04-22
申请人： Toshiyuki Shimizu , Takeshi Horie , Hiroaki Ishihata
发明人： Toshiyuki Shimizu , Takeshi Horie , Hiroaki Ishihata
IPC分类号： G06F13/38 , G06F5/06 , G06F5/10 , G06F5/14 , G06F13/00
CPC分类号： G06F5/14 , H04L49/90 , H04L49/901 , H04L49/9031 , H04L49/9047 , H04L49/9057
摘要： A receiving buffer control system comprises a memory having a buffer area serving as a receiving buffer, data being applied to the memory via a bus, a write pointer indicating a write address of the buffer area, and a read pointer indicating a read address of the buffer area. An overrun/underrun detection circuit detects a situation in which an overrun or an underrun will occur in the buffer area in response to the write address indicated by the write pointer and the read address indicated by the read pointer. A control part disables the data from being written into and read out from the buffer area when the overrun/underrun detection circuit detects the situation.
摘要翻译：接收缓冲器控制系统包括具有用作接收缓冲器的缓冲区的存储器，经由总线被施加到存储器的数据，指示缓冲区的写入地址的写指针，以及指示读取地址的读指针缓冲区。溢出/欠载检测电路响应于由写指针指示的写地址和读指针指示的读地址，检测缓冲区内发生溢出或欠载的情况。当超限/欠载检测电路检测到这种情况时，控制部分禁止数据被写入缓冲区并从缓冲区读出。

6. 发明授权

US5832215A Data gathering/scattering system for a plurality of processors in a parallel computer 失效
标题翻译：用于并行计算机中的多个处理器的数据收集/散射系统
公开(公告)号：US5832215A
公开(公告)日：1998-11-03
申请号：US727932
申请日：1991-07-10
申请人： Sadayuki Kato , Hiroaki Ishihata , Takeshi Horie , Satoshi Inano , Toshiyuki Shimizu
发明人： Sadayuki Kato , Hiroaki Ishihata , Takeshi Horie , Satoshi Inano , Toshiyuki Shimizu
IPC分类号： G06F15/173 , G06F15/163
CPC分类号： G06F15/17393
摘要： In a data gathering/scattering system having a data gathering system and a data scattering system in a parallel computer constituted by a plurality of processors connected in parallel through a common bus or hierarchical common buses, the data gathering/scattering system includes: one processor having a buffer for temporarily storing data gathered from or transmitted to other processors, a three-state buffer for transmitting data from the buffer to the common bus, and a switching unit for switching a connection between a transmission and a reception to form the data gathering system or the data scattering system; each of the other processors having a buffer for temporarily storing data to be transferred or data to be received, a transfer control unit for controlling data transmissions from the buffer to the common bus, a reception control unit for selecting the reception data from among all data on the common bus, a three-state buffer for transmitting data from the buffer to the common bus, and a switching unit for switching a connection between a transmission and a reception to form the data gathering system or the data scattering system, and an AND circuit for obtaining a coincidence of a data transmission or data reception among the processors, and for sending a command for a data transmission or data reception to other processors.
摘要翻译：在具有数据采集系统和数据散布系统的数据采集/散射系统中，数据采集/散射系统包括：一个处理器，具有：用于临时存储从其他处理器收集或发送到其他处理器的数据的缓冲器，用于从缓冲器向公共总线发送数据的三态缓冲器，以及用于切换发送和接收之间的连接以形成数据收集系统的切换单元或数据散射系统; 每个其他处理器具有用于临时存储要传送的数据的缓冲器或要接收的数据;传输控制单元，用于控制从缓冲器到公共总线的数据传输;接收控制单元，用于从所有数据中选择接收数据在公共总线上，用于将数据从缓冲器发送到公共总线的三态缓冲器，以及用于切换发送和接收之间的连接以形成数据收集系统或数据散射系统的切换单元，以及AND 用于获得处理器之间的数据传输或数据接收的一致性，并且用于向其他处理器发送用于数据传输或数据接收的命令。

7. 发明授权

US5278975A Synchronization control system in a parallel computer 失效
标题翻译：并行计算机中的同步控制系统
公开(公告)号：US5278975A
公开(公告)日：1994-01-11
申请号：US715583
申请日：1991-06-14
申请人： Hiroaki Ishihata , Morio Ikesaka , Takeshi Horie
发明人： Hiroaki Ishihata , Morio Ikesaka , Takeshi Horie
IPC分类号： G06F9/46 , G06F15/80 , G06F1/04
CPC分类号： G06F9/52 , G06F15/8007
摘要： An inter-processor synchronization control system in a distributed memory type parallel computer comprises a unit for detecting an establishment of the synchronization of all PEs, a status request register unit provided for each PE for independently issuing a status request through a status request signal, a unit for determining the issues of requests from status request registers of all PEs, a unit for distributing the determination to all PEs and a status detecting register for detecting the status according to the distributed determination and the output of the synchronization establishment detection unit. The inter-processor synchronous control system detects the status of all PEs when the synchronization is established in all PEs.
摘要翻译：分布式存储器型并行计算机中的处理器间同步控制系统包括用于检测所有PE的同步建立的单元，为每个PE提供的状态请求寄存器单元，用于通过状态请求信号独立地发出状态请求，用于确定所有PE的状态请求寄存器的请求的问题的单元，用于向所有PE分配确定的单元和用于根据同步建立检测单元的分布式确定和输出来检测状态的状态检测寄存器。当所有PE建立同步时，处理器间同步控制系统检测所有PE的状态。

8. 发明授权

US5675737A Message receiving system for use in parallel computer system 失效
标题翻译：用于并行计算机系统的消息接收系统
公开(公告)号：US5675737A
公开(公告)日：1997-10-07
申请号：US682478
申请日：1996-07-17
申请人： Takeshi Horie , Hiroaki Ishihata
发明人： Takeshi Horie , Hiroaki Ishihata
IPC分类号： G06F13/00 , G06F15/16 , G06F15/17 , G06F15/173
CPC分类号： G06F15/17
摘要： A message receiving method communicates a message among a plurality of computers in a parallel computer system, shortens a delay time in storing a received message in a user area of a memory, and realizes overlap between receipt of a message and execution by a processor. Each computer in the parallel computer system comprises a message buffer for temporarily storing the received message and a message handler for receiving a receive-a-message request from a processor of a computer to which it belongs. If the receive-a-message request arrives before the arrival of the message, the message handler directly transmits the received message to a user area specified by the receive-a-message request. During the transmission period, the message handler prevents the processor from accessing a portion in the user area to which the message has not been transmitted yet.
摘要翻译：消息接收方法在并行计算机系统中的多个计算机之间传送消息，缩短在存储器的用户区域中存储接收到的消息的延迟时间，并且实现消息的接收和处理器的执行之间的重叠。并行计算机系统中的每个计算机包括用于临时存储接收到的消息的消息缓冲器和用于从其所属的计算机的处理器接收接收消息请求的消息处理程序。如果接收消息请求在消息到达之前到达，则消息处理器将接收到的消息直接发送到由接收消息请求指定的用户区域。在传输期间，消息处理器防止处理器访问尚未发送消息的用户区域中的一部分。

9. 发明授权

US5157692A System for controlling communication between parallel computers 失效
标题翻译：控制并行计算机之间通信的系统
公开(公告)号：US5157692A
公开(公告)日：1992-10-20
申请号：US495987
申请日：1990-03-20
申请人： Takeshi Horie , Morio Ikesaka , Hiroaki Ishihata
发明人： Takeshi Horie , Morio Ikesaka , Hiroaki Ishihata
IPC分类号： G06F15/16 , G06F15/173 , G06F15/177 , G06F15/80
CPC分类号： G06F15/17368
摘要： A communication control system controls communication between parallel computers using a wormhole routing. The system comprises units for connecting a plurality of computer nodes by relay channels within a network to continuously transfer a message divided into a plurality of minimum data units for transmission. Storing units are provided in respective nodes for storing the minimum data units, the number of storing units corresponding to the number of relay channels from the originating node to the most remote node plus 1. Therefore, a deadlock in a communication is avoided, and a high speed communication can be realized.

10. 发明授权

US5604913A Vector processor having a mask register used for performing nested conditional instructions 失效
标题翻译：矢量处理器具有用于执行嵌套条件指令的掩码寄存器
公开(公告)号：US5604913A
公开(公告)日：1997-02-18
申请号：US237305
申请日：1994-05-03
申请人： Yoichi Koyanagi , Takeshi Horie
发明人： Yoichi Koyanagi , Takeshi Horie
IPC分类号： G06F9/32 , G06F9/38 , G06F15/78 , G06F17/16 , G06F15/347
CPC分类号： G06F17/16 , G06F15/8084 , G06F9/30036 , G06F9/30072 , G06F9/30094
摘要： In a computer equipped with a mask register in which is stored mask data indicating, for each array element, whether or not a statement such as an IF statement or an ELSE statement should be applied, the computer having a vector processor executing vector operation processing according to the mask data stored in the mask register, a first executing unit acquires first and second memory areas in which the mask data is saved in a stack formation. A second executing unit generates, when an IF statement appears in execution of a program, mask data indicating truth/falsity of a conditional expression of the IF statement, and saves the mask data indicating the truth/falsity of the conditional expression in the first memory area. A third executing unit reads latest mask data saved in the second memory area in synchronism with a process of the second executing unit. A fourth executing unit performs a bit-base logic operation on the mask data saved by the second executing unit and the mask data read by the third executing unit, stores mask data thus generated and applied to the IF statement in the mask register, and saves the above mask data applied to the above IF statement in the second memory area.
摘要翻译：在配备有掩码寄存器的计算机中，存储掩码数据，指示对于每个数组元素，是否应该应用诸如IF语句或ELSE语句的语句，具有向量处理器的计算机执行向量操作处理对于存储在掩码寄存器中的掩码数据，第一执行单元获取在堆栈形成中保存掩码数据的第一和第二存储区域。第二执行单元在执行程序时出现IF语句时，产生表示IF语句的条件表达式的真实/虚假的数据，并将表示条件表达式的真值/虚假的掩码数据保存在第一存储器中区。第三执行单元与第二执行单元的处理同步地读取保存在第二存储区域中的最新掩码数据。第四执行单元对由第二执行单元保存的掩码数据和由第三执行单元读取的掩码数据执行位基逻辑运算，将由此生成并应用于掩码寄存器中的IF语句的掩码数据存储，并保存上述掩码数据应用于第二存储区域中的上述IF语句。

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