专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07924885B2 Methods and apparatuses for circuit emulation multi-channel clock recovery 失效
标题翻译：电路仿真多通道时钟恢复的方法和装置
公开(公告)号：US07924885B2
公开(公告)日：2011-04-12
申请号：US11985859
申请日：2007-11-17
申请人： Moshe De-Leon , Ofer Kimelman
发明人： Moshe De-Leon , Ofer Kimelman
IPC分类号： H04J3/06
CPC分类号： H04J3/0632
摘要： A method and system for providing multi-channel circuit emulation clock recovery wherein a single instance of the clock recovery logic effects circuit emulation clock recovery for multiple channels. For one embodiment of the invention, fine tuning clocking is effected by comparing an outgoing clock with a recovered clock and switching a clock recovery mechanism, the switching performed in conjunction with a multi-channel context.
摘要翻译：一种用于提供多通道电路仿真时钟恢复的方法和系统，其中时钟恢复逻辑的单个实例影响多个通道的电路仿真时钟恢复。对于本发明的一个实施例，通过将输出时钟与恢复的时钟进行比较并切换时钟恢复机制，结合多信道上下文进行的切换来实现微调时钟。

2. 发明授权

US07324524B2 Pseudo synchronous machine 有权
标题翻译：伪同步机
公开(公告)号：US07324524B2
公开(公告)日：2008-01-29
申请号：US10284494
申请日：2002-10-29
申请人： Axel K. Kloth , Paul Bergantino , Moshe De-Leon , Daniel Fu , Stephen M. Mills , Jeremy Bicknell , Warner Andrews
发明人： Axel K. Kloth , Paul Bergantino , Moshe De-Leon , Daniel Fu , Stephen M. Mills , Jeremy Bicknell , Warner Andrews
IPC分类号： H04L12/56 , H04L12/44
CPC分类号： H04J3/0632 , Y10S370/907
摘要： A method and apparatus is disclosed for interfacing an asynchronous network with a synchronous network and in particular for efficiently utilizing available bandwidth of a synchronous network transmit opportunity. In one embodiment asynchronous traffic arrives via an asynchronous network at a network device, such as a switch, for transmission over a synchronous network. The traffic is parsed into cells and after switching, a reassembly unit is provided for processing one or more cells buckets. Write operations occur based on an ingress pointer while read operations are controlled by an egress pointer. Upon occurrence of a transmit opportunity on the synchronous network, the entire bandwidth of the transmit opportunity is utilized by loading awaiting cells from bucket memory on to the synchronous network. Sufficient cells are stored in memory between the memory locations identified by the ingress pointer and the egress pointer to insure total utilization of transmit opportunity bandwidth.
摘要翻译：公开了一种用于将异步网络与同步网络接口的方法和装置，特别是用于有效地利用同步网络发送机会的可用带宽。在一个实施例中，异步业务经由网络设备（例如交换机）上的异步网络来到达，用于通过同步网络传输。流量被解析为单元格，并且在切换之后，提供了用于处理一个或多个单元格桶的重组单元。写入操作基于入口指针发生，而读取操作由出口指针控制。在同步网络上发生发送机会时，通过将等待小区从桶存储器加载到同步网络来利用发送机会的整个带宽。足够的单元被存储在由入口指针和出口指针标识的存储器位置之间的存储器中，以确保发送机会带宽的总利用率。

3. 发明授权

US07286471B2 Dynamic bandwidth allocation for wide area networks 有权
标题翻译：广域网的动态带宽分配
公开(公告)号：US07286471B2
公开(公告)日：2007-10-23
申请号：US10106670
申请日：2002-03-23
申请人： Axel K. Kloth , Warner Andrews , Paul Bergantino , Jeremy Bicknell , Daniel Fu , Moshe De-Leon , Stephen M. Mills
发明人： Axel K. Kloth , Warner Andrews , Paul Bergantino , Jeremy Bicknell , Daniel Fu , Moshe De-Leon , Stephen M. Mills
IPC分类号： H04L12/66 , G06F15/173
CPC分类号： H04L47/822 , H04L41/0896 , H04L47/15 , H04L47/70 , H04L47/765 , H04L47/781
摘要： System and method for dynamically altering bandwidth allocation to each region serviced by a network. Each region is allocated an initial estimated bandwidth on the network and compares instantaneous demand against the allocation. When demand falls below the allocation, the region releases bandwidth so other regions can take advantage of that bandwidth. When demand exceeds the allocation, the region takes advantage of bandwidth released by other regions.
摘要翻译：用于动态地改变由网络服务的每个区域的带宽分配的系统和方法。每个区域在网络上分配初始估计带宽，并将瞬时需求与分配进行比较。当需求低于分配时，该区域释放带宽，以便其他区域可以利用该带宽。当需求超过分配时，该地区利用其他地区发布的带宽。

4. 发明授权

US5649110A Traffic shaping system with virtual circuit table time stamps for asynchronous transfer mode networks 失效
标题翻译：具有用于异步传输模式网络的虚拟电路表时间戳的流量整形系统
公开(公告)号：US5649110A
公开(公告)日：1997-07-15
申请号：US335281
申请日：1994-11-07
申请人： Michael Ben-Nun , Simoni Ben-Michael , Moshe De-Leon , Peter John Roman , Kadangode K. Ramakrishnan , G. Paul Koning
发明人： Michael Ben-Nun , Simoni Ben-Michael , Moshe De-Leon , Peter John Roman , Kadangode K. Ramakrishnan , G. Paul Koning
IPC分类号： H04L12/56 , G06F3/00
CPC分类号： H04L12/5602 , H04L2012/5679 , H04L2012/568
摘要： A system for controlling the transmission of cells from a network node over multiple virtual circuit is disclosed. The disclosed system performs traffic shaping for all virtual circuits connected with the network node. The system includes a virtual circuit table with one or more entries. Each virtual circuit table entry corresponds to a virtual circuit established with the network node. Each virtual circuit table further includes one or more Cell Rate Accumulator fields and a Time Stamp field. The system includes a schedule table having one or more entries. Each schedule table entry further includes one or more Cell Rate Accumulator fields and corresponding predetermined value fields. A schedule table loading process determines a virtual circuit on which a packet is to be transmitted, and then calculates a time elapsed since a last previous write of a virtual circuit table entry corresponding with that virtual circuit. The schedule table loading process then adds the time elapsed to the value of the Cell Rate Accumulator fields in that virtual circuit table entry, and stores the result of the addition into the corresponding Cell Rate Accumulator fields of the schedule table entry. The system further includes a process for periodically incrementing the Cell Rate Accumulator fields in the schedule table entry. A scanning process periodically increments the Cell Rate Accumulator fields. A transmitting process transmits a cell on the virtual circuit when the value of the Cell Rate Accumulator fields is greater than or equal to the corresponding predetermined values.
摘要翻译：公开了一种用于通过多个虚拟电路来控制来自网络节点的小区的传输的系统。所公开的系统对与网络节点连接的所有虚拟电路执行流量整形。该系统包括具有一个或多个条目的虚拟电路表。每个虚拟电路表条目对应于与网络节点建立的虚拟电路。每个虚拟电路表还包括一个或多个单元速率累加器字段和时间戳字段。该系统包括具有一个或多个条目的日程表。每个调度表条目还包括一个或多个信元速率累加器字段和对应的预定值字段。调度表加载过程确定要在其上发送分组的虚拟电路，然后计算自上一次写入与该虚拟电路相对应的虚拟电路表条目以来经过的时间。调度表加载过程然后将经过的时间加到该虚拟电路表条目中的单元速率累加器字段的值，并将相加的结果存储到调度表条目的相应的单元速率累加器字段中。系统还包括用于周期地增加调度表条目中的信元速率累加器字段的过程。扫描过程周期性地增加单元速率累加器字段。当小区费率累加器字段的值大于或等于相应的预定值时，发送处理在虚拟电路上发送小区。

5. 发明授权

US08228943B2 Systems and methods for providing framing mapping, muxing and data processing 失效
标题翻译：提供构图映射，复用和数据处理的系统和方法
公开(公告)号：US08228943B2
公开(公告)日：2012-07-24
申请号：US12074708
申请日：2008-03-05
申请人： Moshe De-Leon , Yuval Berger , Yehuda Kra , Barak Perlman
发明人： Moshe De-Leon , Yuval Berger , Yehuda Kra , Barak Perlman
IPC分类号： H04J3/22
CPC分类号： H04J3/047 , H04J3/1611 , H04J2203/0082 , H04J2203/0094
摘要： A method and system for providing Layer 1 time division multiplexing (TDM) framing, multiplexing, and mapping as well as Layer 2 data and protocol processing. One embodiment of the invention provides an integrated Layer1/Layer2 service aggregator within a single-device. Such an embodiment provides a complete System-on-Chip implementation for clear channel and deeply channelized OC-48 (STM-16), 4×OC12/3 (STM4/1) application of 2,000 channels or more. One embodiment implements functionality of Layer2 data and protocol processing as well as Layer1 TDM framing, multiplexing and mapping. For one embodiment, target applications include packet-based transport systems, multi-service access and metro systems, switches and routers and ADM/MSPP systems.
摘要翻译：一种用于提供第1层时分复用（TDM）成帧，复用和映射以及第2层数据和协议处理的方法和系统。本发明的一个实施例提供了在单个设备内的集成的Layer1 / Layer2服务聚合器。这样的实施例为2,000通道以上的清晰信道和深通道化OC-48（STM-16），4×OC12 / 3（STM4 / 1）应用提供了完整的片上系统实现。一个实施例实现了第2层数据和协议处理以及第1层TDM成帧，复用和映射的功能。对于一个实施例，目标应用包括基于分组的传输系统，多业务接入和城域系统，交换机和路由器以及ADM / MSPP系统。

6. 发明授权

US06868461B1 Link layer controller that provides a memory status signal to a network layer system in a communication device 有权
标题翻译：链路层控制器，其向通信设备中的网络层系统提供存储器状态信号
公开(公告)号：US06868461B1
公开(公告)日：2005-03-15
申请号：US09619736
申请日：2000-07-19
申请人： Reza Mirkhani , Moshe De-Leon , Samuel L. Spencer
发明人： Reza Mirkhani , Moshe De-Leon , Samuel L. Spencer
IPC分类号： G06F13/00 , H04L1/00 , H04L12/56 , H04L29/06 , H04L29/08
CPC分类号： H04L69/325 , H04L47/30 , H04L47/50 , H04L69/12 , H04L69/32 , H04L69/324
摘要： A link layer controller comprises a network layer interface, a physical layer interface, and a memory controller. The network layer interface exchanges packets with the network layer system and transfers a status signal to the network layer system. The physical layer interface exchanges the packets with the physical layer system. The memory controller exchanges the packets with the network layer interface, a memory, and the physical layer interface. The memory controller also generates the status signal to indicate available space in the memory.
摘要翻译：链路层控制器包括网络层接口，物理层接口和存储器控制器。网络层接口与网络层系统交换数据包，并将状态信号传送到网络层系统。物理层接口与物理层系统交换数据包。存储器控制器与网络层接口，存储器和物理层接口交换数据包。存储器控制器还产生状态信号以指示存储器中的可用空间。

7. 发明授权

US5606665A Buffer descriptor prefetch in network and I/O design 失效
标题翻译：网络缓存描述符预取和I / O设计
公开(公告)号：US5606665A
公开(公告)日：1997-02-25
申请号：US269595
申请日：1994-07-01
申请人： Henry S. Yang , Shirish S. Sathaye , Michael Ben-Nun , Moshe De-Leon , Simoni Ben-Michael
发明人： Henry S. Yang , Shirish S. Sathaye , Michael Ben-Nun , Moshe De-Leon , Simoni Ben-Michael
IPC分类号： H04L12/56 , H04L29/06 , G06F15/173 , H04L12/00
CPC分类号： H04L29/06 , H04L49/90
摘要： The invention improves the efficiency of buffer descriptor processing by performing descriptor prefetches, where multiple descriptors are read within the same descriptor bus transaction. The invention reads multiple buffer descriptors each time the bus is accessed. This allows for a smaller FIFO in a cut-through network adapter because it reduces the number of bus transactions needed to transfer data.
摘要翻译：本发明通过执行描述符预取来提高缓冲器描述符处理的效率，其中在同一描述符总线事务中读取多个描述符。每次访问总线时，本发明读取多个缓冲器描述符。这允许在直通网络适配器中使用较小的FIFO，因为它减少了传输数据所需的总线事务数量。

8. 发明申请

US20080225880A1 Systems and methods for providing framing mapping, muxing and data processing 失效
标题翻译：提供构图映射，复用和数据处理的系统和方法
公开(公告)号：US20080225880A1
公开(公告)日：2008-09-18
申请号：US12074708
申请日：2008-03-05
申请人： Moshe De-Leon , Yuval Berger , Yehuda Kra , Barak Perlman
发明人： Moshe De-Leon , Yuval Berger , Yehuda Kra , Barak Perlman
IPC分类号： H04L12/43
CPC分类号： H04J3/047 , H04J3/1611 , H04J2203/0082 , H04J2203/0094
摘要： A method and system for providing Layer 1 time division multiplexing (TDM) framing, multiplexing, and mapping as well as Layer 2 data and protocol processing. One embodiment of the invention provides an integrated Layer1/Layer2 service aggregator within a single-device. Such an embodiment provides a complete System-on-Chip implementation for clear channel and deeply channelized OC-48 (STM-16), 4×OC12/3 (STM4/1) application of 2,000 channels or more. One embodiment implements functionality of Layer2 data and protocol processing as well as Layer1 TDM framing, multiplexing and mapping. For one embodiment, target applications include packet-based transport systems, multi-service access and metro systems, switches and routers and ADM/MSPP systems.
摘要翻译：一种用于提供第1层时分复用（TDM）成帧，复用和映射以及第2层数据和协议处理的方法和系统。本发明的一个实施例提供了在单个设备内的集成的Layer1 / Layer2服务聚合器。这样的实施例为2,000通道以上的清晰信道和深通道化的OC-48（STM-16），4xOC12 / 3（STM4 / 1）应用提供了完整的片上系统实现。一个实施例实现了第2层数据和协议处理以及第1层TDM成帧，复用和映射的功能。对于一个实施例，目标应用包括基于分组的传输系统，多业务接入和城域系统，交换机和路由器以及ADM / MSPP系统。

9. 发明申请

US20080186999A1 Methods and apparatuses for circuit emulation multi-channel clock recovery 失效
标题翻译：电路仿真多通道时钟恢复的方法和装置
公开(公告)号：US20080186999A1
公开(公告)日：2008-08-07
申请号：US11985859
申请日：2007-11-17
申请人： Moshe De-Leon , Ofer Kimelman
发明人： Moshe De-Leon , Ofer Kimelman
IPC分类号： H04J3/22
CPC分类号： H04J3/0632
摘要： A method and system for providing multi-channel circuit emulation clock recovery wherein a single instance of the clock recovery logic effects circuit emulation clock recovery for multiple channels. For one embodiment of the invention, fine tuning clocking is effected by comparing an outgoing clock with a recovered clock and switching a clock recovery mechanism, the switching performed in conjunction with a multi-channel context.
摘要翻译：一种用于提供多通道电路仿真时钟恢复的方法和系统，其中时钟恢复逻辑的单个实例影响多个通道的电路仿真时钟恢复。对于本发明的一个实施例，通过将输出时钟与恢复的时钟进行比较并切换时钟恢复机制，结合多信道上下文进行的切换来实现微调时钟。

10. 发明授权

US07492825B2 Methods and apparatuses for processing data channels 失效
标题翻译：处理数据通道的方法和装置
公开(公告)号：US07492825B2
公开(公告)日：2009-02-17
申请号：US11490941
申请日：2006-07-21
申请人： Yehuda Kra , Yuval Berger , Moshe De-Leon , Barak Perlman
发明人： Yehuda Kra , Yuval Berger , Moshe De-Leon , Barak Perlman
IPC分类号： H04N7/12 , G06F11/00
CPC分类号： H04L49/90 , H04L69/12
摘要： A system and method for processing an extremely high data rate datastream. Embodiments of the invention provide methods for performing various operations on the datastream in order to map the datastream from one protocol to another as well as providing methods for processing multiple channels of a given protocol. For one embodiment of the invention a portion of a datastream is received to a stream buffer. A data stream window is then created from the received portion, the data stream window containing data of more than one protocol. A corresponding portion of the data of a same protocol, is accessed through each of a plurality of processing machines. The accessed data is concurrently processed at each of the processing machines.
摘要翻译：一种用于处理极高数据速率数据流的系统和方法。本发明的实施例提供了用于对数据流执行各种操作以便将数据流从一个协议映射到另一个协议以及提供用于处理给定协议的多个信道的方法的方法。对于本发明的一个实施例，数据流的一部分被接收到流缓冲器。然后从接收到的部分创建数据流窗口，数据流窗口包含多于一个协议的数据。相同协议的数据的相应部分通过多个处理机器中的每一个访问。访问的数据在每个处理机器上同时处理。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式