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1. 发明授权

US06573780B2 Four-phase charge pump with lower peak current 有权
标题翻译：具有较低峰值电流的四相电荷泵
公开(公告)号：US06573780B2
公开(公告)日：2003-06-03
申请号：US09355654
申请日：1999-08-02
申请人： Yu Shen Lin , Chun-Hsiung Hung , Ray-Lin Wan
发明人： Yu Shen Lin , Chun-Hsiung Hung , Ray-Lin Wan
IPC分类号： G05F110
CPC分类号： H02M3/073 , H02M2003/075
摘要： A four-phase charge pump circuit suitable for use on integrated circuits, such as flash memory devices, includes circuitry that drives charge pump nodes in two components separated by a time delay. The two components can be triggered by edges from the clocks that control the timing of the charge pump. Driving the charge pump nodes in two components separated by a delay decreases the peak current of the charge pump and improves noise characteristics of a voltage supply or ground line connected to the charge pump.
摘要翻译：适用于集成电路（例如闪存器件）的四相电荷泵电路包括驱动由时间延迟分开的两个部件中的电荷泵节点的电路。这两个组件可以由控制电荷泵定时的时钟边沿触发。驱动由延迟分开的两个部件中的电荷泵节点会降低电荷泵的峰值电流，并改善连接到电荷泵的电源或接地线的噪声特性。

2. 发明授权

US06493276B2 Word line boost circuit 有权
标题翻译：字线升压电路
公开(公告)号：US06493276B2
公开(公告)日：2002-12-10
申请号：US09355653
申请日：1999-08-02
申请人： Yu Shen Lin , Chun-Hsiung Hung , Ray-Lin Wan
发明人： Yu Shen Lin , Chun-Hsiung Hung , Ray-Lin Wan
IPC分类号： G11C700
CPC分类号： G11C8/08 , G11C5/145
摘要： An improved word line boost circuit suitable for use on integrated circuits such as flash memory devices includes a two step boosting circuit with a floating circuit node. A first circuit provides an initial boost of the output voltage from a precharged voltage. Part of the first circuit is floated, lessening a load on a second circuit. Then, the second circuit provides a second boost of the output voltage with increased power efficiency. A time delay separates the onset of the second boosting operation from the onset of the first boosting operation so as to define a two-step boost.
摘要翻译：适用于诸如闪存器件的集成电路的改进的字线升压电路包括具有浮动电路节点的两级升压电路。第一电路从预充电电压提供输出电压的初始升压。第一个电路的一部分浮起来，减轻了第二个电路的负载。然后，第二电路以提高的功率效率提供输出电压的第二升压。时间延迟将第二升压操作的开始与第一升压操作的开始分开，以便定义两步升压。

3. 发明授权

US6100557A Triple well charge pump 失效
标题翻译：三重充电泵
公开(公告)号：US6100557A
公开(公告)日：2000-08-08
申请号：US849561
申请日：1997-05-12
申请人： Chun-Hsiung Hung , Ray-Lin Wan , Yao-Wu Cheng
发明人： Chun-Hsiung Hung , Ray-Lin Wan , Yao-Wu Cheng
IPC分类号： H01L27/02 , H02M3/07 , H01L29/72
CPC分类号： H01L27/0222 , H02M3/073
摘要： An improved charge pump design is disclosed. This charge pump comprises at least one pumping transistor having a triple well arrangement. This triple pump transistor has a source and a drain region of a first conductive type formed on a first well having an opposite conductive type. A second well having the first conductive type is formed outside of the first well. The source region, first well and second well are set to substantially the same potential. One aspect of this configuration is that the first well forms a semiconductor diode with the drain region. Another aspect of this arrangement is that the body effect of the transistor is reduced. The reduction in body effect reduces the threshold voltage of the transistor. It is found that the above mentioned diode and threshold voltage reduction, singly and in combination, allow the charge pump to operate more efficiently.
摘要翻译： PCT No.PCT / US96 / 16317 Sec。 371日期：1997年5月12日 102（e）日期1997年5月12日PCT提交1996年10月10日PCT公布。公开号WO98 / 16010 PCT 日期：1998年4月16日公开了改进的电荷泵设计。该电荷泵包括具有三阱布置的至少一个泵浦晶体管。该三重泵晶体管具有形成在具有相反导电类型的第一阱上的第一导电类型的源区和漏区。具有第一导电类型的第二阱形成在第一阱的外部。源区，第一阱和第二阱被设定为基本上相同的电位。该结构的一个方面是第一阱与漏极区形成半导体二极管。这种布置的另一方面是晶体管的体效减小。身体效应的降低降低了晶体管的阈值电压。发现上述二极管和阈值电压降低，单独并且组合地允许电荷泵更有效地操作。

4. 发明授权

US5875152A Address transition detection circuit for a semiconductor memory capable of detecting narrowly spaced address changes 失效
标题翻译：用于能够检测窄间隔地址变化的半导体存储器的地址转换检测电路
公开(公告)号：US5875152A
公开(公告)日：1999-02-23
申请号：US751513
申请日：1996-11-15
申请人： Yin-Shang Liu , Kuen-Long Chang , Chun-Hsiung Hung , Weitong Chuang , Ray-Lin Wan
发明人： Yin-Shang Liu , Kuen-Long Chang , Chun-Hsiung Hung , Weitong Chuang , Ray-Lin Wan
IPC分类号： G11C11/41 , G11C7/22 , G11C8/18 , H03K5/1534 , G11C8/00 , H03K5/22
CPC分类号： H03K5/1534 , G11C7/22 , G11C8/18
摘要： The present invention provides a new (ATD) address transition detection circuit for use on an address bus having any number of address lines. An ATD circuit is disclosed which comprises a first and second circuit and an interval timer. The first circuit has a first and second input and an output. The first circuit receives, at the first input, a change signal corresponding to transitions in one or more addresses of an address bus. In response, the output of the first circuit transitions from an initial first state to a second state. The first circuit is also responsive to a reset command at the second input to return the output to the first state. The interval timer has an output coupled to the second input of the first circuit and an input. The interval timer responsive to an initialize command at the input initiates a timed interval and after the timed interval generates the reset command at the output. The second circuit has an output coupled to the input of the interval timer and an input. The second circuit responsive to the change signal at the input generates an initialize command at the output. The circuit provides a second state at the output of the first circuit, for all including the last received in a series of change signals. This assures that all address transitions have been detected before a memory access is allowed.
摘要翻译：本发明提供一种新的（ATD）地址转换检测电路，用于具有任意数量的地址线的地址总线。公开了一种包括第一和第二电路和间隔定时器的ATD电路。第一电路具有第一和第二输入和输出。第一电路在第一输入端接收对应于地址总线的一个或多个地址中的转变的改变信号。作为响应，第一电路的输出从初始第一状态转变到第二状态。第一电路还响应于第二输入端的复位命令将输出返回到第一状态。间隔定时器具有耦合到第一电路的第二输入和输入的输出。响应于输入的初始化命令的间隔定时器启动定时间隔，并且在定时间隔之后在输出端产生复位命令。第二电路具有耦合到间隔定时器和输入的输入的输出。响应于输入端的变化信号的第二电路在输出端产生初始化命令。该电路在第一电路的输出处提供第二状态，包括在一系列变化信号中最后接收的信号。这确保在允许存储器访问之前已经检测到所有地址转换。

5. 发明授权

US06219290B1 Memory cell sense amplifier 有权
标题翻译：存储单元读出放大器
公开(公告)号：US06219290B1
公开(公告)日：2001-04-17
申请号：US09172274
申请日：1998-10-14
申请人： Kuen-Long Chang , Chun-Hsiung Hung , Ken-Hui Chen , I-Long Lee , Yin-Shang Liu , Ray-Lin Wan
发明人： Kuen-Long Chang , Chun-Hsiung Hung , Ken-Hui Chen , I-Long Lee , Yin-Shang Liu , Ray-Lin Wan
IPC分类号： G11C702
CPC分类号： G11C7/062 , G11C7/067 , G11C7/12 , G11C16/28
摘要： A sensing circuit for sensing the logic state of a memory cell which minimizes read times is described which includes a first circuit branch corresponding to an array circuit path and a second circuit branch corresponding to a reference cell circuit path. In operation during the pre-decode interval, additional load and current generation circuitry are enabled in the first circuit path so that the voltage as seen by the sensing input of a sensing circuit comparator is driven to be essentially equivalent to that of the reference signal as established by the reference cell circuit path on the reference input of the sensing circuit comparator. Once the address has been decoded, the additional load circuitry is disabled so as to allow the sensing input of the comparator to transition to a voltage representative of the logic state stored in the memory cell.
摘要翻译：描述了用于感测最小化读取时间的存储单元的逻辑状态的感测电路，其包括对应于阵列电路路径的第一电路支路和对应于参考单元电路路径的第二电路支路。在预解码间隔期间的操作中，在第一电路路径中启用额外的负载和电流产生电路，使得感测电路比较器的感测输入所看到的电压被驱动为基本上等于参考信号的电压，如由参考单元电路路径建立在感测电路比较器的参考输入端上。一旦解码了地址，则禁用附加负载电路，以便允许比较器的感测输入转换到代表存储在存储单元中的逻辑状态的电压。

6. 发明授权

US5818764A Block-level wordline enablement to reduce negative wordline stress 失效
标题翻译：块级字词启用以减少负面字线压力
公开(公告)号：US5818764A
公开(公告)日：1998-10-06
申请号：US796821
申请日：1997-02-06
申请人： Tom D. Yiu , I-Long Lee , Kuen-Long Chang , Han-Sung Chen , Tzeng-Huei Shiau , Chun-Hsiung Hung , Ray-Lin Wan
发明人： Tom D. Yiu , I-Long Lee , Kuen-Long Chang , Han-Sung Chen , Tzeng-Huei Shiau , Chun-Hsiung Hung , Ray-Lin Wan
IPC分类号： G11C8/08 , G11C16/08 , G11C16/16 , G11C16/00
CPC分类号： G11C8/08 , G11C16/08 , G11C16/16
摘要： A circuit is provided for supplying a negative erasing voltage onto the wordlines of selected blocks in an array of floating gate memory cells. The circuit includes a voltage circuit, which has a plurality of local outputs, each of which connects to wordlines of an associated block of floating gate memory cells. A block selector circuit is coupled to the local outputs of the voltage circuit and selectively switches each of the local outputs to apply either an erasing voltage or a non-erasing voltage onto the wordlines of the associated block of floating gate memory cells. Negative wordline stress is thus reduced for wordlines of unselected blocks which receive a less negative, non-erasing voltage during block erase operations.
摘要翻译：提供电路，用于向浮动栅极存储单元阵列中的选定块的字线提供负的擦除电压。该电路包括具有多个本地输出的电压电路，每个本地输出连接到浮动栅极存储器单元的相关块的字线。块选择器电路耦合到电压电路的本地输出，并且选择性地切换每个本地输出以将擦除电压或非擦除电压施加到浮动栅极存储器单元的相关联块的字线上。因此，对于在块擦除操作期间接收到较小负的非擦除电压的未选择块的字线，负字线应力减小。

7. 发明授权

US6147910A Parallel read and verify for floating gate memory device 有权
标题翻译：并行读取和验证浮动栅极存储器件
公开(公告)号：US6147910A
公开(公告)日：2000-11-14
申请号：US386766
申请日：1999-08-31
申请人： Yu-Ming Hsu , Yin-Shang Liu , Chun-Hsiung Hung , Ray-Lin Wan , Y. T. Lin
发明人： Yu-Ming Hsu , Yin-Shang Liu , Chun-Hsiung Hung , Ray-Lin Wan , Y. T. Lin
IPC分类号： G11C11/56 , G11C16/10 , G11C16/34 , G11C16/06
CPC分类号： G11C16/3459 , G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C16/10 , G11C16/3454 , G11C2211/5621 , G11C2211/5624 , G11C2211/5642 , G11C7/1048
摘要： A page mode flash memory or floating gate memory device, including a page buffer based upon low current bit latches, and additional capabilities for parallel read and parallel program verify operations. The present device includes bit latch circuitry and/or method steps that facilitate such parallel operations and avoid data conflicts. Circuitry for separate read signals can serve to isolate the operations. Additionally, circuitry tied to the data verification signal can also be used. A diode type device can be used to isolate signal conditions that might indicate the cell does not need to be programmed. Bit-by-bit precharging of the bit lines can also be employed in order to save precharging power. Additionally, the large capacitance of the dataline might be used to delay discharging a particular dataline, and thereby allow a latch enabling signal to go high, thus eliminating the need for further isolation circuitry, or the like.
摘要翻译：页面模式闪速存储器或浮动栅极存储器件，包括基于低电流位锁存器的页面缓冲器，以及用于并行读取和并行程序验证操作的附加功能。本装置包括有利于这种并行操作并避免数据冲突的位锁存电路和/或方法步骤。用于单独读取信号的电路可用于隔离操作。此外，还可以使用与数据验证信号相关的电路。可以使用二极管类型的器件来隔离可能指示电池不需要编程的信号条件。为了节省预充电功率，也可以采用位线的逐位预充电。此外，数据线的大电容可能用于延迟放电特定数据线，从而允许锁存使能信号变高，从而不需要进一步的隔离电路等。

8. 发明授权

US5835414A Page mode program, program verify, read and erase verify for floating gate memory device with low current page buffer 失效
标题翻译：页面模式程序，使用低电流页面缓冲区的浮动存储器设备的程序验证，读取和擦除验证
公开(公告)号：US5835414A
公开(公告)日：1998-11-10
申请号：US718334
申请日：1996-10-01
申请人： Chun-Hsiung Hung , Ray-Lin Wan , Yu-Sui Lee
发明人： Chun-Hsiung Hung , Ray-Lin Wan , Yu-Sui Lee
IPC分类号： G11C7/10 , G11C11/56 , G11C16/10 , G11C16/34 , G11C16/06
CPC分类号： G11C16/3445 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/10 , G11C16/34 , G11C16/3459 , G11C7/1078 , G11C2211/5621 , G11C2211/5622 , G11C2211/5642 , G11C2216/14 , G11C7/1048
摘要： A page mode flash memory or floating gate memory device, includes a page buffer based on low current bit latches. The low current bit latches enable efficient program, program verify, read and erase verify processes during page mode operation. The array includes bit lines coupled with corresponding columns of cells in the array, and wordlines coupled with corresponding rows of cells in the array. Bit latches are coupled to respective bit lines to provide a page buffer. Control logic executes the steps of (1) setting a set of bit lines to a pre-charge voltage level (such as VDD or ground); (2) isolating the pre-charged bit line, applying a wordline voltage to the wordline of the page of cells to be sensed; and (3) responding to changes in the voltage levels of the bit lines (which are discharged if a memory cell is conductive) in response to the wordline voltage, to store a constant in the bit latches coupled to the bit lines on which the voltage levels of the bit lines passes a determinate threshold during the step of applying a wordline voltage. The bit lines are connected to the gate terminal of a pass transistor, so that when the turn on threshold of the pass transistor is passed on the bit line, the pass transistor if turned on, and the constant is loaded into the bit latch.
摘要翻译： PCT No.PCT / US96 / 10393 Sec。 371日期：1996年10月1日 102（e）1996年10月1日PCT PCT 1996年6月14日PCT公布。第WO97 / 48101号公报日期1997年12月18日页面模式闪存或浮动栅极存储器件，包括基于低电流位锁存器的页面缓冲器。低电流位锁存器可在页模式操作期间实现高效的程序，程序验证，读取和擦除验证过程。阵列包括与阵列中的单元格的相应列耦合的位线，以及与阵列中的相应单元格行耦合的字线。位锁存器耦合到相应的位线以提供页缓冲器。控制逻辑执行以下步骤：（1）将一组位线设置为预充电电压电平（例如VDD或地）; （2）隔离预充电位线，将字线电压施加到要感测的单元的页面的字线; 和（3）响应于字线电压响应于位线的电压电平的变化（如果存储器单元是导通的则它们被放电），以便在耦合到位线上的位锁存器中存储常数，在施加字线电压的步骤期间，位线的电平通过确定的阈值。位线连接到传输晶体管的栅极端子，使得当通过晶体管的导通阈值在位线上通过时，传输晶体管如果导通，并且常数被加载到位锁存器中。

9. 发明授权

US5748535A Advanced program verify for page mode flash memory 失效
标题翻译：高级程序验证页面模式闪存
公开(公告)号：US5748535A
公开(公告)日：1998-05-05
申请号：US612968
申请日：1996-03-04
申请人： Tien-Ler Lin , Kota Soejima , Jun Takahashi , Chun-Hsiung Hung , Kong-Mou Liou , Ray-Lin Wan
发明人： Tien-Ler Lin , Kota Soejima , Jun Takahashi , Chun-Hsiung Hung , Kong-Mou Liou , Ray-Lin Wan
IPC分类号： G11C16/04 , G11C16/32 , G11C16/34 , G11C7/00
CPC分类号： G11C16/3436 , G11C16/0491 , G11C16/32 , G11C16/3445 , G11C16/3459
摘要： Flash EEPROM cell and array designs, and methods for programming the same result in efficient and accurate programming of a flash EEPROM chip. The flash EEPROM chip comprises a memory array including at least M rows and N columns of flash EEPROM cells. M word lines are each coupled to the flash EEPROM cells in one of the M rows of flash EEPROM cells. A plurality of bit lines are each coupled to the flash EEPROM cells in one of the N columns of flash EEPROM cells. A page buffer coupled to the plurality of bit lines supplies input data to N columns of flash EEPROM cells. Write control circuitry supplies programming voltages for programming input data to the flash EEPROM cells in response to the input data stored in the data input buffer. Verify circuitry automatically verifies programming of the page by resetting bits in the page buffer for each cell which passes.
摘要翻译： PCT No.PCT / US95 / 00077 Sec。 371日期：1996年3月4日 102（e）1996年3月4日PCT PCT 1995年1月5日PCT公布。公开号WO96 / 21227 日期1996年7月11日闪存EEPROM单元和阵列设计以及用于编程相同结果的快速EEPROM芯片的高效准确编程的方法。快闪EEPROM芯片包括至少包括M行和N列快闪EEPROM单元的存储器阵列。 M个字线各自耦合到M行的快闪EEPROM单元之一中的快闪EEPROM单元。多个位线各自耦合到快速EEPROM单元的N列之一中的快闪EEPROM单元。耦合到多个位线的页缓冲器将快速EEPROM单元的输入数据提供给N列。响应于存储在数据输入缓冲器中的输入数据，写控制电路提供用于将输入数据编程到闪存EEPROM单元的编程电压。验证电路通过复位通过的每个单元的页面缓冲区中的位来自动验证页面的编程。

10. 发明授权

US5699298A Flash memory erase with controlled band-to-band tunneling current 失效
标题翻译：具有受控的带对隧道电流的闪存擦除
公开(公告)号：US5699298A
公开(公告)日：1997-12-16
申请号：US718525
申请日：1996-10-07
申请人： Tzeng-Huei Shiau , Ray-Lin Wan , Yuan-Chang Liu , Chun-Hsiung Hung , Weitong Chuang , Han Sung Chen , Fuchia Shone
发明人： Tzeng-Huei Shiau , Ray-Lin Wan , Yuan-Chang Liu , Chun-Hsiung Hung , Weitong Chuang , Han Sung Chen , Fuchia Shone
IPC分类号： G11C16/16 , G11C16/30 , G11C16/00
CPC分类号： G11C16/3445 , G11C16/16 , G11C16/30
摘要： Substantial reduction in peak current encountered during an erase process for a flash memory device is achieved by selection of source voltage potential during the erase according to the expected band-to-band tunneling current encountered during the process. During the beginning of the process, a lower source voltage potential is selected, which is high enough to cause significant erasing while suppressing band-to-band tunneling current in a portion of the array, and during a second part of the erasing process, a higher source potential is utilized, which ensures successful erasing of the array, without exceeding the peak current requirements of the power supply used with the device. The first and second parts of the erase sequence will induce band-to-band tunneling current in addition to Fowler-Nordheim tunneling current. The band-to-band tunneling current is characterized by a turn on threshold source potential which is inversely related to the threshold of the cell receiving the voltage sequence. The source voltage used in the first part of the erase sequence is set at level that is near or above the turn on threshold source potential for higher threshold cells that are in the high threshold state, but less than the turn on threshold source potential for lower threshold cells in the high threshold state. The source potential in the second part is set at level which is near or above the turn on threshold source potential for lower threshold cells in the high threshold state.
摘要翻译： PCT No.PCT / US96 / 07490 Sec。 371日期1996年10月7日第 102（e）1996年10月7日PCT 1996年5月22日提交闪速存储器件的擦除过程中遇到的峰值电流的实质性降低是通过根据预期的带 - 带来在擦除期间选择源极电压电位来实现的过程中遇到的隧道电流。在该过程开始时，选择较低的源极电压电位，其足够高以引起显着擦除，同时抑制阵列的一部分中的带间隧穿电流，并且在擦除处理的第二部分期间，利用更高的源极电位，确保阵列的成功擦除，而不超过与器件一起使用的电源的峰值电流要求。擦除序列的第一部分和第二部分除了Fowler-Nordheim隧道电流之外还将引起带间隧穿电流。带 - 带隧穿电流的特征在于开启阈值源极电位，其与接收电压序列的电池的阈值成反比。在擦除序列的第一部分中使用的源电压被设置为接近或高于处于高阈值状态的较高阈值电池的阈值源极电位的接通或高于电平，但小于阈值源电位的导通电平较低阈值细胞处于高阈值状态。第二部分中的源极电位被设置在接近或高于阈值电位的阈值源电位的接通或高于在高阈值状态下的较低阈值电池的电位。

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